| blob | 67072df39bc7453eaf2d182bc6190d05b8c2a3a7 |
1 &l4_abe { /* 0x40100000 */
2 compatible = "ti,omap4-l4-abe", "simple-bus";
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
5 reg-names = "la", "ap";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
9 <0x49000000 0x49000000 0x100000>;
10 segment@0 { /* 0x40100000 */
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges =
15 /* CPU to L4 ABE mapping */
16 <0x00000000 0x00000000 0x000400>, /* ap 0 */
17 <0x00000400 0x00000400 0x000400>, /* ap 1 */
18 <0x00022000 0x00022000 0x001000>, /* ap 2 */
19 <0x00023000 0x00023000 0x001000>, /* ap 3 */
20 <0x00024000 0x00024000 0x001000>, /* ap 4 */
21 <0x00025000 0x00025000 0x001000>, /* ap 5 */
22 <0x00026000 0x00026000 0x001000>, /* ap 6 */
23 <0x00027000 0x00027000 0x001000>, /* ap 7 */
24 <0x00028000 0x00028000 0x001000>, /* ap 8 */
25 <0x00029000 0x00029000 0x001000>, /* ap 9 */
26 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
27 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
28 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
29 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
30 <0x00030000 0x00030000 0x001000>, /* ap 14 */
31 <0x00031000 0x00031000 0x001000>, /* ap 15 */
32 <0x00032000 0x00032000 0x001000>, /* ap 16 */
33 <0x00033000 0x00033000 0x001000>, /* ap 17 */
34 <0x00038000 0x00038000 0x001000>, /* ap 18 */
35 <0x00039000 0x00039000 0x001000>, /* ap 19 */
36 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
37 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
38 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
39 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
40 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
41 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
42 <0x00080000 0x00080000 0x010000>, /* ap 26 */
43 <0x00080000 0x00080000 0x001000>, /* ap 27 */
44 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
45 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
46 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
47 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
48 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
49 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
51 /* L3 to L4 ABE mapping */
52 <0x49000000 0x49000000 0x000400>, /* ap 0 */
53 <0x49000400 0x49000400 0x000400>, /* ap 1 */
54 <0x49022000 0x49022000 0x001000>, /* ap 2 */
55 <0x49023000 0x49023000 0x001000>, /* ap 3 */
56 <0x49024000 0x49024000 0x001000>, /* ap 4 */
57 <0x49025000 0x49025000 0x001000>, /* ap 5 */
58 <0x49026000 0x49026000 0x001000>, /* ap 6 */
59 <0x49027000 0x49027000 0x001000>, /* ap 7 */
60 <0x49028000 0x49028000 0x001000>, /* ap 8 */
61 <0x49029000 0x49029000 0x001000>, /* ap 9 */
62 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
63 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
64 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
65 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
66 <0x49030000 0x49030000 0x001000>, /* ap 14 */
67 <0x49031000 0x49031000 0x001000>, /* ap 15 */
68 <0x49032000 0x49032000 0x001000>, /* ap 16 */
69 <0x49033000 0x49033000 0x001000>, /* ap 17 */
70 <0x49038000 0x49038000 0x001000>, /* ap 18 */
71 <0x49039000 0x49039000 0x001000>, /* ap 19 */
72 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
73 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
74 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
75 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
76 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
77 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
78 <0x49080000 0x49080000 0x010000>, /* ap 26 */
79 <0x49080000 0x49080000 0x001000>, /* ap 27 */
80 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
81 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
82 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
83 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
84 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
85 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
87 target-module@22000 { /* 0x40122000, ap 2 02.0 */
88 compatible = "ti,sysc-omap2", "ti,sysc";
89 ti,hwmods = "mcbsp1";
90 reg = <0x2208c 0x4>;
91 reg-names = "sysc";
92 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
93 SYSC_OMAP2_ENAWAKEUP |
94 SYSC_OMAP2_SOFTRESET)>;
95 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
96 <SYSC_IDLE_NO>,
97 <SYSC_IDLE_SMART>;
98 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
99 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
100 clock-names = "fck";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0x0 0x22000 0x1000>,
104 <0x49022000 0x49022000 0x1000>;
106 mcbsp1: mcbsp@0 {
107 compatible = "ti,omap4-mcbsp";
108 reg = <0x0 0xff>, /* MPU private access */
109 <0x49022000 0xff>; /* L3 Interconnect */
110 reg-names = "mpu", "dma";
111 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "common";
113 ti,buffer-size = <128>;
114 dmas = <&sdma 33>,
115 <&sdma 34>;
116 dma-names = "tx", "rx";
117 status = "disabled";
118 };
119 };
121 target-module@24000 { /* 0x40124000, ap 4 04.0 */
122 compatible = "ti,sysc-omap2", "ti,sysc";
123 ti,hwmods = "mcbsp2";
124 reg = <0x2408c 0x4>;
125 reg-names = "sysc";
126 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
127 SYSC_OMAP2_ENAWAKEUP |
128 SYSC_OMAP2_SOFTRESET)>;
129 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
130 <SYSC_IDLE_NO>,
131 <SYSC_IDLE_SMART>;
132 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
133 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
134 clock-names = "fck";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0x0 0x24000 0x1000>,
138 <0x49024000 0x49024000 0x1000>;
140 mcbsp2: mcbsp@0 {
141 compatible = "ti,omap4-mcbsp";
142 reg = <0x0 0xff>, /* MPU private access */
143 <0x49024000 0xff>; /* L3 Interconnect */
144 reg-names = "mpu", "dma";
145 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "common";
147 ti,buffer-size = <128>;
148 dmas = <&sdma 17>,
149 <&sdma 18>;
150 dma-names = "tx", "rx";
151 status = "disabled";
152 };
153 };
155 target-module@26000 { /* 0x40126000, ap 6 06.0 */
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 ti,hwmods = "mcbsp3";
158 reg = <0x2608c 0x4>;
159 reg-names = "sysc";
160 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
161 SYSC_OMAP2_ENAWAKEUP |
162 SYSC_OMAP2_SOFTRESET)>;
163 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
164 <SYSC_IDLE_NO>,
165 <SYSC_IDLE_SMART>;
166 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
167 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
168 clock-names = "fck";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x26000 0x1000>,
172 <0x49026000 0x49026000 0x1000>;
174 mcbsp3: mcbsp@0 {
175 compatible = "ti,omap4-mcbsp";
176 reg = <0x0 0xff>, /* MPU private access */
177 <0x49026000 0xff>; /* L3 Interconnect */
178 reg-names = "mpu", "dma";
179 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "common";
181 ti,buffer-size = <128>;
182 dmas = <&sdma 19>,
183 <&sdma 20>;
184 dma-names = "tx", "rx";
185 status = "disabled";
186 };
187 };
189 target-module@28000 { /* 0x40128000, ap 8 08.0 */
190 compatible = "ti,sysc-mcasp", "ti,sysc";
191 ti,hwmods = "mcasp";
192 reg = <0x28000 0x4>,
193 <0x28004 0x4>;
194 reg-names = "rev", "sysc";
195 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
196 <SYSC_IDLE_NO>,
197 <SYSC_IDLE_SMART>,
198 <SYSC_IDLE_SMART_WKUP>;
199 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
200 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
201 clock-names = "fck";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 ranges = <0x0 0x28000 0x1000>,
205 <0x49028000 0x49028000 0x1000>;
207 /*
208 * Child device unsupported by davinci-mcasp. At least
209 * RX path is disabled for omap4, and only DIT mode
210 * works with no I2S. See also old Android kernel
211 * omap-mcasp driver for more information.
212 */
213 };
215 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
216 compatible = "ti,sysc";
217 status = "disabled";
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges = <0x0 0x2a000 0x1000>,
221 <0x4902a000 0x4902a000 0x1000>;
222 };
224 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
225 compatible = "ti,sysc-omap4", "ti,sysc";
226 ti,hwmods = "dmic";
227 reg = <0x2e000 0x4>,
228 <0x2e010 0x4>;
229 reg-names = "rev", "sysc";
230 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
231 SYSC_OMAP4_SOFTRESET)>;
232 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
233 <SYSC_IDLE_NO>,
234 <SYSC_IDLE_SMART>,
235 <SYSC_IDLE_SMART_WKUP>;
236 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
237 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
238 clock-names = "fck";
239 #address-cells = <1>;
240 #size-cells = <1>;
241 ranges = <0x0 0x2e000 0x1000>,
242 <0x4902e000 0x4902e000 0x1000>;
244 dmic: dmic@0 {
245 compatible = "ti,omap4-dmic";
246 reg = <0x0 0x7f>, /* MPU private access */
247 <0x4902e000 0x7f>; /* L3 Interconnect */
248 reg-names = "mpu", "dma";
249 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
250 dmas = <&sdma 67>;
251 dma-names = "up_link";
252 status = "disabled";
253 };
254 };
256 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
257 compatible = "ti,sysc-omap2", "ti,sysc";
258 ti,hwmods = "wd_timer3";
259 reg = <0x30000 0x4>,
260 <0x30010 0x4>,
261 <0x30014 0x4>;
262 reg-names = "rev", "sysc", "syss";
263 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
264 SYSC_OMAP2_SOFTRESET)>;
265 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_NO>,
267 <SYSC_IDLE_SMART>,
268 <SYSC_IDLE_SMART_WKUP>;
269 ti,syss-mask = <1>;
270 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
271 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
272 clock-names = "fck";
273 #address-cells = <1>;
274 #size-cells = <1>;
275 ranges = <0x0 0x30000 0x1000>,
276 <0x49030000 0x49030000 0x1000>;
278 wdt3: wdt@0 {
279 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
280 reg = <0x0 0x80>;
281 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
282 };
283 };
285 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
286 compatible = "ti,sysc-omap4", "ti,sysc";
287 ti,hwmods = "mcpdm";
288 reg = <0x32000 0x4>,
289 <0x32010 0x4>;
290 reg-names = "rev", "sysc";
291 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
292 SYSC_OMAP4_SOFTRESET)>;
293 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
294 <SYSC_IDLE_NO>,
295 <SYSC_IDLE_SMART>,
296 <SYSC_IDLE_SMART_WKUP>;
297 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
298 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
299 clock-names = "fck";
300 #address-cells = <1>;
301 #size-cells = <1>;
302 ranges = <0x0 0x32000 0x1000>,
303 <0x49032000 0x49032000 0x1000>;
305 /* Must be only enabled for boards with pdmclk wired */
306 status = "disabled";
308 mcpdm: mcpdm@0 {
309 compatible = "ti,omap4-mcpdm";
310 reg = <0x0 0x7f>, /* MPU private access */
311 <0x49032000 0x7f>; /* L3 Interconnect */
312 reg-names = "mpu", "dma";
313 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
314 dmas = <&sdma 65>,
315 <&sdma 66>;
316 dma-names = "up_link", "dn_link";
317 };
318 };
320 target-module@38000 { /* 0x40138000, ap 18 12.0 */
321 compatible = "ti,sysc-omap4-timer", "ti,sysc";
322 ti,hwmods = "timer5";
323 reg = <0x38000 0x4>,
324 <0x38010 0x4>;
325 reg-names = "rev", "sysc";
326 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
327 SYSC_OMAP4_SOFTRESET)>;
328 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
329 <SYSC_IDLE_NO>,
330 <SYSC_IDLE_SMART>,
331 <SYSC_IDLE_SMART_WKUP>;
332 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
333 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
334 clock-names = "fck";
335 #address-cells = <1>;
336 #size-cells = <1>;
337 ranges = <0x0 0x38000 0x1000>,
338 <0x49038000 0x49038000 0x1000>;
340 timer5: timer@0 {
341 compatible = "ti,omap4430-timer";
342 reg = <0x00000000 0x80>,
343 <0x49038000 0x80>;
344 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
345 clock-names = "fck";
346 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
347 ti,timer-dsp;
348 };
349 };
351 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
352 compatible = "ti,sysc-omap4-timer", "ti,sysc";
353 ti,hwmods = "timer6";
354 reg = <0x3a000 0x4>,
355 <0x3a010 0x4>;
356 reg-names = "rev", "sysc";
357 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
358 SYSC_OMAP4_SOFTRESET)>;
359 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
360 <SYSC_IDLE_NO>,
361 <SYSC_IDLE_SMART>,
362 <SYSC_IDLE_SMART_WKUP>;
363 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
364 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
365 clock-names = "fck";
366 #address-cells = <1>;
367 #size-cells = <1>;
368 ranges = <0x0 0x3a000 0x1000>,
369 <0x4903a000 0x4903a000 0x1000>;
371 timer6: timer@0 {
372 compatible = "ti,omap4430-timer";
373 reg = <0x00000000 0x80>,
374 <0x4903a000 0x80>;
375 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
376 clock-names = "fck";
377 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
378 ti,timer-dsp;
379 };
380 };
382 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
383 compatible = "ti,sysc-omap4-timer", "ti,sysc";
384 ti,hwmods = "timer7";
385 reg = <0x3c000 0x4>,
386 <0x3c010 0x4>;
387 reg-names = "rev", "sysc";
388 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
389 SYSC_OMAP4_SOFTRESET)>;
390 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
391 <SYSC_IDLE_NO>,
392 <SYSC_IDLE_SMART>,
393 <SYSC_IDLE_SMART_WKUP>;
394 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
395 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
396 clock-names = "fck";
397 #address-cells = <1>;
398 #size-cells = <1>;
399 ranges = <0x0 0x3c000 0x1000>,
400 <0x4903c000 0x4903c000 0x1000>;
402 timer7: timer@0 {
403 compatible = "ti,omap4430-timer";
404 reg = <0x00000000 0x80>,
405 <0x4903c000 0x80>;
406 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
407 clock-names = "fck";
408 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
409 ti,timer-dsp;
410 };
411 };
413 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
414 compatible = "ti,sysc-omap4-timer", "ti,sysc";
415 ti,hwmods = "timer8";
416 reg = <0x3e000 0x4>,
417 <0x3e010 0x4>;
418 reg-names = "rev", "sysc";
419 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
420 SYSC_OMAP4_SOFTRESET)>;
421 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
422 <SYSC_IDLE_NO>,
423 <SYSC_IDLE_SMART>,
424 <SYSC_IDLE_SMART_WKUP>;
425 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
426 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
427 clock-names = "fck";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0x3e000 0x1000>,
431 <0x4903e000 0x4903e000 0x1000>;
433 timer8: timer@0 {
434 compatible = "ti,omap4430-timer";
435 reg = <0x00000000 0x80>,
436 <0x4903e000 0x80>;
437 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
438 clock-names = "fck";
439 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
440 ti,timer-pwm;
441 ti,timer-dsp;
442 };
443 };
445 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
446 compatible = "ti,sysc";
447 status = "disabled";
448 #address-cells = <1>;
449 #size-cells = <1>;
450 ranges = <0x0 0x80000 0x10000>,
451 <0x49080000 0x49080000 0x10000>;
452 };
454 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
455 compatible = "ti,sysc";
456 status = "disabled";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 ranges = <0x0 0xa0000 0x10000>,
460 <0x490a0000 0x490a0000 0x10000>;
461 };
463 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
464 compatible = "ti,sysc";
465 status = "disabled";
466 #address-cells = <1>;
467 #size-cells = <1>;
468 ranges = <0x0 0xc0000 0x10000>,
469 <0x490c0000 0x490c0000 0x10000>;
470 };
472 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
473 compatible = "ti,sysc-omap4", "ti,sysc";
474 ti,hwmods = "aess";
475 reg = <0xf1000 0x4>,
476 <0xf1010 0x4>;
477 reg-names = "rev", "sysc";
478 ti,sysc-midle = <SYSC_IDLE_FORCE>,
479 <SYSC_IDLE_NO>,
480 <SYSC_IDLE_SMART>,
481 <SYSC_IDLE_SMART_WKUP>;
482 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
483 <SYSC_IDLE_NO>,
484 <SYSC_IDLE_SMART>;
485 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
486 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
487 clock-names = "fck";
488 #address-cells = <1>;
489 #size-cells = <1>;
490 ranges = <0x0 0xf1000 0x1000>,
491 <0x490f1000 0x490f1000 0x1000>;
493 /*
494 * No child device binding or driver in mainline.
495 * See Android tree and related upstreaming efforts
496 * for the old driver.
497 */
498 };
499 };
500 };