arch/arm/boot/dts/rk3288-veyron-jaq.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Jaq Rev 1+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "rk3288-veyron-chromebook.dtsi"
  11 #include "cros-ec-sbs.dtsi"
  12
  13 / {
  14         model = "Google Jaq";
  15         compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
  16                      "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
  17                      "google,veyron-jaq-rev1", "google,veyron-jaq",
  18                      "google,veyron", "rockchip,rk3288";
  19
  20         panel_regulator: panel-regulator {
  21                 compatible = "regulator-fixed";
  22                 enable-active-high;
  23                 gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&lcd_enable_h>;
  26                 regulator-name = "panel_regulator";
  27                 startup-delay-us = <100000>;
  28                 vin-supply = <&vcc33_sys>;
  29         };
  30
  31         vcc18_lcd: vcc18-lcd {
  32                 compatible = "regulator-fixed";
  33                 enable-active-high;
  34                 gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&avdd_1v8_disp_en>;
  37                 regulator-name = "vcc18_lcd";
  38                 regulator-always-on;
  39                 regulator-boot-on;
  40                 vin-supply = <&vcc18_wl>;
  41         };
  42
  43         backlight_regulator: backlight-regulator {
  44                 compatible = "regulator-fixed";
  45                 enable-active-high;
  46                 gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&bl_pwr_en>;
  49                 regulator-name = "backlight_regulator";
  50                 vin-supply = <&vcc33_sys>;
  51                 startup-delay-us = <15000>;
  52         };
  53 };
  54
  55 &backlight {
  56         /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
  57         brightness-levels = <
  58                   0
  59                   8   9  10  11  12  13  14  15
  60                  16  17  18  19  20  21  22  23
  61                  24  25  26  27  28  29  30  31
  62                  32  33  34  35  36  37  38  39
  63                  40  41  42  43  44  45  46  47
  64                  48  49  50  51  52  53  54  55
  65                  56  57  58  59  60  61  62  63
  66                  64  65  66  67  68  69  70  71
  67                  72  73  74  75  76  77  78  79
  68                  80  81  82  83  84  85  86  87
  69                  88  89  90  91  92  93  94  95
  70                  96  97  98  99 100 101 102 103
  71                 104 105 106 107 108 109 110 111
  72                 112 113 114 115 116 117 118 119
  73                 120 121 122 123 124 125 126 127
  74                 128 129 130 131 132 133 134 135
  75                 136 137 138 139 140 141 142 143
  76                 144 145 146 147 148 149 150 151
  77                 152 153 154 155 156 157 158 159
  78                 160 161 162 163 164 165 166 167
  79                 168 169 170 171 172 173 174 175
  80                 176 177 178 179 180 181 182 183
  81                 184 185 186 187 188 189 190 191
  82                 192 193 194 195 196 197 198 199
  83                 200 201 202 203 204 205 206 207
  84                 208 209 210 211 212 213 214 215
  85                 216 217 218 219 220 221 222 223
  86                 224 225 226 227 228 229 230 231
  87                 232 233 234 235 236 237 238 239
  88                 240 241 242 243 244 245 246 247
  89                 248 249 250 251 252 253 254 255>;
  90         power-supply = <&backlight_regulator>;
  91 };
  92
  93 &panel {
  94         power-supply = <&panel_regulator>;
  95 };
  96
  97 &rk808 {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
 100         dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
 101                     <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
 102
 103         regulators {
 104                 mic_vcc: LDO_REG2 {
 105                         regulator-name = "mic_vcc";
 106                         regulator-always-on;
 107                         regulator-boot-on;
 108                         regulator-min-microvolt = <1800000>;
 109                         regulator-max-microvolt = <1800000>;
 110                         regulator-state-mem {
 111                                 regulator-off-in-suspend;
 112                         };
 113                 };
 114         };
 115 };
 116
 117 &sdmmc {
 118         disable-wp;
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
 121                         &sdmmc_bus4>;
 122 };
 123
 124 &vcc_5v {
 125         enable-active-high;
 126         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&drv_5v>;
 129 };
 130
 131 &vcc50_hdmi {
 132         enable-active-high;
 133         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&vcc50_hdmi_en>;
 136 };
 137
 138 &gpio0 {
 139         gpio-line-names = "PMIC_SLEEP_AP",
 140                           "DDRIO_PWROFF",
 141                           "DDRIO_RETEN",
 142                           "TS3A227E_INT_L",
 143                           "PMIC_INT_L",
 144                           "PWR_KEY_L",
 145                           "AP_LID_INT_L",
 146                           "EC_IN_RW",
 147
 148                           "AC_PRESENT_AP",
 149                           /*
 150                            * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
 151                            * it REC_MODE_L.
 152                            */
 153                           "RECOVERY_SW_L",
 154                           "OTP_OUT",
 155                           "HOST1_PWR_EN",
 156                           "USBOTG_PWREN_H",
 157                           "AP_WARM_RESET_H",
 158                           "nFALUT2",
 159                           "I2C0_SDA_PMIC",
 160
 161                           "I2C0_SCL_PMIC",
 162                           "SUSPEND_L",
 163                           "USB_INT";
 164 };
 165
 166 &gpio2 {
 167         gpio-line-names = "CONFIG0",
 168                           "CONFIG1",
 169                           "CONFIG2",
 170                           "",
 171                           "",
 172                           "",
 173                           "",
 174                           "CONFIG3",
 175
 176                           "",
 177                           "EMMC_RST_L",
 178                           "",
 179                           "",
 180                           "BL_PWR_EN",
 181                           "AVDD_1V8_DISP_EN";
 182 };
 183
 184 &gpio3 {
 185         gpio-line-names = "FLASH0_D0",
 186                           "FLASH0_D1",
 187                           "FLASH0_D2",
 188                           "FLASH0_D3",
 189                           "FLASH0_D4",
 190                           "FLASH0_D5",
 191                           "FLASH0_D6",
 192                           "FLASH0_D7",
 193
 194                           "",
 195                           "",
 196                           "",
 197                           "",
 198                           "",
 199                           "",
 200                           "",
 201                           "",
 202
 203                           "FLASH0_CS2/EMMC_CMD",
 204                           "",
 205                           "FLASH0_DQS/EMMC_CLKO";
 206 };
 207
 208 &gpio4 {
 209         gpio-line-names = "",
 210                           "",
 211                           "",
 212                           "",
 213                           "",
 214                           "",
 215                           "",
 216                           "",
 217
 218                           "",
 219                           "",
 220                           "",
 221                           "",
 222                           "",
 223                           "",
 224                           "",
 225                           "",
 226
 227                           "UART0_RXD",
 228                           "UART0_TXD",
 229                           "UART0_CTS",
 230                           "UART0_RTS",
 231                           "SDIO0_D0",
 232                           "SDIO0_D1",
 233                           "SDIO0_D2",
 234                           "SDIO0_D3",
 235
 236                           "SDIO0_CMD",
 237                           "SDIO0_CLK",
 238                           "BT_DEV_WAKE",        /* Maybe missing from mighty? */
 239                           "",
 240                           "WIFI_ENABLE_H",
 241                           "BT_ENABLE_L",
 242                           "WIFI_HOST_WAKE",
 243                           "BT_HOST_WAKE";
 244 };
 245
 246 &gpio5 {
 247         gpio-line-names = "",
 248                           "",
 249                           "",
 250                           "",
 251                           "",
 252                           "",
 253                           "",
 254                           "",
 255
 256                           "",
 257                           "",
 258                           "",
 259                           "",
 260                           "SPI0_CLK",
 261                           "SPI0_CS0",
 262                           "SPI0_TXD",
 263                           "SPI0_RXD",
 264
 265                           "",
 266                           "",
 267                           "",
 268                           "VCC50_HDMI_EN";
 269 };
 270
 271 &gpio6 {
 272         gpio-line-names = "I2S0_SCLK",
 273                           "I2S0_LRCK_RX",
 274                           "I2S0_LRCK_TX",
 275                           "I2S0_SDI",
 276                           "I2S0_SDO0",
 277                           "HP_DET_H",
 278                           "ALS_INT",
 279                           "INT_CODEC",
 280
 281                           "I2S0_CLK",
 282                           "I2C2_SDA",
 283                           "I2C2_SCL",
 284                           "MICDET",
 285                           "",
 286                           "",
 287                           "",
 288                           "",
 289
 290                           "SDMMC_D0",
 291                           "SDMMC_D1",
 292                           "SDMMC_D2",
 293                           "SDMMC_D3",
 294                           "SDMMC_CLK",
 295                           "SDMMC_CMD";
 296 };
 297
 298 &gpio7 {
 299         gpio-line-names = "LCDC_BL",
 300                           "PWM_LOG",
 301                           "BL_EN",
 302                           "TRACKPAD_INT",
 303                           "TPM_INT_H",
 304                           "SDMMC_DET_L",
 305                           /*
 306                            * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
 307                            * it FW_WP_AP.
 308                            */
 309                           "AP_FLASH_WP_L",
 310                           "EC_INT",
 311
 312                           "CPU_NMI",
 313                           "DVSOK",
 314                           "SDMMC_WP",           /* mighty only */
 315                           "EDP_HPD",
 316                           "DVS1",
 317                           "nFALUT1",            /* nFAULT1 on jaq */
 318                           "LCD_EN",
 319                           "DVS2",
 320
 321                           "VCC5V_GOOD_H",
 322                           "I2C4_SDA_TP",
 323                           "I2C4_SCL_TP",
 324                           "I2C5_SDA_HDMI",
 325                           "I2C5_SCL_HDMI",
 326                           "5V_DRV",
 327                           "UART2_RXD",
 328                           "UART2_TXD";
 329 };
 330
 331 &gpio8 {
 332         gpio-line-names = "RAM_ID0",
 333                           "RAM_ID1",
 334                           "RAM_ID2",
 335                           "RAM_ID3",
 336                           "I2C1_SDA_TPM",
 337                           "I2C1_SCL_TPM",
 338                           "SPI2_CLK",
 339                           "SPI2_CS0",
 340
 341                           "SPI2_RXD",
 342                           "SPI2_TXD";
 343 };
 344
 345 &pinctrl {
 346         backlight {
 347                 bl_pwr_en: bl_pwr_en {
 348                         rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 349                 };
 350         };
 351
 352         buck-5v {
 353                 drv_5v: drv-5v {
 354                         rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 355                 };
 356         };
 357
 358         hdmi {
 359                 vcc50_hdmi_en: vcc50-hdmi-en {
 360                         rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 361                 };
 362         };
 363
 364         lcd {
 365                 lcd_enable_h: lcd-en {
 366                         rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 367                 };
 368
 369                 avdd_1v8_disp_en: avdd-1v8-disp-en {
 370                         rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 371                 };
 372         };
 373
 374         pmic {
 375                 dvs_1: dvs-1 {
 376                         rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
 377                 };
 378
 379                 dvs_2: dvs-2 {
 380                         rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
 381                 };
 382         };
 383 };