arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "armv7-m.dtsi"
  44 #include <dt-bindings/clock/stm32fx-clock.h>
  45 #include <dt-bindings/mfd/stm32f7-rcc.h>
  46
  47 / {
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         clocks {
  52                 clk_hse: clk-hse {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <0>;
  56                 };
  57
  58                 clk-lse {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <32768>;
  62                 };
  63
  64                 clk-lsi {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32000>;
  68                 };
  69
  70                 clk_i2s_ckin: clk-i2s-ckin {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <48000000>;
  74                 };
  75         };
  76
  77         soc {
  78                 timer2: timer@40000000 {
  79                         compatible = "st,stm32-timer";
  80                         reg = <0x40000000 0x400>;
  81                         interrupts = <28>;
  82                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  83                         status = "disabled";
  84                 };
  85
  86                 timers2: timers@40000000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "st,stm32-timers";
  90                         reg = <0x40000000 0x400>;
  91                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  92                         clock-names = "int";
  93                         status = "disabled";
  94
  95                         pwm {
  96                                 compatible = "st,stm32-pwm";
  97                                 status = "disabled";
  98                         };
  99
 100                         timer@1 {
 101                                 compatible = "st,stm32-timer-trigger";
 102                                 reg = <1>;
 103                                 status = "disabled";
 104                         };
 105                 };
 106
 107                 timer3: timer@40000400 {
 108                         compatible = "st,stm32-timer";
 109                         reg = <0x40000400 0x400>;
 110                         interrupts = <29>;
 111                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 112                         status = "disabled";
 113                 };
 114
 115                 timers3: timers@40000400 {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         compatible = "st,stm32-timers";
 119                         reg = <0x40000400 0x400>;
 120                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 121                         clock-names = "int";
 122                         status = "disabled";
 123
 124                         pwm {
 125                                 compatible = "st,stm32-pwm";
 126                                 status = "disabled";
 127                         };
 128
 129                         timer@2 {
 130                                 compatible = "st,stm32-timer-trigger";
 131                                 reg = <2>;
 132                                 status = "disabled";
 133                         };
 134                 };
 135
 136                 timer4: timer@40000800 {
 137                         compatible = "st,stm32-timer";
 138                         reg = <0x40000800 0x400>;
 139                         interrupts = <30>;
 140                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 141                         status = "disabled";
 142                 };
 143
 144                 timers4: timers@40000800 {
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         compatible = "st,stm32-timers";
 148                         reg = <0x40000800 0x400>;
 149                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 150                         clock-names = "int";
 151                         status = "disabled";
 152
 153                         pwm {
 154                                 compatible = "st,stm32-pwm";
 155                                 status = "disabled";
 156                         };
 157
 158                         timer@3 {
 159                                 compatible = "st,stm32-timer-trigger";
 160                                 reg = <3>;
 161                                 status = "disabled";
 162                         };
 163                 };
 164
 165                 timer5: timer@40000c00 {
 166                         compatible = "st,stm32-timer";
 167                         reg = <0x40000c00 0x400>;
 168                         interrupts = <50>;
 169                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 170                 };
 171
 172                 timers5: timers@40000c00 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         compatible = "st,stm32-timers";
 176                         reg = <0x40000C00 0x400>;
 177                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 178                         clock-names = "int";
 179                         status = "disabled";
 180
 181                         pwm {
 182                                 compatible = "st,stm32-pwm";
 183                                 status = "disabled";
 184                         };
 185
 186                         timer@4 {
 187                                 compatible = "st,stm32-timer-trigger";
 188                                 reg = <4>;
 189                                 status = "disabled";
 190                         };
 191                 };
 192
 193                 timer6: timer@40001000 {
 194                         compatible = "st,stm32-timer";
 195                         reg = <0x40001000 0x400>;
 196                         interrupts = <54>;
 197                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 198                         status = "disabled";
 199                 };
 200
 201                 timers6: timers@40001000 {
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         compatible = "st,stm32-timers";
 205                         reg = <0x40001000 0x400>;
 206                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 207                         clock-names = "int";
 208                         status = "disabled";
 209
 210                         timer@5 {
 211                                 compatible = "st,stm32-timer-trigger";
 212                                 reg = <5>;
 213                                 status = "disabled";
 214                         };
 215                 };
 216
 217                 timer7: timer@40001400 {
 218                         compatible = "st,stm32-timer";
 219                         reg = <0x40001400 0x400>;
 220                         interrupts = <55>;
 221                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 222                         status = "disabled";
 223                 };
 224
 225                 timers7: timers@40001400 {
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         compatible = "st,stm32-timers";
 229                         reg = <0x40001400 0x400>;
 230                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 231                         clock-names = "int";
 232                         status = "disabled";
 233
 234                         timer@6 {
 235                                 compatible = "st,stm32-timer-trigger";
 236                                 reg = <6>;
 237                                 status = "disabled";
 238                         };
 239                 };
 240
 241                 timers12: timers@40001800 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         compatible = "st,stm32-timers";
 245                         reg = <0x40001800 0x400>;
 246                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 247                         clock-names = "int";
 248                         status = "disabled";
 249
 250                         pwm {
 251                                 compatible = "st,stm32-pwm";
 252                                 status = "disabled";
 253                         };
 254
 255                         timer@11 {
 256                                 compatible = "st,stm32-timer-trigger";
 257                                 reg = <11>;
 258                                 status = "disabled";
 259                         };
 260                 };
 261
 262                 timers13: timers@40001c00 {
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         compatible = "st,stm32-timers";
 266                         reg = <0x40001C00 0x400>;
 267                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 268                         clock-names = "int";
 269                         status = "disabled";
 270
 271                         pwm {
 272                                 compatible = "st,stm32-pwm";
 273                                 status = "disabled";
 274                         };
 275                 };
 276
 277                 timers14: timers@40002000 {
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         compatible = "st,stm32-timers";
 281                         reg = <0x40002000 0x400>;
 282                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 283                         clock-names = "int";
 284                         status = "disabled";
 285
 286                         pwm {
 287                                 compatible = "st,stm32-pwm";
 288                                 status = "disabled";
 289                         };
 290                 };
 291
 292                 rtc: rtc@40002800 {
 293                         compatible = "st,stm32-rtc";
 294                         reg = <0x40002800 0x400>;
 295                         clocks = <&rcc 1 CLK_RTC>;
 296                         clock-names = "ck_rtc";
 297                         assigned-clocks = <&rcc 1 CLK_RTC>;
 298                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 299                         interrupt-parent = <&exti>;
 300                         interrupts = <17 1>;
 301                         interrupt-names = "alarm";
 302                         st,syscfg = <&pwrcfg 0x00 0x100>;
 303                         status = "disabled";
 304                 };
 305
 306                 usart2: serial@40004400 {
 307                         compatible = "st,stm32f7-uart";
 308                         reg = <0x40004400 0x400>;
 309                         interrupts = <38>;
 310                         clocks = <&rcc 1 CLK_USART2>;
 311                         status = "disabled";
 312                 };
 313
 314                 usart3: serial@40004800 {
 315                         compatible = "st,stm32f7-uart";
 316                         reg = <0x40004800 0x400>;
 317                         interrupts = <39>;
 318                         clocks = <&rcc 1 CLK_USART3>;
 319                         status = "disabled";
 320                 };
 321
 322                 usart4: serial@40004c00 {
 323                         compatible = "st,stm32f7-uart";
 324                         reg = <0x40004c00 0x400>;
 325                         interrupts = <52>;
 326                         clocks = <&rcc 1 CLK_UART4>;
 327                         status = "disabled";
 328                 };
 329
 330                 usart5: serial@40005000 {
 331                         compatible = "st,stm32f7-uart";
 332                         reg = <0x40005000 0x400>;
 333                         interrupts = <53>;
 334                         clocks = <&rcc 1 CLK_UART5>;
 335                         status = "disabled";
 336                 };
 337
 338                 i2c1: i2c@40005400 {
 339                         compatible = "st,stm32f7-i2c";
 340                         reg = <0x40005400 0x400>;
 341                         interrupts = <31>,
 342                                      <32>;
 343                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 344                         clocks = <&rcc 1 CLK_I2C1>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         status = "disabled";
 348                 };
 349
 350                 i2c2: i2c@40005800 {
 351                         compatible = "st,stm32f7-i2c";
 352                         reg = <0x40005800 0x400>;
 353                         interrupts = <33>,
 354                                      <34>;
 355                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 356                         clocks = <&rcc 1 CLK_I2C2>;
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         status = "disabled";
 360                 };
 361
 362                 i2c3: i2c@40005C00 {
 363                         compatible = "st,stm32f7-i2c";
 364                         reg = <0x40005C00 0x400>;
 365                         interrupts = <72>,
 366                                      <73>;
 367                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 368                         clocks = <&rcc 1 CLK_I2C3>;
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         status = "disabled";
 372                 };
 373
 374                 i2c4: i2c@40006000 {
 375                         compatible = "st,stm32f7-i2c";
 376                         reg = <0x40006000 0x400>;
 377                         interrupts = <95>,
 378                                      <96>;
 379                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 380                         clocks = <&rcc 1 CLK_I2C4>;
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         status = "disabled";
 384                 };
 385
 386                 cec: cec@40006c00 {
 387                         compatible = "st,stm32-cec";
 388                         reg = <0x40006C00 0x400>;
 389                         interrupts = <94>;
 390                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 391                         clock-names = "cec", "hdmi-cec";
 392                         status = "disabled";
 393                 };
 394
 395                 usart7: serial@40007800 {
 396                         compatible = "st,stm32f7-uart";
 397                         reg = <0x40007800 0x400>;
 398                         interrupts = <82>;
 399                         clocks = <&rcc 1 CLK_UART7>;
 400                         status = "disabled";
 401                 };
 402
 403                 usart8: serial@40007c00 {
 404                         compatible = "st,stm32f7-uart";
 405                         reg = <0x40007c00 0x400>;
 406                         interrupts = <83>;
 407                         clocks = <&rcc 1 CLK_UART8>;
 408                         status = "disabled";
 409                 };
 410
 411                 timers1: timers@40010000 {
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         compatible = "st,stm32-timers";
 415                         reg = <0x40010000 0x400>;
 416                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 417                         clock-names = "int";
 418                         status = "disabled";
 419
 420                         pwm {
 421                                 compatible = "st,stm32-pwm";
 422                                 status = "disabled";
 423                         };
 424
 425                         timer@0 {
 426                                 compatible = "st,stm32-timer-trigger";
 427                                 reg = <0>;
 428                                 status = "disabled";
 429                         };
 430                 };
 431
 432                 timers8: timers@40010400 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         compatible = "st,stm32-timers";
 436                         reg = <0x40010400 0x400>;
 437                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 438                         clock-names = "int";
 439                         status = "disabled";
 440
 441                         pwm {
 442                                 compatible = "st,stm32-pwm";
 443                                 status = "disabled";
 444                         };
 445
 446                         timer@7 {
 447                                 compatible = "st,stm32-timer-trigger";
 448                                 reg = <7>;
 449                                 status = "disabled";
 450                         };
 451                 };
 452
 453                 usart1: serial@40011000 {
 454                         compatible = "st,stm32f7-uart";
 455                         reg = <0x40011000 0x400>;
 456                         interrupts = <37>;
 457                         clocks = <&rcc 1 CLK_USART1>;
 458                         status = "disabled";
 459                 };
 460
 461                 usart6: serial@40011400 {
 462                         compatible = "st,stm32f7-uart";
 463                         reg = <0x40011400 0x400>;
 464                         interrupts = <71>;
 465                         clocks = <&rcc 1 CLK_USART6>;
 466                         status = "disabled";
 467                 };
 468
 469                 sdio2: sdio2@40011c00 {
 470                         compatible = "arm,pl180", "arm,primecell";
 471                         arm,primecell-periphid = <0x00880180>;
 472                         reg = <0x40011c00 0x400>;
 473                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 474                         clock-names = "apb_pclk";
 475                         interrupts = <103>;
 476                         max-frequency = <48000000>;
 477                         status = "disabled";
 478                 };
 479
 480                 sdio1: sdio1@40012c00 {
 481                         compatible = "arm,pl180", "arm,primecell";
 482                         arm,primecell-periphid = <0x00880180>;
 483                         reg = <0x40012c00 0x400>;
 484                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 485                         clock-names = "apb_pclk";
 486                         interrupts = <49>;
 487                         max-frequency = <48000000>;
 488                         status = "disabled";
 489                 };
 490
 491                 syscfg: system-config@40013800 {
 492                         compatible = "syscon";
 493                         reg = <0x40013800 0x400>;
 494                 };
 495
 496                 exti: interrupt-controller@40013c00 {
 497                         compatible = "st,stm32-exti";
 498                         interrupt-controller;
 499                         #interrupt-cells = <2>;
 500                         reg = <0x40013C00 0x400>;
 501                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 502                 };
 503
 504                 timers9: timers@40014000 {
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         compatible = "st,stm32-timers";
 508                         reg = <0x40014000 0x400>;
 509                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 510                         clock-names = "int";
 511                         status = "disabled";
 512
 513                         pwm {
 514                                 compatible = "st,stm32-pwm";
 515                                 status = "disabled";
 516                         };
 517
 518                         timer@8 {
 519                                 compatible = "st,stm32-timer-trigger";
 520                                 reg = <8>;
 521                                 status = "disabled";
 522                         };
 523                 };
 524
 525                 timers10: timers@40014400 {
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         compatible = "st,stm32-timers";
 529                         reg = <0x40014400 0x400>;
 530                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 531                         clock-names = "int";
 532                         status = "disabled";
 533
 534                         pwm {
 535                                 compatible = "st,stm32-pwm";
 536                                 status = "disabled";
 537                         };
 538                 };
 539
 540                 timers11: timers@40014800 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         compatible = "st,stm32-timers";
 544                         reg = <0x40014800 0x400>;
 545                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 546                         clock-names = "int";
 547                         status = "disabled";
 548
 549                         pwm {
 550                                 compatible = "st,stm32-pwm";
 551                                 status = "disabled";
 552                         };
 553                 };
 554
 555                 pwrcfg: power-config@40007000 {
 556                         compatible = "syscon";
 557                         reg = <0x40007000 0x400>;
 558                 };
 559
 560                 crc: crc@40023000 {
 561                         compatible = "st,stm32f7-crc";
 562                         reg = <0x40023000 0x400>;
 563                         clocks = <&rcc 0 12>;
 564                         status = "disabled";
 565                 };
 566
 567                 rcc: rcc@40023800 {
 568                         #reset-cells = <1>;
 569                         #clock-cells = <2>;
 570                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 571                         reg = <0x40023800 0x400>;
 572                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 573                         st,syscfg = <&pwrcfg>;
 574                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 575                         assigned-clock-rates = <1000000>;
 576                 };
 577
 578                 dma1: dma@40026000 {
 579                         compatible = "st,stm32-dma";
 580                         reg = <0x40026000 0x400>;
 581                         interrupts = <11>,
 582                                      <12>,
 583                                      <13>,
 584                                      <14>,
 585                                      <15>,
 586                                      <16>,
 587                                      <17>,
 588                                      <47>;
 589                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 590                         #dma-cells = <4>;
 591                         status = "disabled";
 592                 };
 593
 594                 dma2: dma@40026400 {
 595                         compatible = "st,stm32-dma";
 596                         reg = <0x40026400 0x400>;
 597                         interrupts = <56>,
 598                                      <57>,
 599                                      <58>,
 600                                      <59>,
 601                                      <60>,
 602                                      <68>,
 603                                      <69>,
 604                                      <70>;
 605                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 606                         #dma-cells = <4>;
 607                         st,mem2mem;
 608                         status = "disabled";
 609                 };
 610
 611                 usbotg_hs: usb@40040000 {
 612                         compatible = "st,stm32f7-hsotg";
 613                         reg = <0x40040000 0x40000>;
 614                         interrupts = <77>;
 615                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 616                         clock-names = "otg";
 617                         g-rx-fifo-size = <256>;
 618                         g-np-tx-fifo-size = <32>;
 619                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 620                         status = "disabled";
 621                 };
 622
 623                 usbotg_fs: usb@50000000 {
 624                         compatible = "st,stm32f4x9-fsotg";
 625                         reg = <0x50000000 0x40000>;
 626                         interrupts = <67>;
 627                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 628                         clock-names = "otg";
 629                         status = "disabled";
 630                 };
 631         };
 632 };
 633
 634 &systick {
 635         clocks = <&rcc 1 0>;
 636         status = "okay";
 637 };