| blob | 0c4e6ebc35291e8e243c816d0a7631ae1ee8ab9f |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a7";
26 device_type = "cpu";
27 reg = <1>;
28 };
29 };
31 psci {
32 compatible = "arm,psci";
33 method = "smc";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
36 };
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 };
55 clocks {
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
80 clk_csi: clk-csi {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
84 };
85 };
87 thermal-zones {
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
90 polling-delay = <0>;
91 thermal-sensors = <&dts>;
93 trips {
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
96 hysteresis = <0>;
97 type = "passive";
98 };
100 cpu-crit {
101 temperature = <120000>;
102 hysteresis = <0>;
103 type = "critical";
104 };
105 };
107 cooling-maps {
108 };
109 };
110 };
112 soc {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 interrupt-parent = <&intc>;
117 ranges;
119 timers2: timer@40000000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000000 0x400>;
124 clocks = <&rcc TIM2_K>;
125 clock-names = "int";
126 dmas = <&dmamux1 18 0x400 0x1>,
127 <&dmamux1 19 0x400 0x1>,
128 <&dmamux1 20 0x400 0x1>,
129 <&dmamux1 21 0x400 0x1>,
130 <&dmamux1 22 0x400 0x1>;
131 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
132 status = "disabled";
134 pwm {
135 compatible = "st,stm32-pwm";
136 status = "disabled";
137 };
139 timer@1 {
140 compatible = "st,stm32h7-timer-trigger";
141 reg = <1>;
142 status = "disabled";
143 };
144 };
146 timers3: timer@40001000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "st,stm32-timers";
150 reg = <0x40001000 0x400>;
151 clocks = <&rcc TIM3_K>;
152 clock-names = "int";
153 dmas = <&dmamux1 23 0x400 0x1>,
154 <&dmamux1 24 0x400 0x1>,
155 <&dmamux1 25 0x400 0x1>,
156 <&dmamux1 26 0x400 0x1>,
157 <&dmamux1 27 0x400 0x1>,
158 <&dmamux1 28 0x400 0x1>;
159 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
160 status = "disabled";
162 pwm {
163 compatible = "st,stm32-pwm";
164 status = "disabled";
165 };
167 timer@2 {
168 compatible = "st,stm32h7-timer-trigger";
169 reg = <2>;
170 status = "disabled";
171 };
172 };
174 timers4: timer@40002000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "st,stm32-timers";
178 reg = <0x40002000 0x400>;
179 clocks = <&rcc TIM4_K>;
180 clock-names = "int";
181 dmas = <&dmamux1 29 0x400 0x1>,
182 <&dmamux1 30 0x400 0x1>,
183 <&dmamux1 31 0x400 0x1>,
184 <&dmamux1 32 0x400 0x1>;
185 dma-names = "ch1", "ch2", "ch3", "ch4";
186 status = "disabled";
188 pwm {
189 compatible = "st,stm32-pwm";
190 status = "disabled";
191 };
193 timer@3 {
194 compatible = "st,stm32h7-timer-trigger";
195 reg = <3>;
196 status = "disabled";
197 };
198 };
200 timers5: timer@40003000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
204 reg = <0x40003000 0x400>;
205 clocks = <&rcc TIM5_K>;
206 clock-names = "int";
207 dmas = <&dmamux1 55 0x400 0x1>,
208 <&dmamux1 56 0x400 0x1>,
209 <&dmamux1 57 0x400 0x1>,
210 <&dmamux1 58 0x400 0x1>,
211 <&dmamux1 59 0x400 0x1>,
212 <&dmamux1 60 0x400 0x1>;
213 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
214 status = "disabled";
216 pwm {
217 compatible = "st,stm32-pwm";
218 status = "disabled";
219 };
221 timer@4 {
222 compatible = "st,stm32h7-timer-trigger";
223 reg = <4>;
224 status = "disabled";
225 };
226 };
228 timers6: timer@40004000 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "st,stm32-timers";
232 reg = <0x40004000 0x400>;
233 clocks = <&rcc TIM6_K>;
234 clock-names = "int";
235 dmas = <&dmamux1 69 0x400 0x1>;
236 dma-names = "up";
237 status = "disabled";
239 timer@5 {
240 compatible = "st,stm32h7-timer-trigger";
241 reg = <5>;
242 status = "disabled";
243 };
244 };
246 timers7: timer@40005000 {
247 #address-cells = <1>;
248 #size-cells = <0>;
249 compatible = "st,stm32-timers";
250 reg = <0x40005000 0x400>;
251 clocks = <&rcc TIM7_K>;
252 clock-names = "int";
253 dmas = <&dmamux1 70 0x400 0x1>;
254 dma-names = "up";
255 status = "disabled";
257 timer@6 {
258 compatible = "st,stm32h7-timer-trigger";
259 reg = <6>;
260 status = "disabled";
261 };
262 };
264 timers12: timer@40006000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "st,stm32-timers";
268 reg = <0x40006000 0x400>;
269 clocks = <&rcc TIM12_K>;
270 clock-names = "int";
271 status = "disabled";
273 pwm {
274 compatible = "st,stm32-pwm";
275 status = "disabled";
276 };
278 timer@11 {
279 compatible = "st,stm32h7-timer-trigger";
280 reg = <11>;
281 status = "disabled";
282 };
283 };
285 timers13: timer@40007000 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "st,stm32-timers";
289 reg = <0x40007000 0x400>;
290 clocks = <&rcc TIM13_K>;
291 clock-names = "int";
292 status = "disabled";
294 pwm {
295 compatible = "st,stm32-pwm";
296 status = "disabled";
297 };
299 timer@12 {
300 compatible = "st,stm32h7-timer-trigger";
301 reg = <12>;
302 status = "disabled";
303 };
304 };
306 timers14: timer@40008000 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 compatible = "st,stm32-timers";
310 reg = <0x40008000 0x400>;
311 clocks = <&rcc TIM14_K>;
312 clock-names = "int";
313 status = "disabled";
315 pwm {
316 compatible = "st,stm32-pwm";
317 status = "disabled";
318 };
320 timer@13 {
321 compatible = "st,stm32h7-timer-trigger";
322 reg = <13>;
323 status = "disabled";
324 };
325 };
327 lptimer1: timer@40009000 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "st,stm32-lptimer";
331 reg = <0x40009000 0x400>;
332 clocks = <&rcc LPTIM1_K>;
333 clock-names = "mux";
334 status = "disabled";
336 pwm {
337 compatible = "st,stm32-pwm-lp";
338 #pwm-cells = <3>;
339 status = "disabled";
340 };
342 trigger@0 {
343 compatible = "st,stm32-lptimer-trigger";
344 reg = <0>;
345 status = "disabled";
346 };
348 counter {
349 compatible = "st,stm32-lptimer-counter";
350 status = "disabled";
351 };
352 };
354 spi2: spi@4000b000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "st,stm32h7-spi";
358 reg = <0x4000b000 0x400>;
359 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&rcc SPI2_K>;
361 resets = <&rcc SPI2_R>;
362 dmas = <&dmamux1 39 0x400 0x05>,
363 <&dmamux1 40 0x400 0x05>;
364 dma-names = "rx", "tx";
365 status = "disabled";
366 };
368 i2s2: audio-controller@4000b000 {
369 compatible = "st,stm32h7-i2s";
370 #sound-dai-cells = <0>;
371 reg = <0x4000b000 0x400>;
372 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
373 dmas = <&dmamux1 39 0x400 0x01>,
374 <&dmamux1 40 0x400 0x01>;
375 dma-names = "rx", "tx";
376 status = "disabled";
377 };
379 spi3: spi@4000c000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "st,stm32h7-spi";
383 reg = <0x4000c000 0x400>;
384 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&rcc SPI3_K>;
386 resets = <&rcc SPI3_R>;
387 dmas = <&dmamux1 61 0x400 0x05>,
388 <&dmamux1 62 0x400 0x05>;
389 dma-names = "rx", "tx";
390 status = "disabled";
391 };
393 i2s3: audio-controller@4000c000 {
394 compatible = "st,stm32h7-i2s";
395 #sound-dai-cells = <0>;
396 reg = <0x4000c000 0x400>;
397 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
398 dmas = <&dmamux1 61 0x400 0x01>,
399 <&dmamux1 62 0x400 0x01>;
400 dma-names = "rx", "tx";
401 status = "disabled";
402 };
404 spdifrx: audio-controller@4000d000 {
405 compatible = "st,stm32h7-spdifrx";
406 #sound-dai-cells = <0>;
407 reg = <0x4000d000 0x400>;
408 clocks = <&rcc SPDIF_K>;
409 clock-names = "kclk";
410 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
411 dmas = <&dmamux1 93 0x400 0x01>,
412 <&dmamux1 94 0x400 0x01>;
413 dma-names = "rx", "rx-ctrl";
414 status = "disabled";
415 };
417 usart2: serial@4000e000 {
418 compatible = "st,stm32h7-uart";
419 reg = <0x4000e000 0x400>;
420 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&rcc USART2_K>;
422 status = "disabled";
423 };
425 usart3: serial@4000f000 {
426 compatible = "st,stm32h7-uart";
427 reg = <0x4000f000 0x400>;
428 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&rcc USART3_K>;
430 status = "disabled";
431 };
433 uart4: serial@40010000 {
434 compatible = "st,stm32h7-uart";
435 reg = <0x40010000 0x400>;
436 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&rcc UART4_K>;
438 status = "disabled";
439 };
441 uart5: serial@40011000 {
442 compatible = "st,stm32h7-uart";
443 reg = <0x40011000 0x400>;
444 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&rcc UART5_K>;
446 status = "disabled";
447 };
449 i2c1: i2c@40012000 {
450 compatible = "st,stm32f7-i2c";
451 reg = <0x40012000 0x400>;
452 interrupt-names = "event", "error";
453 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&rcc I2C1_K>;
456 resets = <&rcc I2C1_R>;
457 #address-cells = <1>;
458 #size-cells = <0>;
459 status = "disabled";
460 };
462 i2c2: i2c@40013000 {
463 compatible = "st,stm32f7-i2c";
464 reg = <0x40013000 0x400>;
465 interrupt-names = "event", "error";
466 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&rcc I2C2_K>;
469 resets = <&rcc I2C2_R>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
475 i2c3: i2c@40014000 {
476 compatible = "st,stm32f7-i2c";
477 reg = <0x40014000 0x400>;
478 interrupt-names = "event", "error";
479 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&rcc I2C3_K>;
482 resets = <&rcc I2C3_R>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
488 i2c5: i2c@40015000 {
489 compatible = "st,stm32f7-i2c";
490 reg = <0x40015000 0x400>;
491 interrupt-names = "event", "error";
492 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&rcc I2C5_K>;
495 resets = <&rcc I2C5_R>;
496 #address-cells = <1>;
497 #size-cells = <0>;
498 status = "disabled";
499 };
501 cec: cec@40016000 {
502 compatible = "st,stm32-cec";
503 reg = <0x40016000 0x400>;
504 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&rcc CEC_K>, <&clk_lse>;
506 clock-names = "cec", "hdmi-cec";
507 status = "disabled";
508 };
510 dac: dac@40017000 {
511 compatible = "st,stm32h7-dac-core";
512 reg = <0x40017000 0x400>;
513 clocks = <&rcc DAC12>;
514 clock-names = "pclk";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
519 dac1: dac@1 {
520 compatible = "st,stm32-dac";
521 #io-channels-cells = <1>;
522 reg = <1>;
523 status = "disabled";
524 };
526 dac2: dac@2 {
527 compatible = "st,stm32-dac";
528 #io-channels-cells = <1>;
529 reg = <2>;
530 status = "disabled";
531 };
532 };
534 uart7: serial@40018000 {
535 compatible = "st,stm32h7-uart";
536 reg = <0x40018000 0x400>;
537 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&rcc UART7_K>;
539 status = "disabled";
540 };
542 uart8: serial@40019000 {
543 compatible = "st,stm32h7-uart";
544 reg = <0x40019000 0x400>;
545 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&rcc UART8_K>;
547 status = "disabled";
548 };
550 timers1: timer@44000000 {
551 #address-cells = <1>;
552 #size-cells = <0>;
553 compatible = "st,stm32-timers";
554 reg = <0x44000000 0x400>;
555 clocks = <&rcc TIM1_K>;
556 clock-names = "int";
557 dmas = <&dmamux1 11 0x400 0x1>,
558 <&dmamux1 12 0x400 0x1>,
559 <&dmamux1 13 0x400 0x1>,
560 <&dmamux1 14 0x400 0x1>,
561 <&dmamux1 15 0x400 0x1>,
562 <&dmamux1 16 0x400 0x1>,
563 <&dmamux1 17 0x400 0x1>;
564 dma-names = "ch1", "ch2", "ch3", "ch4",
565 "up", "trig", "com";
566 status = "disabled";
568 pwm {
569 compatible = "st,stm32-pwm";
570 status = "disabled";
571 };
573 timer@0 {
574 compatible = "st,stm32h7-timer-trigger";
575 reg = <0>;
576 status = "disabled";
577 };
578 };
580 timers8: timer@44001000 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "st,stm32-timers";
584 reg = <0x44001000 0x400>;
585 clocks = <&rcc TIM8_K>;
586 clock-names = "int";
587 dmas = <&dmamux1 47 0x400 0x1>,
588 <&dmamux1 48 0x400 0x1>,
589 <&dmamux1 49 0x400 0x1>,
590 <&dmamux1 50 0x400 0x1>,
591 <&dmamux1 51 0x400 0x1>,
592 <&dmamux1 52 0x400 0x1>,
593 <&dmamux1 53 0x400 0x1>;
594 dma-names = "ch1", "ch2", "ch3", "ch4",
595 "up", "trig", "com";
596 status = "disabled";
598 pwm {
599 compatible = "st,stm32-pwm";
600 status = "disabled";
601 };
603 timer@7 {
604 compatible = "st,stm32h7-timer-trigger";
605 reg = <7>;
606 status = "disabled";
607 };
608 };
610 usart6: serial@44003000 {
611 compatible = "st,stm32h7-uart";
612 reg = <0x44003000 0x400>;
613 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&rcc USART6_K>;
615 status = "disabled";
616 };
618 spi1: spi@44004000 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "st,stm32h7-spi";
622 reg = <0x44004000 0x400>;
623 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&rcc SPI1_K>;
625 resets = <&rcc SPI1_R>;
626 dmas = <&dmamux1 37 0x400 0x05>,
627 <&dmamux1 38 0x400 0x05>;
628 dma-names = "rx", "tx";
629 status = "disabled";
630 };
632 i2s1: audio-controller@44004000 {
633 compatible = "st,stm32h7-i2s";
634 #sound-dai-cells = <0>;
635 reg = <0x44004000 0x400>;
636 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
637 dmas = <&dmamux1 37 0x400 0x01>,
638 <&dmamux1 38 0x400 0x01>;
639 dma-names = "rx", "tx";
640 status = "disabled";
641 };
643 spi4: spi@44005000 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "st,stm32h7-spi";
647 reg = <0x44005000 0x400>;
648 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&rcc SPI4_K>;
650 resets = <&rcc SPI4_R>;
651 dmas = <&dmamux1 83 0x400 0x05>,
652 <&dmamux1 84 0x400 0x05>;
653 dma-names = "rx", "tx";
654 status = "disabled";
655 };
657 timers15: timer@44006000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "st,stm32-timers";
661 reg = <0x44006000 0x400>;
662 clocks = <&rcc TIM15_K>;
663 clock-names = "int";
664 dmas = <&dmamux1 105 0x400 0x1>,
665 <&dmamux1 106 0x400 0x1>,
666 <&dmamux1 107 0x400 0x1>,
667 <&dmamux1 108 0x400 0x1>;
668 dma-names = "ch1", "up", "trig", "com";
669 status = "disabled";
671 pwm {
672 compatible = "st,stm32-pwm";
673 status = "disabled";
674 };
676 timer@14 {
677 compatible = "st,stm32h7-timer-trigger";
678 reg = <14>;
679 status = "disabled";
680 };
681 };
683 timers16: timer@44007000 {
684 #address-cells = <1>;
685 #size-cells = <0>;
686 compatible = "st,stm32-timers";
687 reg = <0x44007000 0x400>;
688 clocks = <&rcc TIM16_K>;
689 clock-names = "int";
690 dmas = <&dmamux1 109 0x400 0x1>,
691 <&dmamux1 110 0x400 0x1>;
692 dma-names = "ch1", "up";
693 status = "disabled";
695 pwm {
696 compatible = "st,stm32-pwm";
697 status = "disabled";
698 };
699 timer@15 {
700 compatible = "st,stm32h7-timer-trigger";
701 reg = <15>;
702 status = "disabled";
703 };
704 };
706 timers17: timer@44008000 {
707 #address-cells = <1>;
708 #size-cells = <0>;
709 compatible = "st,stm32-timers";
710 reg = <0x44008000 0x400>;
711 clocks = <&rcc TIM17_K>;
712 clock-names = "int";
713 dmas = <&dmamux1 111 0x400 0x1>,
714 <&dmamux1 112 0x400 0x1>;
715 dma-names = "ch1", "up";
716 status = "disabled";
718 pwm {
719 compatible = "st,stm32-pwm";
720 status = "disabled";
721 };
723 timer@16 {
724 compatible = "st,stm32h7-timer-trigger";
725 reg = <16>;
726 status = "disabled";
727 };
728 };
730 spi5: spi@44009000 {
731 #address-cells = <1>;
732 #size-cells = <0>;
733 compatible = "st,stm32h7-spi";
734 reg = <0x44009000 0x400>;
735 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&rcc SPI5_K>;
737 resets = <&rcc SPI5_R>;
738 dmas = <&dmamux1 85 0x400 0x05>,
739 <&dmamux1 86 0x400 0x05>;
740 dma-names = "rx", "tx";
741 status = "disabled";
742 };
744 sai1: sai@4400a000 {
745 compatible = "st,stm32h7-sai";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0 0x4400a000 0x400>;
749 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
750 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
751 resets = <&rcc SAI1_R>;
752 status = "disabled";
754 sai1a: audio-controller@4400a004 {
755 #sound-dai-cells = <0>;
757 compatible = "st,stm32-sai-sub-a";
758 reg = <0x4 0x1c>;
759 clocks = <&rcc SAI1_K>;
760 clock-names = "sai_ck";
761 dmas = <&dmamux1 87 0x400 0x01>;
762 status = "disabled";
763 };
765 sai1b: audio-controller@4400a024 {
766 #sound-dai-cells = <0>;
767 compatible = "st,stm32-sai-sub-b";
768 reg = <0x24 0x1c>;
769 clocks = <&rcc SAI1_K>;
770 clock-names = "sai_ck";
771 dmas = <&dmamux1 88 0x400 0x01>;
772 status = "disabled";
773 };
774 };
776 sai2: sai@4400b000 {
777 compatible = "st,stm32h7-sai";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 ranges = <0 0x4400b000 0x400>;
781 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
782 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
783 resets = <&rcc SAI2_R>;
784 status = "disabled";
786 sai2a: audio-controller@4400b004 {
787 #sound-dai-cells = <0>;
788 compatible = "st,stm32-sai-sub-a";
789 reg = <0x4 0x1c>;
790 clocks = <&rcc SAI2_K>;
791 clock-names = "sai_ck";
792 dmas = <&dmamux1 89 0x400 0x01>;
793 status = "disabled";
794 };
796 sai2b: audio-controller@4400b024 {
797 #sound-dai-cells = <0>;
798 compatible = "st,stm32-sai-sub-b";
799 reg = <0x24 0x1c>;
800 clocks = <&rcc SAI2_K>;
801 clock-names = "sai_ck";
802 dmas = <&dmamux1 90 0x400 0x01>;
803 status = "disabled";
804 };
805 };
807 sai3: sai@4400c000 {
808 compatible = "st,stm32h7-sai";
809 #address-cells = <1>;
810 #size-cells = <1>;
811 ranges = <0 0x4400c000 0x400>;
812 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
813 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
814 resets = <&rcc SAI3_R>;
815 status = "disabled";
817 sai3a: audio-controller@4400c004 {
818 #sound-dai-cells = <0>;
819 compatible = "st,stm32-sai-sub-a";
820 reg = <0x04 0x1c>;
821 clocks = <&rcc SAI3_K>;
822 clock-names = "sai_ck";
823 dmas = <&dmamux1 113 0x400 0x01>;
824 status = "disabled";
825 };
827 sai3b: audio-controller@4400c024 {
828 #sound-dai-cells = <0>;
829 compatible = "st,stm32-sai-sub-b";
830 reg = <0x24 0x1c>;
831 clocks = <&rcc SAI3_K>;
832 clock-names = "sai_ck";
833 dmas = <&dmamux1 114 0x400 0x01>;
834 status = "disabled";
835 };
836 };
838 dfsdm: dfsdm@4400d000 {
839 compatible = "st,stm32mp1-dfsdm";
840 reg = <0x4400d000 0x800>;
841 clocks = <&rcc DFSDM_K>;
842 clock-names = "dfsdm";
843 #address-cells = <1>;
844 #size-cells = <0>;
845 status = "disabled";
847 dfsdm0: filter@0 {
848 compatible = "st,stm32-dfsdm-adc";
849 #io-channel-cells = <1>;
850 reg = <0>;
851 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
852 dmas = <&dmamux1 101 0x400 0x01>;
853 dma-names = "rx";
854 status = "disabled";
855 };
857 dfsdm1: filter@1 {
858 compatible = "st,stm32-dfsdm-adc";
859 #io-channel-cells = <1>;
860 reg = <1>;
861 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
862 dmas = <&dmamux1 102 0x400 0x01>;
863 dma-names = "rx";
864 status = "disabled";
865 };
867 dfsdm2: filter@2 {
868 compatible = "st,stm32-dfsdm-adc";
869 #io-channel-cells = <1>;
870 reg = <2>;
871 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
872 dmas = <&dmamux1 103 0x400 0x01>;
873 dma-names = "rx";
874 status = "disabled";
875 };
877 dfsdm3: filter@3 {
878 compatible = "st,stm32-dfsdm-adc";
879 #io-channel-cells = <1>;
880 reg = <3>;
881 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
882 dmas = <&dmamux1 104 0x400 0x01>;
883 dma-names = "rx";
884 status = "disabled";
885 };
887 dfsdm4: filter@4 {
888 compatible = "st,stm32-dfsdm-adc";
889 #io-channel-cells = <1>;
890 reg = <4>;
891 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
892 dmas = <&dmamux1 91 0x400 0x01>;
893 dma-names = "rx";
894 status = "disabled";
895 };
897 dfsdm5: filter@5 {
898 compatible = "st,stm32-dfsdm-adc";
899 #io-channel-cells = <1>;
900 reg = <5>;
901 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
902 dmas = <&dmamux1 92 0x400 0x01>;
903 dma-names = "rx";
904 status = "disabled";
905 };
906 };
908 m_can1: can@4400e000 {
909 compatible = "bosch,m_can";
910 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
911 reg-names = "m_can", "message_ram";
912 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
914 interrupt-names = "int0", "int1";
915 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
916 clock-names = "hclk", "cclk";
917 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
918 status = "disabled";
919 };
921 m_can2: can@4400f000 {
922 compatible = "bosch,m_can";
923 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
924 reg-names = "m_can", "message_ram";
925 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
927 interrupt-names = "int0", "int1";
928 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
929 clock-names = "hclk", "cclk";
930 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
931 status = "disabled";
932 };
934 dma1: dma@48000000 {
935 compatible = "st,stm32-dma";
936 reg = <0x48000000 0x400>;
937 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&rcc DMA1>;
946 #dma-cells = <4>;
947 st,mem2mem;
948 dma-requests = <8>;
949 };
951 dma2: dma@48001000 {
952 compatible = "st,stm32-dma";
953 reg = <0x48001000 0x400>;
954 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&rcc DMA2>;
963 #dma-cells = <4>;
964 st,mem2mem;
965 dma-requests = <8>;
966 };
968 dmamux1: dma-router@48002000 {
969 compatible = "st,stm32h7-dmamux";
970 reg = <0x48002000 0x1c>;
971 #dma-cells = <3>;
972 dma-requests = <128>;
973 dma-masters = <&dma1 &dma2>;
974 dma-channels = <16>;
975 clocks = <&rcc DMAMUX>;
976 };
978 adc: adc@48003000 {
979 compatible = "st,stm32mp1-adc-core";
980 reg = <0x48003000 0x400>;
981 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
984 clock-names = "bus", "adc";
985 interrupt-controller;
986 #interrupt-cells = <1>;
987 #address-cells = <1>;
988 #size-cells = <0>;
989 status = "disabled";
991 adc1: adc@0 {
992 compatible = "st,stm32mp1-adc";
993 #io-channel-cells = <1>;
994 reg = <0x0>;
995 interrupt-parent = <&adc>;
996 interrupts = <0>;
997 dmas = <&dmamux1 9 0x400 0x01>;
998 dma-names = "rx";
999 status = "disabled";
1000 };
1002 adc2: adc@100 {
1003 compatible = "st,stm32mp1-adc";
1004 #io-channel-cells = <1>;
1005 reg = <0x100>;
1006 interrupt-parent = <&adc>;
1007 interrupts = <1>;
1008 dmas = <&dmamux1 10 0x400 0x01>;
1009 dma-names = "rx";
1010 status = "disabled";
1011 };
1012 };
1014 usbotg_hs: usb-otg@49000000 {
1015 compatible = "snps,dwc2";
1016 reg = <0x49000000 0x10000>;
1017 clocks = <&rcc USBO_K>;
1018 clock-names = "otg";
1019 resets = <&rcc USBO_R>;
1020 reset-names = "dwc2";
1021 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1022 g-rx-fifo-size = <256>;
1023 g-np-tx-fifo-size = <32>;
1024 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1025 dr_mode = "otg";
1026 status = "disabled";
1027 };
1029 ipcc: mailbox@4c001000 {
1030 compatible = "st,stm32mp1-ipcc";
1031 #mbox-cells = <1>;
1032 reg = <0x4c001000 0x400>;
1033 st,proc-id = <0>;
1034 interrupts-extended =
1035 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1036 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1037 <&exti 61 1>;
1038 interrupt-names = "rx", "tx", "wakeup";
1039 clocks = <&rcc IPCC>;
1040 wakeup-source;
1041 status = "disabled";
1042 };
1044 dcmi: dcmi@4c006000 {
1045 compatible = "st,stm32-dcmi";
1046 reg = <0x4c006000 0x400>;
1047 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1048 resets = <&rcc CAMITF_R>;
1049 clocks = <&rcc DCMI>;
1050 clock-names = "mclk";
1051 dmas = <&dmamux1 75 0x400 0x0d>;
1052 dma-names = "tx";
1053 status = "disabled";
1054 };
1056 rcc: rcc@50000000 {
1057 compatible = "st,stm32mp1-rcc", "syscon";
1058 reg = <0x50000000 0x1000>;
1059 #clock-cells = <1>;
1060 #reset-cells = <1>;
1061 };
1063 exti: interrupt-controller@5000d000 {
1064 compatible = "st,stm32mp1-exti", "syscon";
1065 interrupt-controller;
1066 #interrupt-cells = <2>;
1067 reg = <0x5000d000 0x400>;
1068 };
1070 syscfg: syscon@50020000 {
1071 compatible = "st,stm32mp157-syscfg", "syscon";
1072 reg = <0x50020000 0x400>;
1073 clocks = <&rcc SYSCFG>;
1074 };
1076 lptimer2: timer@50021000 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 compatible = "st,stm32-lptimer";
1080 reg = <0x50021000 0x400>;
1081 clocks = <&rcc LPTIM2_K>;
1082 clock-names = "mux";
1083 status = "disabled";
1085 pwm {
1086 compatible = "st,stm32-pwm-lp";
1087 #pwm-cells = <3>;
1088 status = "disabled";
1089 };
1091 trigger@1 {
1092 compatible = "st,stm32-lptimer-trigger";
1093 reg = <1>;
1094 status = "disabled";
1095 };
1097 counter {
1098 compatible = "st,stm32-lptimer-counter";
1099 status = "disabled";
1100 };
1101 };
1103 lptimer3: timer@50022000 {
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 compatible = "st,stm32-lptimer";
1107 reg = <0x50022000 0x400>;
1108 clocks = <&rcc LPTIM3_K>;
1109 clock-names = "mux";
1110 status = "disabled";
1112 pwm {
1113 compatible = "st,stm32-pwm-lp";
1114 #pwm-cells = <3>;
1115 status = "disabled";
1116 };
1118 trigger@2 {
1119 compatible = "st,stm32-lptimer-trigger";
1120 reg = <2>;
1121 status = "disabled";
1122 };
1123 };
1125 lptimer4: timer@50023000 {
1126 compatible = "st,stm32-lptimer";
1127 reg = <0x50023000 0x400>;
1128 clocks = <&rcc LPTIM4_K>;
1129 clock-names = "mux";
1130 status = "disabled";
1132 pwm {
1133 compatible = "st,stm32-pwm-lp";
1134 #pwm-cells = <3>;
1135 status = "disabled";
1136 };
1137 };
1139 lptimer5: timer@50024000 {
1140 compatible = "st,stm32-lptimer";
1141 reg = <0x50024000 0x400>;
1142 clocks = <&rcc LPTIM5_K>;
1143 clock-names = "mux";
1144 status = "disabled";
1146 pwm {
1147 compatible = "st,stm32-pwm-lp";
1148 #pwm-cells = <3>;
1149 status = "disabled";
1150 };
1151 };
1153 vrefbuf: vrefbuf@50025000 {
1154 compatible = "st,stm32-vrefbuf";
1155 reg = <0x50025000 0x8>;
1156 regulator-min-microvolt = <1500000>;
1157 regulator-max-microvolt = <2500000>;
1158 clocks = <&rcc VREF>;
1159 status = "disabled";
1160 };
1162 sai4: sai@50027000 {
1163 compatible = "st,stm32h7-sai";
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1166 ranges = <0 0x50027000 0x400>;
1167 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1168 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1169 resets = <&rcc SAI4_R>;
1170 status = "disabled";
1172 sai4a: audio-controller@50027004 {
1173 #sound-dai-cells = <0>;
1174 compatible = "st,stm32-sai-sub-a";
1175 reg = <0x04 0x1c>;
1176 clocks = <&rcc SAI4_K>;
1177 clock-names = "sai_ck";
1178 dmas = <&dmamux1 99 0x400 0x01>;
1179 status = "disabled";
1180 };
1182 sai4b: audio-controller@50027024 {
1183 #sound-dai-cells = <0>;
1184 compatible = "st,stm32-sai-sub-b";
1185 reg = <0x24 0x1c>;
1186 clocks = <&rcc SAI4_K>;
1187 clock-names = "sai_ck";
1188 dmas = <&dmamux1 100 0x400 0x01>;
1189 status = "disabled";
1190 };
1191 };
1193 dts: thermal@50028000 {
1194 compatible = "st,stm32-thermal";
1195 reg = <0x50028000 0x100>;
1196 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&rcc TMPSENS>;
1198 clock-names = "pclk";
1199 #thermal-sensor-cells = <0>;
1200 status = "disabled";
1201 };
1203 cryp1: cryp@54001000 {
1204 compatible = "st,stm32mp1-cryp";
1205 reg = <0x54001000 0x400>;
1206 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&rcc CRYP1>;
1208 resets = <&rcc CRYP1_R>;
1209 status = "disabled";
1210 };
1212 hash1: hash@54002000 {
1213 compatible = "st,stm32f756-hash";
1214 reg = <0x54002000 0x400>;
1215 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&rcc HASH1>;
1217 resets = <&rcc HASH1_R>;
1218 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1219 dma-names = "in";
1220 dma-maxburst = <2>;
1221 status = "disabled";
1222 };
1224 rng1: rng@54003000 {
1225 compatible = "st,stm32-rng";
1226 reg = <0x54003000 0x400>;
1227 clocks = <&rcc RNG1_K>;
1228 resets = <&rcc RNG1_R>;
1229 status = "disabled";
1230 };
1232 mdma1: dma@58000000 {
1233 compatible = "st,stm32h7-mdma";
1234 reg = <0x58000000 0x1000>;
1235 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&rcc MDMA>;
1237 #dma-cells = <5>;
1238 dma-channels = <32>;
1239 dma-requests = <48>;
1240 };
1242 qspi: spi@58003000 {
1243 compatible = "st,stm32f469-qspi";
1244 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1245 reg-names = "qspi", "qspi_mm";
1246 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&rcc QSPI_K>;
1248 resets = <&rcc QSPI_R>;
1249 status = "disabled";
1250 };
1252 sdmmc1: sdmmc@58005000 {
1253 compatible = "arm,pl18x", "arm,primecell";
1254 arm,primecell-periphid = <0x10153180>;
1255 reg = <0x58005000 0x1000>;
1256 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1257 interrupt-names = "cmd_irq";
1258 clocks = <&rcc SDMMC1_K>;
1259 clock-names = "apb_pclk";
1260 resets = <&rcc SDMMC1_R>;
1261 cap-sd-highspeed;
1262 cap-mmc-highspeed;
1263 max-frequency = <120000000>;
1264 };
1266 crc1: crc@58009000 {
1267 compatible = "st,stm32f7-crc";
1268 reg = <0x58009000 0x400>;
1269 clocks = <&rcc CRC1>;
1270 status = "disabled";
1271 };
1273 stmmac_axi_config_0: stmmac-axi-config {
1274 snps,wr_osr_lmt = <0x7>;
1275 snps,rd_osr_lmt = <0x7>;
1276 snps,blen = <0 0 0 0 16 8 4>;
1277 };
1279 ethernet0: ethernet@5800a000 {
1280 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1281 reg = <0x5800a000 0x2000>;
1282 reg-names = "stmmaceth";
1283 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1284 interrupt-names = "macirq";
1285 clock-names = "stmmaceth",
1286 "mac-clk-tx",
1287 "mac-clk-rx",
1288 "ethstp",
1289 "syscfg-clk";
1290 clocks = <&rcc ETHMAC>,
1291 <&rcc ETHTX>,
1292 <&rcc ETHRX>,
1293 <&rcc ETHSTP>,
1294 <&rcc SYSCFG>;
1295 st,syscon = <&syscfg 0x4>;
1296 snps,mixed-burst;
1297 snps,pbl = <2>;
1298 snps,axi-config = <&stmmac_axi_config_0>;
1299 snps,tso;
1300 status = "disabled";
1301 };
1303 usbh_ohci: usbh-ohci@5800c000 {
1304 compatible = "generic-ohci";
1305 reg = <0x5800c000 0x1000>;
1306 clocks = <&rcc USBH>;
1307 resets = <&rcc USBH_R>;
1308 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1309 status = "disabled";
1310 };
1312 usbh_ehci: usbh-ehci@5800d000 {
1313 compatible = "generic-ehci";
1314 reg = <0x5800d000 0x1000>;
1315 clocks = <&rcc USBH>;
1316 resets = <&rcc USBH_R>;
1317 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1318 companion = <&usbh_ohci>;
1319 status = "disabled";
1320 };
1322 gpu: gpu@59000000 {
1323 compatible = "vivante,gc";
1324 reg = <0x59000000 0x800>;
1325 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&rcc GPU>, <&rcc GPU_K>;
1327 clock-names = "bus" ,"core";
1328 resets = <&rcc GPU_R>;
1329 status = "disabled";
1330 };
1332 dsi: dsi@5a000000 {
1333 compatible = "st,stm32-dsi";
1334 reg = <0x5a000000 0x800>;
1335 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1336 clock-names = "pclk", "ref", "px_clk";
1337 resets = <&rcc DSI_R>;
1338 reset-names = "apb";
1339 status = "disabled";
1340 };
1342 ltdc: display-controller@5a001000 {
1343 compatible = "st,stm32-ltdc";
1344 reg = <0x5a001000 0x400>;
1345 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&rcc LTDC_PX>;
1348 clock-names = "lcd";
1349 resets = <&rcc LTDC_R>;
1350 status = "disabled";
1351 };
1353 iwdg2: watchdog@5a002000 {
1354 compatible = "st,stm32mp1-iwdg";
1355 reg = <0x5a002000 0x400>;
1356 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1357 clock-names = "pclk", "lsi";
1358 status = "disabled";
1359 };
1361 usbphyc: usbphyc@5a006000 {
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 compatible = "st,stm32mp1-usbphyc";
1365 reg = <0x5a006000 0x1000>;
1366 clocks = <&rcc USBPHY_K>;
1367 resets = <&rcc USBPHY_R>;
1368 status = "disabled";
1370 usbphyc_port0: usb-phy@0 {
1371 #phy-cells = <0>;
1372 reg = <0>;
1373 };
1375 usbphyc_port1: usb-phy@1 {
1376 #phy-cells = <1>;
1377 reg = <1>;
1378 };
1379 };
1381 usart1: serial@5c000000 {
1382 compatible = "st,stm32h7-uart";
1383 reg = <0x5c000000 0x400>;
1384 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1385 clocks = <&rcc USART1_K>;
1386 status = "disabled";
1387 };
1389 spi6: spi@5c001000 {
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 compatible = "st,stm32h7-spi";
1393 reg = <0x5c001000 0x400>;
1394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&rcc SPI6_K>;
1396 resets = <&rcc SPI6_R>;
1397 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1398 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1399 dma-names = "rx", "tx";
1400 status = "disabled";
1401 };
1403 i2c4: i2c@5c002000 {
1404 compatible = "st,stm32f7-i2c";
1405 reg = <0x5c002000 0x400>;
1406 interrupt-names = "event", "error";
1407 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&rcc I2C4_K>;
1410 resets = <&rcc I2C4_R>;
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1413 status = "disabled";
1414 };
1416 rtc: rtc@5c004000 {
1417 compatible = "st,stm32mp1-rtc";
1418 reg = <0x5c004000 0x400>;
1419 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1420 clock-names = "pclk", "rtc_ck";
1421 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1422 status = "disabled";
1423 };
1425 bsec: nvmem@5c005000 {
1426 compatible = "st,stm32mp15-bsec";
1427 reg = <0x5c005000 0x400>;
1428 #address-cells = <1>;
1429 #size-cells = <1>;
1430 ts_cal1: calib@5c {
1431 reg = <0x5c 0x2>;
1432 };
1433 ts_cal2: calib@5e {
1434 reg = <0x5e 0x2>;
1435 };
1436 };
1438 i2c6: i2c@5c009000 {
1439 compatible = "st,stm32f7-i2c";
1440 reg = <0x5c009000 0x400>;
1441 interrupt-names = "event", "error";
1442 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&rcc I2C6_K>;
1445 resets = <&rcc I2C6_R>;
1446 #address-cells = <1>;
1447 #size-cells = <0>;
1448 status = "disabled";
1449 };
1450 };
1451 };