| blob | 6007d0cc252d3a05aeff9ab9b340781c6d99d794 |
1 /*
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
50 / {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
55 clocks {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
60 osc24M: osc24M {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-accuracy = <50000>;
65 clock-output-names = "osc24M";
66 };
68 osc32k: osc32k {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 clock-accuracy = <20000>;
73 clock-output-names = "ext-osc32k";
74 };
75 };
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
81 cpu@0 {
82 compatible = "arm,cortex-a7";
83 device_type = "cpu";
84 reg = <0>;
85 };
87 cpu@1 {
88 compatible = "arm,cortex-a7";
89 device_type = "cpu";
90 reg = <1>;
91 };
93 cpu@2 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <2>;
97 };
99 cpu@3 {
100 compatible = "arm,cortex-a7";
101 device_type = "cpu";
102 reg = <3>;
103 };
104 };
106 de: display-engine {
107 compatible = "allwinner,sun8i-r40-display-engine";
108 allwinner,pipelines = <&mixer0>, <&mixer1>;
109 status = "disabled";
110 };
112 soc {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges;
118 display_clocks: clock@1000000 {
119 compatible = "allwinner,sun8i-r40-de2-clk",
120 "allwinner,sun8i-h3-de2-clk";
121 reg = <0x01000000 0x100000>;
122 clocks = <&ccu CLK_DE>,
123 <&ccu CLK_BUS_DE>;
124 clock-names = "mod",
125 "bus";
126 resets = <&ccu RST_BUS_DE>;
127 #clock-cells = <1>;
128 #reset-cells = <1>;
129 };
131 mixer0: mixer@1100000 {
132 compatible = "allwinner,sun8i-r40-de2-mixer-0";
133 reg = <0x01100000 0x100000>;
134 clocks = <&display_clocks CLK_BUS_MIXER0>,
135 <&display_clocks CLK_MIXER0>;
136 clock-names = "bus",
137 "mod";
138 resets = <&display_clocks RST_MIXER0>;
140 ports {
141 #address-cells = <1>;
142 #size-cells = <0>;
144 mixer0_out: port@1 {
145 reg = <1>;
146 mixer0_out_tcon_top: endpoint {
147 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
148 };
149 };
150 };
151 };
153 mixer1: mixer@1200000 {
154 compatible = "allwinner,sun8i-r40-de2-mixer-1";
155 reg = <0x01200000 0x100000>;
156 clocks = <&display_clocks CLK_BUS_MIXER1>,
157 <&display_clocks CLK_MIXER1>;
158 clock-names = "bus",
159 "mod";
160 resets = <&display_clocks RST_WB>;
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
166 mixer1_out: port@1 {
167 reg = <1>;
168 mixer1_out_tcon_top: endpoint {
169 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
170 };
171 };
172 };
173 };
175 nmi_intc: interrupt-controller@1c00030 {
176 compatible = "allwinner,sun7i-a20-sc-nmi";
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 reg = <0x01c00030 0x0c>;
180 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
181 };
183 mmc0: mmc@1c0f000 {
184 compatible = "allwinner,sun8i-r40-mmc",
185 "allwinner,sun50i-a64-mmc";
186 reg = <0x01c0f000 0x1000>;
187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
188 clock-names = "ahb", "mmc";
189 resets = <&ccu RST_BUS_MMC0>;
190 reset-names = "ahb";
191 pinctrl-0 = <&mmc0_pins>;
192 pinctrl-names = "default";
193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
194 status = "disabled";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
199 mmc1: mmc@1c10000 {
200 compatible = "allwinner,sun8i-r40-mmc",
201 "allwinner,sun50i-a64-mmc";
202 reg = <0x01c10000 0x1000>;
203 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
204 clock-names = "ahb", "mmc";
205 resets = <&ccu RST_BUS_MMC1>;
206 reset-names = "ahb";
207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
208 status = "disabled";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 };
213 mmc2: mmc@1c11000 {
214 compatible = "allwinner,sun8i-r40-emmc",
215 "allwinner,sun50i-a64-emmc";
216 reg = <0x01c11000 0x1000>;
217 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
218 clock-names = "ahb", "mmc";
219 resets = <&ccu RST_BUS_MMC2>;
220 reset-names = "ahb";
221 pinctrl-0 = <&mmc2_pins>;
222 pinctrl-names = "default";
223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
224 status = "disabled";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 };
229 mmc3: mmc@1c12000 {
230 compatible = "allwinner,sun8i-r40-mmc",
231 "allwinner,sun50i-a64-mmc";
232 reg = <0x01c12000 0x1000>;
233 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
234 clock-names = "ahb", "mmc";
235 resets = <&ccu RST_BUS_MMC3>;
236 reset-names = "ahb";
237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
238 status = "disabled";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 };
243 usbphy: phy@1c13400 {
244 compatible = "allwinner,sun8i-r40-usb-phy";
245 reg = <0x01c13400 0x14>,
246 <0x01c14800 0x4>,
247 <0x01c19800 0x4>,
248 <0x01c1c800 0x4>;
249 reg-names = "phy_ctrl",
250 "pmu0",
251 "pmu1",
252 "pmu2";
253 clocks = <&ccu CLK_USB_PHY0>,
254 <&ccu CLK_USB_PHY1>,
255 <&ccu CLK_USB_PHY2>;
256 clock-names = "usb0_phy",
257 "usb1_phy",
258 "usb2_phy";
259 resets = <&ccu RST_USB_PHY0>,
260 <&ccu RST_USB_PHY1>,
261 <&ccu RST_USB_PHY2>;
262 reset-names = "usb0_reset",
263 "usb1_reset",
264 "usb2_reset";
265 status = "disabled";
266 #phy-cells = <1>;
267 };
269 ehci1: usb@1c19000 {
270 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
271 reg = <0x01c19000 0x100>;
272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_EHCI1>;
274 resets = <&ccu RST_BUS_EHCI1>;
275 phys = <&usbphy 1>;
276 status = "disabled";
277 };
279 ohci1: usb@1c19400 {
280 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
281 reg = <0x01c19400 0x100>;
282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&ccu CLK_BUS_OHCI1>,
284 <&ccu CLK_USB_OHCI1>;
285 resets = <&ccu RST_BUS_OHCI1>;
286 phys = <&usbphy 1>;
287 status = "disabled";
288 };
290 ehci2: usb@1c1c000 {
291 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
292 reg = <0x01c1c000 0x100>;
293 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&ccu CLK_BUS_EHCI2>;
295 resets = <&ccu RST_BUS_EHCI2>;
296 phys = <&usbphy 2>;
297 status = "disabled";
298 };
300 ohci2: usb@1c1c400 {
301 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
302 reg = <0x01c1c400 0x100>;
303 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&ccu CLK_BUS_OHCI2>,
305 <&ccu CLK_USB_OHCI2>;
306 resets = <&ccu RST_BUS_OHCI2>;
307 phys = <&usbphy 2>;
308 status = "disabled";
309 };
311 ccu: clock@1c20000 {
312 compatible = "allwinner,sun8i-r40-ccu";
313 reg = <0x01c20000 0x400>;
314 clocks = <&osc24M>, <&rtc 0>;
315 clock-names = "hosc", "losc";
316 #clock-cells = <1>;
317 #reset-cells = <1>;
318 };
320 rtc: rtc@1c20400 {
321 compatible = "allwinner,sun8i-r40-rtc";
322 reg = <0x01c20400 0x400>;
323 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
324 clock-output-names = "osc32k", "osc32k-out";
325 clocks = <&osc32k>;
326 #clock-cells = <1>;
327 };
329 pio: pinctrl@1c20800 {
330 compatible = "allwinner,sun8i-r40-pinctrl";
331 reg = <0x01c20800 0x400>;
332 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
334 clock-names = "apb", "hosc", "losc";
335 gpio-controller;
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 #gpio-cells = <3>;
340 clk_out_a_pin: clk-out-a-pin {
341 pins = "PI12";
342 function = "clk_out_a";
343 };
345 gmac_rgmii_pins: gmac-rgmii-pins {
346 pins = "PA0", "PA1", "PA2", "PA3",
347 "PA4", "PA5", "PA6", "PA7",
348 "PA8", "PA10", "PA11", "PA12",
349 "PA13", "PA15", "PA16";
350 function = "gmac";
351 /*
352 * data lines in RGMII mode use DDR mode
353 * and need a higher signal drive strength
354 */
355 drive-strength = <40>;
356 };
358 i2c0_pins: i2c0-pins {
359 pins = "PB0", "PB1";
360 function = "i2c0";
361 };
363 mmc0_pins: mmc0-pins {
364 pins = "PF0", "PF1", "PF2",
365 "PF3", "PF4", "PF5";
366 function = "mmc0";
367 drive-strength = <30>;
368 bias-pull-up;
369 };
371 mmc1_pg_pins: mmc1-pg-pins {
372 pins = "PG0", "PG1", "PG2",
373 "PG3", "PG4", "PG5";
374 function = "mmc1";
375 drive-strength = <30>;
376 bias-pull-up;
377 };
379 mmc2_pins: mmc2-pins {
380 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
381 "PC10", "PC11", "PC12", "PC13", "PC14",
382 "PC15", "PC24";
383 function = "mmc2";
384 drive-strength = <30>;
385 bias-pull-up;
386 };
388 uart0_pb_pins: uart0-pb-pins {
389 pins = "PB22", "PB23";
390 function = "uart0";
391 };
393 uart3_pg_pins: uart3-pg-pins {
394 pins = "PG6", "PG7";
395 function = "uart3";
396 };
398 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
399 pins = "PG8", "PG9";
400 function = "uart3";
401 };
402 };
404 wdt: watchdog@1c20c90 {
405 compatible = "allwinner,sun4i-a10-wdt";
406 reg = <0x01c20c90 0x10>;
407 };
409 uart0: serial@1c28000 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x01c28000 0x400>;
412 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clocks = <&ccu CLK_BUS_UART0>;
416 resets = <&ccu RST_BUS_UART0>;
417 status = "disabled";
418 };
420 uart1: serial@1c28400 {
421 compatible = "snps,dw-apb-uart";
422 reg = <0x01c28400 0x400>;
423 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
424 reg-shift = <2>;
425 reg-io-width = <4>;
426 clocks = <&ccu CLK_BUS_UART1>;
427 resets = <&ccu RST_BUS_UART1>;
428 status = "disabled";
429 };
431 uart2: serial@1c28800 {
432 compatible = "snps,dw-apb-uart";
433 reg = <0x01c28800 0x400>;
434 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
435 reg-shift = <2>;
436 reg-io-width = <4>;
437 clocks = <&ccu CLK_BUS_UART2>;
438 resets = <&ccu RST_BUS_UART2>;
439 status = "disabled";
440 };
442 uart3: serial@1c28c00 {
443 compatible = "snps,dw-apb-uart";
444 reg = <0x01c28c00 0x400>;
445 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
446 reg-shift = <2>;
447 reg-io-width = <4>;
448 clocks = <&ccu CLK_BUS_UART3>;
449 resets = <&ccu RST_BUS_UART3>;
450 status = "disabled";
451 };
453 uart4: serial@1c29000 {
454 compatible = "snps,dw-apb-uart";
455 reg = <0x01c29000 0x400>;
456 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
457 reg-shift = <2>;
458 reg-io-width = <4>;
459 clocks = <&ccu CLK_BUS_UART4>;
460 resets = <&ccu RST_BUS_UART4>;
461 status = "disabled";
462 };
464 uart5: serial@1c29400 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c29400 0x400>;
467 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
468 reg-shift = <2>;
469 reg-io-width = <4>;
470 clocks = <&ccu CLK_BUS_UART5>;
471 resets = <&ccu RST_BUS_UART5>;
472 status = "disabled";
473 };
475 uart6: serial@1c29800 {
476 compatible = "snps,dw-apb-uart";
477 reg = <0x01c29800 0x400>;
478 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
479 reg-shift = <2>;
480 reg-io-width = <4>;
481 clocks = <&ccu CLK_BUS_UART6>;
482 resets = <&ccu RST_BUS_UART6>;
483 status = "disabled";
484 };
486 uart7: serial@1c29c00 {
487 compatible = "snps,dw-apb-uart";
488 reg = <0x01c29c00 0x400>;
489 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
490 reg-shift = <2>;
491 reg-io-width = <4>;
492 clocks = <&ccu CLK_BUS_UART7>;
493 resets = <&ccu RST_BUS_UART7>;
494 status = "disabled";
495 };
497 i2c0: i2c@1c2ac00 {
498 compatible = "allwinner,sun6i-a31-i2c";
499 reg = <0x01c2ac00 0x400>;
500 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&ccu CLK_BUS_I2C0>;
502 resets = <&ccu RST_BUS_I2C0>;
503 pinctrl-0 = <&i2c0_pins>;
504 pinctrl-names = "default";
505 status = "disabled";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 };
510 i2c1: i2c@1c2b000 {
511 compatible = "allwinner,sun6i-a31-i2c";
512 reg = <0x01c2b000 0x400>;
513 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ccu CLK_BUS_I2C1>;
515 resets = <&ccu RST_BUS_I2C1>;
516 status = "disabled";
517 #address-cells = <1>;
518 #size-cells = <0>;
519 };
521 i2c2: i2c@1c2b400 {
522 compatible = "allwinner,sun6i-a31-i2c";
523 reg = <0x01c2b400 0x400>;
524 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&ccu CLK_BUS_I2C2>;
526 resets = <&ccu RST_BUS_I2C2>;
527 status = "disabled";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 };
532 i2c3: i2c@1c2b800 {
533 compatible = "allwinner,sun6i-a31-i2c";
534 reg = <0x01c2b800 0x400>;
535 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&ccu CLK_BUS_I2C3>;
537 resets = <&ccu RST_BUS_I2C3>;
538 status = "disabled";
539 #address-cells = <1>;
540 #size-cells = <0>;
541 };
543 i2c4: i2c@1c2c000 {
544 compatible = "allwinner,sun6i-a31-i2c";
545 reg = <0x01c2c000 0x400>;
546 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&ccu CLK_BUS_I2C4>;
548 resets = <&ccu RST_BUS_I2C4>;
549 status = "disabled";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 };
554 ahci: sata@1c18000 {
555 compatible = "allwinner,sun8i-r40-ahci";
556 reg = <0x01c18000 0x1000>;
557 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
559 resets = <&ccu RST_BUS_SATA>;
560 reset-names = "ahci";
561 status = "disabled";
563 };
565 gmac: ethernet@1c50000 {
566 compatible = "allwinner,sun8i-r40-gmac";
567 syscon = <&ccu>;
568 reg = <0x01c50000 0x10000>;
569 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
570 interrupt-names = "macirq";
571 resets = <&ccu RST_BUS_GMAC>;
572 reset-names = "stmmaceth";
573 clocks = <&ccu CLK_BUS_GMAC>;
574 clock-names = "stmmaceth";
575 status = "disabled";
577 gmac_mdio: mdio {
578 compatible = "snps,dwmac-mdio";
579 #address-cells = <1>;
580 #size-cells = <0>;
581 };
582 };
584 tcon_top: tcon-top@1c70000 {
585 compatible = "allwinner,sun8i-r40-tcon-top";
586 reg = <0x01c70000 0x1000>;
587 clocks = <&ccu CLK_BUS_TCON_TOP>,
588 <&ccu CLK_TCON_TV0>,
589 <&ccu CLK_TVE0>,
590 <&ccu CLK_TCON_TV1>,
591 <&ccu CLK_TVE1>,
592 <&ccu CLK_DSI_DPHY>;
593 clock-names = "bus",
594 "tcon-tv0",
595 "tve0",
596 "tcon-tv1",
597 "tve1",
598 "dsi";
599 clock-output-names = "tcon-top-tv0",
600 "tcon-top-tv1",
601 "tcon-top-dsi";
602 resets = <&ccu RST_BUS_TCON_TOP>;
603 #clock-cells = <1>;
605 ports {
606 #address-cells = <1>;
607 #size-cells = <0>;
609 tcon_top_mixer0_in: port@0 {
610 reg = <0>;
612 tcon_top_mixer0_in_mixer0: endpoint {
613 remote-endpoint = <&mixer0_out_tcon_top>;
614 };
615 };
617 tcon_top_mixer0_out: port@1 {
618 #address-cells = <1>;
619 #size-cells = <0>;
620 reg = <1>;
622 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
623 reg = <0>;
624 };
626 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
627 reg = <1>;
628 };
630 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
631 reg = <2>;
632 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
633 };
635 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
636 reg = <3>;
637 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
638 };
639 };
641 tcon_top_mixer1_in: port@2 {
642 #address-cells = <1>;
643 #size-cells = <0>;
644 reg = <2>;
646 tcon_top_mixer1_in_mixer1: endpoint@1 {
647 reg = <1>;
648 remote-endpoint = <&mixer1_out_tcon_top>;
649 };
650 };
652 tcon_top_mixer1_out: port@3 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 reg = <3>;
657 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
658 reg = <0>;
659 };
661 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
662 reg = <1>;
663 };
665 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
666 reg = <2>;
667 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
668 };
670 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
671 reg = <3>;
672 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
673 };
674 };
676 tcon_top_hdmi_in: port@4 {
677 #address-cells = <1>;
678 #size-cells = <0>;
679 reg = <4>;
681 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
682 reg = <0>;
683 remote-endpoint = <&tcon_tv0_out_tcon_top>;
684 };
686 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
687 reg = <1>;
688 remote-endpoint = <&tcon_tv1_out_tcon_top>;
689 };
690 };
692 tcon_top_hdmi_out: port@5 {
693 reg = <5>;
695 tcon_top_hdmi_out_hdmi: endpoint {
696 remote-endpoint = <&hdmi_in_tcon_top>;
697 };
698 };
699 };
700 };
702 tcon_tv0: lcd-controller@1c73000 {
703 compatible = "allwinner,sun8i-r40-tcon-tv";
704 reg = <0x01c73000 0x1000>;
705 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
707 clock-names = "ahb", "tcon-ch1";
708 resets = <&ccu RST_BUS_TCON_TV0>;
709 reset-names = "lcd";
710 status = "disabled";
712 ports {
713 #address-cells = <1>;
714 #size-cells = <0>;
716 tcon_tv0_in: port@0 {
717 #address-cells = <1>;
718 #size-cells = <0>;
719 reg = <0>;
721 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
722 reg = <0>;
723 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
724 };
726 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
727 reg = <1>;
728 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
729 };
730 };
732 tcon_tv0_out: port@1 {
733 #address-cells = <1>;
734 #size-cells = <0>;
735 reg = <1>;
737 tcon_tv0_out_tcon_top: endpoint@1 {
738 reg = <1>;
739 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
740 };
741 };
742 };
743 };
745 tcon_tv1: lcd-controller@1c74000 {
746 compatible = "allwinner,sun8i-r40-tcon-tv";
747 reg = <0x01c74000 0x1000>;
748 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
750 clock-names = "ahb", "tcon-ch1";
751 resets = <&ccu RST_BUS_TCON_TV1>;
752 reset-names = "lcd";
753 status = "disabled";
755 ports {
756 #address-cells = <1>;
757 #size-cells = <0>;
759 tcon_tv1_in: port@0 {
760 #address-cells = <1>;
761 #size-cells = <0>;
762 reg = <0>;
764 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
765 reg = <0>;
766 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
767 };
769 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
770 reg = <1>;
771 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
772 };
773 };
775 tcon_tv1_out: port@1 {
776 #address-cells = <1>;
777 #size-cells = <0>;
778 reg = <1>;
780 tcon_tv1_out_tcon_top: endpoint@1 {
781 reg = <1>;
782 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
783 };
784 };
785 };
786 };
788 gic: interrupt-controller@1c81000 {
789 compatible = "arm,gic-400";
790 reg = <0x01c81000 0x1000>,
791 <0x01c82000 0x1000>,
792 <0x01c84000 0x2000>,
793 <0x01c86000 0x2000>;
794 interrupt-controller;
795 #interrupt-cells = <3>;
796 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
797 };
799 hdmi: hdmi@1ee0000 {
800 compatible = "allwinner,sun8i-r40-dw-hdmi",
801 "allwinner,sun8i-a83t-dw-hdmi";
802 reg = <0x01ee0000 0x10000>;
803 reg-io-width = <1>;
804 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
806 <&ccu CLK_HDMI>;
807 clock-names = "iahb", "isfr", "tmds";
808 resets = <&ccu RST_BUS_HDMI1>;
809 reset-names = "ctrl";
810 phys = <&hdmi_phy>;
811 phy-names = "hdmi-phy";
812 status = "disabled";
814 ports {
815 #address-cells = <1>;
816 #size-cells = <0>;
818 hdmi_in: port@0 {
819 reg = <0>;
821 hdmi_in_tcon_top: endpoint {
822 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
823 };
824 };
826 hdmi_out: port@1 {
827 reg = <1>;
828 };
829 };
830 };
832 hdmi_phy: hdmi-phy@1ef0000 {
833 compatible = "allwinner,sun8i-r40-hdmi-phy";
834 reg = <0x01ef0000 0x10000>;
835 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
836 <&ccu 7>, <&ccu 16>;
837 clock-names = "bus", "mod", "pll-0", "pll-1";
838 resets = <&ccu RST_BUS_HDMI0>;
839 reset-names = "phy";
840 #phy-cells = <0>;
841 };
842 };
844 timer {
845 compatible = "arm,armv7-timer";
846 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
847 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
848 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
849 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
850 };
851 };