| blob | e074258d451836c65276d79d693e1192e4b2ec65 |
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 / {
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&lic>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 memory@80000000 {
15 device_type = "memory";
16 reg = <0x80000000 0x0>;
17 };
19 pcie@3000 {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
35 #address-cells = <3>;
36 #size-cells = <2>;
38 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
39 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
40 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
41 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
42 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
43 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
45 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
46 <&tegra_car TEGRA30_CLK_AFI>,
47 <&tegra_car TEGRA30_CLK_PLL_E>,
48 <&tegra_car TEGRA30_CLK_CML0>;
49 clock-names = "pex", "afi", "pll_e", "cml";
50 resets = <&tegra_car 70>,
51 <&tegra_car 72>,
52 <&tegra_car 74>;
53 reset-names = "pex", "afi", "pcie_x";
54 status = "disabled";
56 pci@1,0 {
57 device_type = "pci";
58 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
59 reg = <0x000800 0 0 0 0>;
60 bus-range = <0x00 0xff>;
61 status = "disabled";
63 #address-cells = <3>;
64 #size-cells = <2>;
65 ranges;
67 nvidia,num-lanes = <2>;
68 };
70 pci@2,0 {
71 device_type = "pci";
72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
74 bus-range = <0x00 0xff>;
75 status = "disabled";
77 #address-cells = <3>;
78 #size-cells = <2>;
79 ranges;
81 nvidia,num-lanes = <2>;
82 };
84 pci@3,0 {
85 device_type = "pci";
86 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
87 reg = <0x001800 0 0 0 0>;
88 bus-range = <0x00 0xff>;
89 status = "disabled";
91 #address-cells = <3>;
92 #size-cells = <2>;
93 ranges;
95 nvidia,num-lanes = <2>;
96 };
97 };
99 iram@40000000 {
100 compatible = "mmio-sram";
101 reg = <0x40000000 0x40000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x40000000 0x40000>;
106 vde_pool: vde@400 {
107 reg = <0x400 0x3fc00>;
108 pool;
109 };
110 };
112 host1x@50000000 {
113 compatible = "nvidia,tegra30-host1x", "simple-bus";
114 reg = <0x50000000 0x00024000>;
115 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
116 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
117 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
118 resets = <&tegra_car 28>;
119 reset-names = "host1x";
120 iommus = <&mc TEGRA_SWGROUP_HC>;
122 #address-cells = <1>;
123 #size-cells = <1>;
125 ranges = <0x54000000 0x54000000 0x04000000>;
127 mpe@54040000 {
128 compatible = "nvidia,tegra30-mpe";
129 reg = <0x54040000 0x00040000>;
130 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&tegra_car TEGRA30_CLK_MPE>;
132 resets = <&tegra_car 60>;
133 reset-names = "mpe";
135 iommus = <&mc TEGRA_SWGROUP_MPE>;
136 };
138 vi@54080000 {
139 compatible = "nvidia,tegra30-vi";
140 reg = <0x54080000 0x00040000>;
141 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA30_CLK_VI>;
143 resets = <&tegra_car 20>;
144 reset-names = "vi";
146 iommus = <&mc TEGRA_SWGROUP_VI>;
147 };
149 epp@540c0000 {
150 compatible = "nvidia,tegra30-epp";
151 reg = <0x540c0000 0x00040000>;
152 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&tegra_car TEGRA30_CLK_EPP>;
154 resets = <&tegra_car 19>;
155 reset-names = "epp";
157 iommus = <&mc TEGRA_SWGROUP_EPP>;
158 };
160 isp@54100000 {
161 compatible = "nvidia,tegra30-isp";
162 reg = <0x54100000 0x00040000>;
163 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA30_CLK_ISP>;
165 resets = <&tegra_car 23>;
166 reset-names = "isp";
168 iommus = <&mc TEGRA_SWGROUP_ISP>;
169 };
171 gr2d@54140000 {
172 compatible = "nvidia,tegra30-gr2d";
173 reg = <0x54140000 0x00040000>;
174 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
176 resets = <&tegra_car 21>;
177 reset-names = "2d";
179 iommus = <&mc TEGRA_SWGROUP_G2>;
180 };
182 gr3d@54180000 {
183 compatible = "nvidia,tegra30-gr3d";
184 reg = <0x54180000 0x00040000>;
185 clocks = <&tegra_car TEGRA30_CLK_GR3D
186 &tegra_car TEGRA30_CLK_GR3D2>;
187 clock-names = "3d", "3d2";
188 resets = <&tegra_car 24>,
189 <&tegra_car 98>;
190 reset-names = "3d", "3d2";
192 iommus = <&mc TEGRA_SWGROUP_NV>,
193 <&mc TEGRA_SWGROUP_NV2>;
194 };
196 dc@54200000 {
197 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
198 reg = <0x54200000 0x00040000>;
199 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
201 <&tegra_car TEGRA30_CLK_PLL_P>;
202 clock-names = "dc", "parent";
203 resets = <&tegra_car 27>;
204 reset-names = "dc";
206 iommus = <&mc TEGRA_SWGROUP_DC>;
208 nvidia,head = <0>;
210 rgb {
211 status = "disabled";
212 };
213 };
215 dc@54240000 {
216 compatible = "nvidia,tegra30-dc";
217 reg = <0x54240000 0x00040000>;
218 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
220 <&tegra_car TEGRA30_CLK_PLL_P>;
221 clock-names = "dc", "parent";
222 resets = <&tegra_car 26>;
223 reset-names = "dc";
225 iommus = <&mc TEGRA_SWGROUP_DCB>;
227 nvidia,head = <1>;
229 rgb {
230 status = "disabled";
231 };
232 };
234 hdmi@54280000 {
235 compatible = "nvidia,tegra30-hdmi";
236 reg = <0x54280000 0x00040000>;
237 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
239 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
240 clock-names = "hdmi", "parent";
241 resets = <&tegra_car 51>;
242 reset-names = "hdmi";
243 status = "disabled";
244 };
246 tvo@542c0000 {
247 compatible = "nvidia,tegra30-tvo";
248 reg = <0x542c0000 0x00040000>;
249 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&tegra_car TEGRA30_CLK_TVO>;
251 status = "disabled";
252 };
254 dsi@54300000 {
255 compatible = "nvidia,tegra30-dsi";
256 reg = <0x54300000 0x00040000>;
257 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
258 resets = <&tegra_car 48>;
259 reset-names = "dsi";
260 status = "disabled";
261 };
262 };
264 timer@50040600 {
265 compatible = "arm,cortex-a9-twd-timer";
266 reg = <0x50040600 0x20>;
267 interrupt-parent = <&intc>;
268 interrupts = <GIC_PPI 13
269 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
270 clocks = <&tegra_car TEGRA30_CLK_TWD>;
271 };
273 intc: interrupt-controller@50041000 {
274 compatible = "arm,cortex-a9-gic";
275 reg = <0x50041000 0x1000
276 0x50040100 0x0100>;
277 interrupt-controller;
278 #interrupt-cells = <3>;
279 interrupt-parent = <&intc>;
280 };
282 cache-controller@50043000 {
283 compatible = "arm,pl310-cache";
284 reg = <0x50043000 0x1000>;
285 arm,data-latency = <6 6 2>;
286 arm,tag-latency = <5 5 2>;
287 cache-unified;
288 cache-level = <2>;
289 };
291 lic: interrupt-controller@60004000 {
292 compatible = "nvidia,tegra30-ictlr";
293 reg = <0x60004000 0x100>,
294 <0x60004100 0x50>,
295 <0x60004200 0x50>,
296 <0x60004300 0x50>,
297 <0x60004400 0x50>;
298 interrupt-controller;
299 #interrupt-cells = <3>;
300 interrupt-parent = <&intc>;
301 };
303 timer@60005000 {
304 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
305 reg = <0x60005000 0x400>;
306 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
313 };
315 tegra_car: clock@60006000 {
316 compatible = "nvidia,tegra30-car";
317 reg = <0x60006000 0x1000>;
318 #clock-cells = <1>;
319 #reset-cells = <1>;
320 };
322 flow-controller@60007000 {
323 compatible = "nvidia,tegra30-flowctrl";
324 reg = <0x60007000 0x1000>;
325 };
327 apbdma: dma@6000a000 {
328 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
329 reg = <0x6000a000 0x1400>;
330 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
363 resets = <&tegra_car 34>;
364 reset-names = "dma";
365 #dma-cells = <1>;
366 };
368 ahb: ahb@6000c000 {
369 compatible = "nvidia,tegra30-ahb";
370 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
371 };
373 actmon@6000c800 {
374 compatible = "nvidia,tegra30-actmon";
375 reg = <0x6000c800 0x400>;
376 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
378 <&tegra_car TEGRA30_CLK_EMC>;
379 clock-names = "actmon", "emc";
380 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
381 reset-names = "actmon";
382 };
384 gpio: gpio@6000d000 {
385 compatible = "nvidia,tegra30-gpio";
386 reg = <0x6000d000 0x1000>;
387 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
395 #gpio-cells = <2>;
396 gpio-controller;
397 #interrupt-cells = <2>;
398 interrupt-controller;
399 /*
400 gpio-ranges = <&pinmux 0 0 248>;
401 */
402 };
404 vde@6001a000 {
405 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
406 reg = <0x6001a000 0x1000 /* Syntax Engine */
407 0x6001b000 0x1000 /* Video Bitstream Engine */
408 0x6001c000 0x100 /* Macroblock Engine */
409 0x6001c200 0x100 /* Post-processing Engine */
410 0x6001c400 0x100 /* Motion Compensation Engine */
411 0x6001c600 0x100 /* Transform Engine */
412 0x6001c800 0x100 /* Pixel prediction block */
413 0x6001ca00 0x100 /* Video DMA */
414 0x6001d800 0x400>; /* Video frame controls */
415 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
416 "tfe", "ppb", "vdma", "frameid";
417 iram = <&vde_pool>; /* IRAM region */
418 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
419 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
420 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
421 interrupt-names = "sync-token", "bsev", "sxe";
422 clocks = <&tegra_car TEGRA30_CLK_VDE>;
423 reset-names = "vde", "mc";
424 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
425 };
427 apbmisc@70000800 {
428 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
429 reg = <0x70000800 0x64 /* Chip revision */
430 0x70000008 0x04>; /* Strapping options */
431 };
433 pinmux: pinmux@70000868 {
434 compatible = "nvidia,tegra30-pinmux";
435 reg = <0x70000868 0xd4 /* Pad control registers */
436 0x70003000 0x3e4>; /* Mux registers */
437 };
439 /*
440 * There are two serial driver i.e. 8250 based simple serial
441 * driver and APB DMA based serial driver for higher baudrate
442 * and performace. To enable the 8250 based driver, the compatible
443 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
444 * the APB DMA based serial driver, the compatible is
445 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
446 */
447 uarta: serial@70006000 {
448 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
449 reg = <0x70006000 0x40>;
450 reg-shift = <2>;
451 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
453 resets = <&tegra_car 6>;
454 reset-names = "serial";
455 dmas = <&apbdma 8>, <&apbdma 8>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
460 uartb: serial@70006040 {
461 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
462 reg = <0x70006040 0x40>;
463 reg-shift = <2>;
464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
466 resets = <&tegra_car 7>;
467 reset-names = "serial";
468 dmas = <&apbdma 9>, <&apbdma 9>;
469 dma-names = "rx", "tx";
470 status = "disabled";
471 };
473 uartc: serial@70006200 {
474 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
475 reg = <0x70006200 0x100>;
476 reg-shift = <2>;
477 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
479 resets = <&tegra_car 55>;
480 reset-names = "serial";
481 dmas = <&apbdma 10>, <&apbdma 10>;
482 dma-names = "rx", "tx";
483 status = "disabled";
484 };
486 uartd: serial@70006300 {
487 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
488 reg = <0x70006300 0x100>;
489 reg-shift = <2>;
490 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
492 resets = <&tegra_car 65>;
493 reset-names = "serial";
494 dmas = <&apbdma 19>, <&apbdma 19>;
495 dma-names = "rx", "tx";
496 status = "disabled";
497 };
499 uarte: serial@70006400 {
500 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
501 reg = <0x70006400 0x100>;
502 reg-shift = <2>;
503 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
505 resets = <&tegra_car 66>;
506 reset-names = "serial";
507 dmas = <&apbdma 20>, <&apbdma 20>;
508 dma-names = "rx", "tx";
509 status = "disabled";
510 };
512 gmi@70009000 {
513 compatible = "nvidia,tegra30-gmi";
514 reg = <0x70009000 0x1000>;
515 #address-cells = <2>;
516 #size-cells = <1>;
517 ranges = <0 0 0x48000000 0x7ffffff>;
518 clocks = <&tegra_car TEGRA30_CLK_NOR>;
519 clock-names = "gmi";
520 resets = <&tegra_car 42>;
521 reset-names = "gmi";
522 status = "disabled";
523 };
525 pwm: pwm@7000a000 {
526 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
527 reg = <0x7000a000 0x100>;
528 #pwm-cells = <2>;
529 clocks = <&tegra_car TEGRA30_CLK_PWM>;
530 resets = <&tegra_car 17>;
531 reset-names = "pwm";
532 status = "disabled";
533 };
535 rtc@7000e000 {
536 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
537 reg = <0x7000e000 0x100>;
538 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&tegra_car TEGRA30_CLK_RTC>;
540 };
542 i2c@7000c000 {
543 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
544 reg = <0x7000c000 0x100>;
545 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
549 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
550 clock-names = "div-clk", "fast-clk";
551 resets = <&tegra_car 12>;
552 reset-names = "i2c";
553 dmas = <&apbdma 21>, <&apbdma 21>;
554 dma-names = "rx", "tx";
555 status = "disabled";
556 };
558 i2c@7000c400 {
559 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
560 reg = <0x7000c400 0x100>;
561 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
565 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
566 clock-names = "div-clk", "fast-clk";
567 resets = <&tegra_car 54>;
568 reset-names = "i2c";
569 dmas = <&apbdma 22>, <&apbdma 22>;
570 dma-names = "rx", "tx";
571 status = "disabled";
572 };
574 i2c@7000c500 {
575 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
576 reg = <0x7000c500 0x100>;
577 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
581 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
582 clock-names = "div-clk", "fast-clk";
583 resets = <&tegra_car 67>;
584 reset-names = "i2c";
585 dmas = <&apbdma 23>, <&apbdma 23>;
586 dma-names = "rx", "tx";
587 status = "disabled";
588 };
590 i2c@7000c700 {
591 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
592 reg = <0x7000c700 0x100>;
593 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
594 #address-cells = <1>;
595 #size-cells = <0>;
596 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
597 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
598 resets = <&tegra_car 103>;
599 reset-names = "i2c";
600 clock-names = "div-clk", "fast-clk";
601 dmas = <&apbdma 26>, <&apbdma 26>;
602 dma-names = "rx", "tx";
603 status = "disabled";
604 };
606 i2c@7000d000 {
607 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
608 reg = <0x7000d000 0x100>;
609 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
611 #size-cells = <0>;
612 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
613 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
614 clock-names = "div-clk", "fast-clk";
615 resets = <&tegra_car 47>;
616 reset-names = "i2c";
617 dmas = <&apbdma 24>, <&apbdma 24>;
618 dma-names = "rx", "tx";
619 status = "disabled";
620 };
622 spi@7000d400 {
623 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
624 reg = <0x7000d400 0x200>;
625 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
626 #address-cells = <1>;
627 #size-cells = <0>;
628 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
629 resets = <&tegra_car 41>;
630 reset-names = "spi";
631 dmas = <&apbdma 15>, <&apbdma 15>;
632 dma-names = "rx", "tx";
633 status = "disabled";
634 };
636 spi@7000d600 {
637 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
638 reg = <0x7000d600 0x200>;
639 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
641 #size-cells = <0>;
642 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
643 resets = <&tegra_car 44>;
644 reset-names = "spi";
645 dmas = <&apbdma 16>, <&apbdma 16>;
646 dma-names = "rx", "tx";
647 status = "disabled";
648 };
650 spi@7000d800 {
651 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
652 reg = <0x7000d800 0x200>;
653 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
654 #address-cells = <1>;
655 #size-cells = <0>;
656 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
657 resets = <&tegra_car 46>;
658 reset-names = "spi";
659 dmas = <&apbdma 17>, <&apbdma 17>;
660 dma-names = "rx", "tx";
661 status = "disabled";
662 };
664 spi@7000da00 {
665 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
666 reg = <0x7000da00 0x200>;
667 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
671 resets = <&tegra_car 68>;
672 reset-names = "spi";
673 dmas = <&apbdma 18>, <&apbdma 18>;
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
678 spi@7000dc00 {
679 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
680 reg = <0x7000dc00 0x200>;
681 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
682 #address-cells = <1>;
683 #size-cells = <0>;
684 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
685 resets = <&tegra_car 104>;
686 reset-names = "spi";
687 dmas = <&apbdma 27>, <&apbdma 27>;
688 dma-names = "rx", "tx";
689 status = "disabled";
690 };
692 spi@7000de00 {
693 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
694 reg = <0x7000de00 0x200>;
695 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
699 resets = <&tegra_car 106>;
700 reset-names = "spi";
701 dmas = <&apbdma 28>, <&apbdma 28>;
702 dma-names = "rx", "tx";
703 status = "disabled";
704 };
706 kbc@7000e200 {
707 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
708 reg = <0x7000e200 0x100>;
709 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&tegra_car TEGRA30_CLK_KBC>;
711 resets = <&tegra_car 36>;
712 reset-names = "kbc";
713 status = "disabled";
714 };
716 pmc@7000e400 {
717 compatible = "nvidia,tegra30-pmc";
718 reg = <0x7000e400 0x400>;
719 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
720 clock-names = "pclk", "clk32k_in";
721 };
723 mc: memory-controller@7000f000 {
724 compatible = "nvidia,tegra30-mc";
725 reg = <0x7000f000 0x400>;
726 clocks = <&tegra_car TEGRA30_CLK_MC>;
727 clock-names = "mc";
729 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
731 #iommu-cells = <1>;
732 #reset-cells = <1>;
733 };
735 fuse@7000f800 {
736 compatible = "nvidia,tegra30-efuse";
737 reg = <0x7000f800 0x400>;
738 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
739 clock-names = "fuse";
740 resets = <&tegra_car 39>;
741 reset-names = "fuse";
742 };
744 hda@70030000 {
745 compatible = "nvidia,tegra30-hda";
746 reg = <0x70030000 0x10000>;
747 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&tegra_car TEGRA30_CLK_HDA>,
749 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
750 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
751 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
752 resets = <&tegra_car 125>, /* hda */
753 <&tegra_car 128>, /* hda2hdmi */
754 <&tegra_car 111>; /* hda2codec_2x */
755 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
756 status = "disabled";
757 };
759 ahub@70080000 {
760 compatible = "nvidia,tegra30-ahub";
761 reg = <0x70080000 0x200
762 0x70080200 0x100>;
763 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
765 <&tegra_car TEGRA30_CLK_APBIF>;
766 clock-names = "d_audio", "apbif";
767 resets = <&tegra_car 106>, /* d_audio */
768 <&tegra_car 107>, /* apbif */
769 <&tegra_car 30>, /* i2s0 */
770 <&tegra_car 11>, /* i2s1 */
771 <&tegra_car 18>, /* i2s2 */
772 <&tegra_car 101>, /* i2s3 */
773 <&tegra_car 102>, /* i2s4 */
774 <&tegra_car 108>, /* dam0 */
775 <&tegra_car 109>, /* dam1 */
776 <&tegra_car 110>, /* dam2 */
777 <&tegra_car 10>; /* spdif */
778 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
779 "i2s3", "i2s4", "dam0", "dam1", "dam2",
780 "spdif";
781 dmas = <&apbdma 1>, <&apbdma 1>,
782 <&apbdma 2>, <&apbdma 2>,
783 <&apbdma 3>, <&apbdma 3>,
784 <&apbdma 4>, <&apbdma 4>;
785 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
786 "rx3", "tx3";
787 ranges;
788 #address-cells = <1>;
789 #size-cells = <1>;
791 tegra_i2s0: i2s@70080300 {
792 compatible = "nvidia,tegra30-i2s";
793 reg = <0x70080300 0x100>;
794 nvidia,ahub-cif-ids = <4 4>;
795 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
796 resets = <&tegra_car 30>;
797 reset-names = "i2s";
798 status = "disabled";
799 };
801 tegra_i2s1: i2s@70080400 {
802 compatible = "nvidia,tegra30-i2s";
803 reg = <0x70080400 0x100>;
804 nvidia,ahub-cif-ids = <5 5>;
805 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
806 resets = <&tegra_car 11>;
807 reset-names = "i2s";
808 status = "disabled";
809 };
811 tegra_i2s2: i2s@70080500 {
812 compatible = "nvidia,tegra30-i2s";
813 reg = <0x70080500 0x100>;
814 nvidia,ahub-cif-ids = <6 6>;
815 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
816 resets = <&tegra_car 18>;
817 reset-names = "i2s";
818 status = "disabled";
819 };
821 tegra_i2s3: i2s@70080600 {
822 compatible = "nvidia,tegra30-i2s";
823 reg = <0x70080600 0x100>;
824 nvidia,ahub-cif-ids = <7 7>;
825 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
826 resets = <&tegra_car 101>;
827 reset-names = "i2s";
828 status = "disabled";
829 };
831 tegra_i2s4: i2s@70080700 {
832 compatible = "nvidia,tegra30-i2s";
833 reg = <0x70080700 0x100>;
834 nvidia,ahub-cif-ids = <8 8>;
835 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
836 resets = <&tegra_car 102>;
837 reset-names = "i2s";
838 status = "disabled";
839 };
840 };
842 sdhci@78000000 {
843 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
844 reg = <0x78000000 0x200>;
845 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
847 resets = <&tegra_car 14>;
848 reset-names = "sdhci";
849 status = "disabled";
850 };
852 sdhci@78000200 {
853 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
854 reg = <0x78000200 0x200>;
855 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
857 resets = <&tegra_car 9>;
858 reset-names = "sdhci";
859 status = "disabled";
860 };
862 sdhci@78000400 {
863 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
864 reg = <0x78000400 0x200>;
865 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
867 resets = <&tegra_car 69>;
868 reset-names = "sdhci";
869 status = "disabled";
870 };
872 sdhci@78000600 {
873 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
874 reg = <0x78000600 0x200>;
875 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
877 resets = <&tegra_car 15>;
878 reset-names = "sdhci";
879 status = "disabled";
880 };
882 usb@7d000000 {
883 compatible = "nvidia,tegra30-ehci", "usb-ehci";
884 reg = <0x7d000000 0x4000>;
885 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
886 phy_type = "utmi";
887 clocks = <&tegra_car TEGRA30_CLK_USBD>;
888 resets = <&tegra_car 22>;
889 reset-names = "usb";
890 nvidia,needs-double-reset;
891 nvidia,phy = <&phy1>;
892 status = "disabled";
893 };
895 phy1: usb-phy@7d000000 {
896 compatible = "nvidia,tegra30-usb-phy";
897 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
898 phy_type = "utmi";
899 clocks = <&tegra_car TEGRA30_CLK_USBD>,
900 <&tegra_car TEGRA30_CLK_PLL_U>,
901 <&tegra_car TEGRA30_CLK_USBD>;
902 clock-names = "reg", "pll_u", "utmi-pads";
903 resets = <&tegra_car 22>, <&tegra_car 22>;
904 reset-names = "usb", "utmi-pads";
905 nvidia,hssync-start-delay = <9>;
906 nvidia,idle-wait-delay = <17>;
907 nvidia,elastic-limit = <16>;
908 nvidia,term-range-adj = <6>;
909 nvidia,xcvr-setup = <51>;
910 nvidia,xcvr-setup-use-fuses;
911 nvidia,xcvr-lsfslew = <1>;
912 nvidia,xcvr-lsrslew = <1>;
913 nvidia,xcvr-hsslew = <32>;
914 nvidia,hssquelch-level = <2>;
915 nvidia,hsdiscon-level = <5>;
916 nvidia,has-utmi-pad-registers;
917 status = "disabled";
918 };
920 usb@7d004000 {
921 compatible = "nvidia,tegra30-ehci", "usb-ehci";
922 reg = <0x7d004000 0x4000>;
923 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
924 phy_type = "utmi";
925 clocks = <&tegra_car TEGRA30_CLK_USB2>;
926 resets = <&tegra_car 58>;
927 reset-names = "usb";
928 nvidia,phy = <&phy2>;
929 status = "disabled";
930 };
932 phy2: usb-phy@7d004000 {
933 compatible = "nvidia,tegra30-usb-phy";
934 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
935 phy_type = "utmi";
936 clocks = <&tegra_car TEGRA30_CLK_USB2>,
937 <&tegra_car TEGRA30_CLK_PLL_U>,
938 <&tegra_car TEGRA30_CLK_USBD>;
939 clock-names = "reg", "pll_u", "utmi-pads";
940 resets = <&tegra_car 58>, <&tegra_car 22>;
941 reset-names = "usb", "utmi-pads";
942 nvidia,hssync-start-delay = <9>;
943 nvidia,idle-wait-delay = <17>;
944 nvidia,elastic-limit = <16>;
945 nvidia,term-range-adj = <6>;
946 nvidia,xcvr-setup = <51>;
947 nvidia,xcvr-setup-use-fuses;
948 nvidia,xcvr-lsfslew = <2>;
949 nvidia,xcvr-lsrslew = <2>;
950 nvidia,xcvr-hsslew = <32>;
951 nvidia,hssquelch-level = <2>;
952 nvidia,hsdiscon-level = <5>;
953 status = "disabled";
954 };
956 usb@7d008000 {
957 compatible = "nvidia,tegra30-ehci", "usb-ehci";
958 reg = <0x7d008000 0x4000>;
959 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
960 phy_type = "utmi";
961 clocks = <&tegra_car TEGRA30_CLK_USB3>;
962 resets = <&tegra_car 59>;
963 reset-names = "usb";
964 nvidia,phy = <&phy3>;
965 status = "disabled";
966 };
968 phy3: usb-phy@7d008000 {
969 compatible = "nvidia,tegra30-usb-phy";
970 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
971 phy_type = "utmi";
972 clocks = <&tegra_car TEGRA30_CLK_USB3>,
973 <&tegra_car TEGRA30_CLK_PLL_U>,
974 <&tegra_car TEGRA30_CLK_USBD>;
975 clock-names = "reg", "pll_u", "utmi-pads";
976 resets = <&tegra_car 59>, <&tegra_car 22>;
977 reset-names = "usb", "utmi-pads";
978 nvidia,hssync-start-delay = <0>;
979 nvidia,idle-wait-delay = <17>;
980 nvidia,elastic-limit = <16>;
981 nvidia,term-range-adj = <6>;
982 nvidia,xcvr-setup = <51>;
983 nvidia,xcvr-setup-use-fuses;
984 nvidia,xcvr-lsfslew = <2>;
985 nvidia,xcvr-lsrslew = <2>;
986 nvidia,xcvr-hsslew = <32>;
987 nvidia,hssquelch-level = <2>;
988 nvidia,hsdiscon-level = <5>;
989 status = "disabled";
990 };
992 cpus {
993 #address-cells = <1>;
994 #size-cells = <0>;
996 cpu@0 {
997 device_type = "cpu";
998 compatible = "arm,cortex-a9";
999 reg = <0>;
1000 };
1002 cpu@1 {
1003 device_type = "cpu";
1004 compatible = "arm,cortex-a9";
1005 reg = <1>;
1006 };
1008 cpu@2 {
1009 device_type = "cpu";
1010 compatible = "arm,cortex-a9";
1011 reg = <2>;
1012 };
1014 cpu@3 {
1015 device_type = "cpu";
1016 compatible = "arm,cortex-a9";
1017 reg = <3>;
1018 };
1019 };
1021 pmu {
1022 compatible = "arm,cortex-a9-pmu";
1023 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1027 interrupt-affinity = <&{/cpus/cpu@0}>,
1028 <&{/cpus/cpu@1}>,
1029 <&{/cpus/cpu@2}>,
1030 <&{/cpus/cpu@3}>;
1031 };
1032 };