arch/arm/mach-w90x900/include/mach/map.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/mach-w90x900/include/mach/map.h
   4  *
   5  * Copyright (c) 2008 Nuvoton technology corporation.
   6  *
   7  * Wan ZongShun <mcuos.com@gmail.com>
   8  *
   9  * Based on arch/arm/mach-s3c2410/include/mach/map.h
  10  */
  11
  12 #ifndef __ASM_ARCH_MAP_H
  13 #define __ASM_ARCH_MAP_H
  14
  15 #ifndef __ASSEMBLY__
  16 #define W90X900_ADDR(x)         ((void __iomem *)(0xF0000000 + (x)))
  17 #else
  18 #define W90X900_ADDR(x)         (0xF0000000 + (x))
  19 #endif
  20
  21 #define AHB_IO_BASE             0xB0000000
  22 #define APB_IO_BASE             0xB8000000
  23 #define CLOCKPW_BASE            (APB_IO_BASE+0x200)
  24 #define AIC_IO_BASE             (APB_IO_BASE+0x2000)
  25 #define TIMER_IO_BASE           (APB_IO_BASE+0x1000)
  26
  27 /*
  28  * interrupt controller is the first thing we put in, to make
  29  * the assembly code for the irq detection easier
  30  */
  31 #define W90X900_VA_IRQ          W90X900_ADDR(0x00000000)
  32 #define W90X900_PA_IRQ          (0xB8002000)
  33 #define W90X900_SZ_IRQ          SZ_4K
  34
  35 #define W90X900_VA_GCR          W90X900_ADDR(0x08002000)
  36 #define W90X900_PA_GCR          (0xB0000000)
  37 #define W90X900_SZ_GCR          SZ_4K
  38
  39 /* Clock and Power management */
  40 #define W90X900_VA_CLKPWR       (W90X900_VA_GCR+0x200)
  41 #define W90X900_PA_CLKPWR       (0xB0000200)
  42 #define W90X900_SZ_CLKPWR       SZ_4K
  43
  44 /* EBI management */
  45 #define W90X900_VA_EBI          W90X900_ADDR(0x00001000)
  46 #define W90X900_PA_EBI          (0xB0001000)
  47 #define W90X900_SZ_EBI          SZ_4K
  48
  49 /* UARTs */
  50 #define W90X900_VA_UART         W90X900_ADDR(0x08000000)
  51 #define W90X900_PA_UART         (0xB8000000)
  52 #define W90X900_SZ_UART         SZ_4K
  53
  54 /* Timers */
  55 #define W90X900_VA_TIMER        W90X900_ADDR(0x08001000)
  56 #define W90X900_PA_TIMER        (0xB8001000)
  57 #define W90X900_SZ_TIMER        SZ_4K
  58
  59 /* GPIO ports */
  60 #define W90X900_VA_GPIO         W90X900_ADDR(0x08003000)
  61 #define W90X900_PA_GPIO         (0xB8003000)
  62 #define W90X900_SZ_GPIO         SZ_4K
  63
  64 /* GDMA control */
  65 #define W90X900_VA_GDMA         W90X900_ADDR(0x00004000)
  66 #define W90X900_PA_GDMA         (0xB0004000)
  67 #define W90X900_SZ_GDMA         SZ_4K
  68
  69 /* USB host controller*/
  70 #define W90X900_VA_USBEHCIHOST  W90X900_ADDR(0x00005000)
  71 #define W90X900_PA_USBEHCIHOST  (0xB0005000)
  72 #define W90X900_SZ_USBEHCIHOST  SZ_4K
  73
  74 #define W90X900_VA_USBOHCIHOST  W90X900_ADDR(0x00007000)
  75 #define W90X900_PA_USBOHCIHOST  (0xB0007000)
  76 #define W90X900_SZ_USBOHCIHOST  SZ_4K
  77
  78 /* I2C hardware controller */
  79 #define W90X900_VA_I2C          W90X900_ADDR(0x08006000)
  80 #define W90X900_PA_I2C          (0xB8006000)
  81 #define W90X900_SZ_I2C          SZ_4K
  82
  83 /* Keypad Interface*/
  84 #define W90X900_VA_KPI          W90X900_ADDR(0x08008000)
  85 #define W90X900_PA_KPI          (0xB8008000)
  86 #define W90X900_SZ_KPI          SZ_4K
  87
  88 /* Smart card host*/
  89 #define W90X900_VA_SC           W90X900_ADDR(0x08005000)
  90 #define W90X900_PA_SC           (0xB8005000)
  91 #define W90X900_SZ_SC           SZ_4K
  92
  93 /* LCD controller*/
  94 #define W90X900_VA_LCD          W90X900_ADDR(0x00008000)
  95 #define W90X900_PA_LCD          (0xB0008000)
  96 #define W90X900_SZ_LCD          SZ_4K
  97
  98 /* 2D controller*/
  99 #define W90X900_VA_GE           W90X900_ADDR(0x0000B000)
 100 #define W90X900_PA_GE           (0xB000B000)
 101 #define W90X900_SZ_GE           SZ_4K
 102
 103 /* ATAPI */
 104 #define W90X900_VA_ATAPI        W90X900_ADDR(0x0000A000)
 105 #define W90X900_PA_ATAPI        (0xB000A000)
 106 #define W90X900_SZ_ATAPI        SZ_4K
 107
 108 /* ADC */
 109 #define W90X900_VA_ADC          W90X900_ADDR(0x0800A000)
 110 #define W90X900_PA_ADC          (0xB800A000)
 111 #define W90X900_SZ_ADC          SZ_4K
 112
 113 /* PS2 Interface*/
 114 #define W90X900_VA_PS2          W90X900_ADDR(0x08009000)
 115 #define W90X900_PA_PS2          (0xB8009000)
 116 #define W90X900_SZ_PS2          SZ_4K
 117
 118 /* RTC */
 119 #define W90X900_VA_RTC          W90X900_ADDR(0x08004000)
 120 #define W90X900_PA_RTC          (0xB8004000)
 121 #define W90X900_SZ_RTC          SZ_4K
 122
 123 /* Pulse Width Modulation(PWM) Registers */
 124 #define W90X900_VA_PWM          W90X900_ADDR(0x08007000)
 125 #define W90X900_PA_PWM          (0xB8007000)
 126 #define W90X900_SZ_PWM          SZ_4K
 127
 128 /* Audio Controller controller */
 129 #define W90X900_VA_ACTL         W90X900_ADDR(0x00009000)
 130 #define W90X900_PA_ACTL         (0xB0009000)
 131 #define W90X900_SZ_ACTL         SZ_4K
 132
 133 /* DMA controller */
 134 #define W90X900_VA_DMA          W90X900_ADDR(0x0000c000)
 135 #define W90X900_PA_DMA          (0xB000c000)
 136 #define W90X900_SZ_DMA          SZ_4K
 137
 138 /* FMI controller */
 139 #define W90X900_VA_FMI          W90X900_ADDR(0x0000d000)
 140 #define W90X900_PA_FMI          (0xB000d000)
 141 #define W90X900_SZ_FMI          SZ_4K
 142
 143 /* USB Device port */
 144 #define W90X900_VA_USBDEV       W90X900_ADDR(0x00006000)
 145 #define W90X900_PA_USBDEV       (0xB0006000)
 146 #define W90X900_SZ_USBDEV       SZ_4K
 147
 148 /* External MAC control*/
 149 #define W90X900_VA_EMC          W90X900_ADDR(0x00003000)
 150 #define W90X900_PA_EMC          (0xB0003000)
 151 #define W90X900_SZ_EMC          SZ_4K
 152
 153 #endif /* __ASM_ARCH_MAP_H */