arch/arm/mach-w90x900/include/mach/regs-clock.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/mach-w90x900/include/mach/regs-clock.h
   4  *
   5  * Copyright (c) 2008 Nuvoton technology corporation.
   6  *
   7  * Wan ZongShun <mcuos.com@gmail.com>
   8  */
   9
  10 #ifndef __ASM_ARCH_REGS_CLOCK_H
  11 #define __ASM_ARCH_REGS_CLOCK_H
  12
  13 /* Clock Control Registers  */
  14 #define CLK_BA          W90X900_VA_CLKPWR
  15 #define REG_CLKEN       (CLK_BA + 0x00)
  16 #define REG_CLKSEL      (CLK_BA + 0x04)
  17 #define REG_CLKDIV      (CLK_BA + 0x08)
  18 #define REG_PLLCON0     (CLK_BA + 0x0C)
  19 #define REG_PLLCON1     (CLK_BA + 0x10)
  20 #define REG_PMCON       (CLK_BA + 0x14)
  21 #define REG_IRQWAKECON  (CLK_BA + 0x18)
  22 #define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
  23 #define REG_IPSRST      (CLK_BA + 0x20)
  24 #define REG_CLKEN1      (CLK_BA + 0x24)
  25 #define REG_CLKDIV1     (CLK_BA + 0x28)
  26
  27 /* Define PLL freq setting */
  28 #define PLL_DISABLE             0x12B63
  29 #define PLL_66MHZ               0x2B63
  30 #define PLL_100MHZ              0x4F64
  31 #define PLL_120MHZ              0x4F63
  32 #define PLL_166MHZ              0x4124
  33 #define PLL_200MHZ              0x4F24
  34
  35 /* Define AHB:CPUFREQ ratio */
  36 #define AHB_CPUCLK_1_1          0x00
  37 #define AHB_CPUCLK_1_2          0x01
  38 #define AHB_CPUCLK_1_4          0x02
  39 #define AHB_CPUCLK_1_8          0x03
  40
  41 /* Define APB:AHB ratio */
  42 #define APB_AHB_1_2             0x01
  43 #define APB_AHB_1_4             0x02
  44 #define APB_AHB_1_8             0x03
  45
  46 /* Define clock skew */
  47 #define DEFAULTSKEW             0x48
  48
  49 #endif /*  __ASM_ARCH_REGS_CLOCK_H */