arch/arm/mm/dma-mapping-nommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Based on linux/arch/arm/mm/dma-mapping.c
   4  *
   5  *  Copyright (C) 2000-2004 Russell King
   6  */
   7
   8 #include <linux/export.h>
   9 #include <linux/mm.h>
  10 #include <linux/dma-direct.h>
  11 #include <linux/scatterlist.h>
  12
  13 #include <asm/cachetype.h>
  14 #include <asm/cacheflush.h>
  15 #include <asm/outercache.h>
  16 #include <asm/cp15.h>
  17
  18 #include "dma.h"
  19
  20 /*
  21  *  The generic direct mapping code is used if
  22  *   - MMU/MPU is off
  23  *   - cpu is v7m w/o cache support
  24  *   - device is coherent
  25  *  otherwise arm_nommu_dma_ops is used.
  26  *
  27  *  arm_nommu_dma_ops rely on consistent DMA memory (please, refer to
  28  *  [1] on how to declare such memory).
  29  *
  30  *  [1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  31  */
  32
  33 static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
  34                                  dma_addr_t *dma_handle, gfp_t gfp,
  35                                  unsigned long attrs)
  36
  37 {
  38         void *ret = dma_alloc_from_global_coherent(size, dma_handle);
  39
  40         /*
  41          * dma_alloc_from_global_coherent() may fail because:
  42          *
  43          * - no consistent DMA region has been defined, so we can't
  44          *   continue.
  45          * - there is no space left in consistent DMA region, so we
  46          *   only can fallback to generic allocator if we are
  47          *   advertised that consistency is not required.
  48          */
  49
  50         WARN_ON_ONCE(ret == NULL);
  51         return ret;
  52 }
  53
  54 static void arm_nommu_dma_free(struct device *dev, size_t size,
  55                                void *cpu_addr, dma_addr_t dma_addr,
  56                                unsigned long attrs)
  57 {
  58         int ret = dma_release_from_global_coherent(get_order(size), cpu_addr);
  59
  60         WARN_ON_ONCE(ret == 0);
  61 }
  62
  63 static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
  64                               void *cpu_addr, dma_addr_t dma_addr, size_t size,
  65                               unsigned long attrs)
  66 {
  67         int ret;
  68
  69         if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
  70                 return ret;
  71
  72         return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
  73 }
  74
  75
  76 static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
  77                                   enum dma_data_direction dir)
  78 {
  79         dmac_map_area(__va(paddr), size, dir);
  80
  81         if (dir == DMA_FROM_DEVICE)
  82                 outer_inv_range(paddr, paddr + size);
  83         else
  84                 outer_clean_range(paddr, paddr + size);
  85 }
  86
  87 static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size,
  88                                   enum dma_data_direction dir)
  89 {
  90         if (dir != DMA_TO_DEVICE) {
  91                 outer_inv_range(paddr, paddr + size);
  92                 dmac_unmap_area(__va(paddr), size, dir);
  93         }
  94 }
  95
  96 static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page,
  97                                          unsigned long offset, size_t size,
  98                                          enum dma_data_direction dir,
  99                                          unsigned long attrs)
 100 {
 101         dma_addr_t handle = page_to_phys(page) + offset;
 102
 103         __dma_page_cpu_to_dev(handle, size, dir);
 104
 105         return handle;
 106 }
 107
 108 static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle,
 109                                      size_t size, enum dma_data_direction dir,
 110                                      unsigned long attrs)
 111 {
 112         __dma_page_dev_to_cpu(handle, size, dir);
 113 }
 114
 115
 116 static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl,
 117                                 int nents, enum dma_data_direction dir,
 118                                 unsigned long attrs)
 119 {
 120         int i;
 121         struct scatterlist *sg;
 122
 123         for_each_sg(sgl, sg, nents, i) {
 124                 sg_dma_address(sg) = sg_phys(sg);
 125                 sg_dma_len(sg) = sg->length;
 126                 __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
 127         }
 128
 129         return nents;
 130 }
 131
 132 static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
 133                                    int nents, enum dma_data_direction dir,
 134                                    unsigned long attrs)
 135 {
 136         struct scatterlist *sg;
 137         int i;
 138
 139         for_each_sg(sgl, sg, nents, i)
 140                 __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
 141 }
 142
 143 static void arm_nommu_dma_sync_single_for_device(struct device *dev,
 144                 dma_addr_t handle, size_t size, enum dma_data_direction dir)
 145 {
 146         __dma_page_cpu_to_dev(handle, size, dir);
 147 }
 148
 149 static void arm_nommu_dma_sync_single_for_cpu(struct device *dev,
 150                 dma_addr_t handle, size_t size, enum dma_data_direction dir)
 151 {
 152         __dma_page_cpu_to_dev(handle, size, dir);
 153 }
 154
 155 static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
 156                                              int nents, enum dma_data_direction dir)
 157 {
 158         struct scatterlist *sg;
 159         int i;
 160
 161         for_each_sg(sgl, sg, nents, i)
 162                 __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
 163 }
 164
 165 static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
 166                                           int nents, enum dma_data_direction dir)
 167 {
 168         struct scatterlist *sg;
 169         int i;
 170
 171         for_each_sg(sgl, sg, nents, i)
 172                 __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
 173 }
 174
 175 const struct dma_map_ops arm_nommu_dma_ops = {
 176         .alloc                  = arm_nommu_dma_alloc,
 177         .free                   = arm_nommu_dma_free,
 178         .mmap                   = arm_nommu_dma_mmap,
 179         .map_page               = arm_nommu_dma_map_page,
 180         .unmap_page             = arm_nommu_dma_unmap_page,
 181         .map_sg                 = arm_nommu_dma_map_sg,
 182         .unmap_sg               = arm_nommu_dma_unmap_sg,
 183         .sync_single_for_device = arm_nommu_dma_sync_single_for_device,
 184         .sync_single_for_cpu    = arm_nommu_dma_sync_single_for_cpu,
 185         .sync_sg_for_device     = arm_nommu_dma_sync_sg_for_device,
 186         .sync_sg_for_cpu        = arm_nommu_dma_sync_sg_for_cpu,
 187 };
 188 EXPORT_SYMBOL(arm_nommu_dma_ops);
 189
 190 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 191                         const struct iommu_ops *iommu, bool coherent)
 192 {
 193         if (IS_ENABLED(CONFIG_CPU_V7M)) {
 194                 /*
 195                  * Cache support for v7m is optional, so can be treated as
 196                  * coherent if no cache has been detected. Note that it is not
 197                  * enough to check if MPU is in use or not since in absense of
 198                  * MPU system memory map is used.
 199                  */
 200                 dev->archdata.dma_coherent = (cacheid) ? coherent : true;
 201         } else {
 202                 /*
 203                  * Assume coherent DMA in case MMU/MPU has not been set up.
 204                  */
 205                 dev->archdata.dma_coherent = (get_cr() & CR_M) ? coherent : true;
 206         }
 207
 208         if (!dev->archdata.dma_coherent)
 209                 set_dma_ops(dev, &arm_nommu_dma_ops);
 210 }