| blob | b05d78164fc178a64446e1b070b0d4dd7f023688 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 */
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
11 / {
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
21 service_reserved: svcbuffer@0 {
22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
25 no-map;
26 };
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
34 compatible = "arm,cortex-a53";
35 device_type = "cpu";
36 enable-method = "psci";
37 reg = <0x0>;
38 };
40 cpu1: cpu@1 {
41 compatible = "arm,cortex-a53";
42 device_type = "cpu";
43 enable-method = "psci";
44 reg = <0x1>;
45 };
47 cpu2: cpu@2 {
48 compatible = "arm,cortex-a53";
49 device_type = "cpu";
50 enable-method = "psci";
51 reg = <0x2>;
52 };
54 cpu3: cpu@3 {
55 compatible = "arm,cortex-a53";
56 device_type = "cpu";
57 enable-method = "psci";
58 reg = <0x3>;
59 };
60 };
62 pmu {
63 compatible = "arm,armv8-pmuv3";
64 interrupts = <0 120 8>,
65 <0 121 8>,
66 <0 122 8>,
67 <0 123 8>;
68 interrupt-affinity = <&cpu0>,
69 <&cpu1>,
70 <&cpu2>,
71 <&cpu3>;
72 interrupt-parent = <&intc>;
73 };
75 psci {
76 compatible = "arm,psci-0.2";
77 method = "smc";
78 };
80 intc: intc@fffc1000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
84 reg = <0x0 0xfffc1000 0x0 0x1000>,
85 <0x0 0xfffc2000 0x0 0x2000>,
86 <0x0 0xfffc4000 0x0 0x2000>,
87 <0x0 0xfffc6000 0x0 0x2000>;
88 };
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 device_type = "soc";
95 interrupt-parent = <&intc>;
96 ranges = <0 0 0 0xffffffff>;
98 base_fpga_region {
99 #address-cells = <0x1>;
100 #size-cells = <0x1>;
102 compatible = "fpga-region";
103 fpga-mgr = <&fpga_mgr>;
104 };
106 clkmgr: clock-controller@ffd10000 {
107 compatible = "intel,stratix10-clkmgr";
108 reg = <0xffd10000 0x1000>;
109 #clock-cells = <1>;
110 };
112 clocks {
113 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 };
118 cb_intosc_ls_clk: cb-intosc-ls-clk {
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 };
123 f2s_free_clk: f2s-free-clk {
124 #clock-cells = <0>;
125 compatible = "fixed-clock";
126 };
128 osc1: osc1 {
129 #clock-cells = <0>;
130 compatible = "fixed-clock";
131 };
133 qspi_clk: qspi-clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <200000000>;
137 };
138 };
140 gmac0: ethernet@ff800000 {
141 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
142 reg = <0xff800000 0x2000>;
143 interrupts = <0 90 4>;
144 interrupt-names = "macirq";
145 mac-address = [00 00 00 00 00 00];
146 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
147 reset-names = "stmmaceth", "stmmaceth-ocp";
148 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
149 clock-names = "stmmaceth";
150 tx-fifo-depth = <16384>;
151 rx-fifo-depth = <16384>;
152 snps,multicast-filter-bins = <256>;
153 iommus = <&smmu 1>;
154 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
155 status = "disabled";
156 };
158 gmac1: ethernet@ff802000 {
159 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
160 reg = <0xff802000 0x2000>;
161 interrupts = <0 91 4>;
162 interrupt-names = "macirq";
163 mac-address = [00 00 00 00 00 00];
164 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
165 reset-names = "stmmaceth", "stmmaceth-ocp";
166 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
167 clock-names = "stmmaceth";
168 tx-fifo-depth = <16384>;
169 rx-fifo-depth = <16384>;
170 snps,multicast-filter-bins = <256>;
171 iommus = <&smmu 2>;
172 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
173 status = "disabled";
174 };
176 gmac2: ethernet@ff804000 {
177 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
178 reg = <0xff804000 0x2000>;
179 interrupts = <0 92 4>;
180 interrupt-names = "macirq";
181 mac-address = [00 00 00 00 00 00];
182 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
183 reset-names = "stmmaceth", "stmmaceth-ocp";
184 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
185 clock-names = "stmmaceth";
186 tx-fifo-depth = <16384>;
187 rx-fifo-depth = <16384>;
188 snps,multicast-filter-bins = <256>;
189 iommus = <&smmu 3>;
190 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
191 status = "disabled";
192 };
194 gpio0: gpio@ffc03200 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "snps,dw-apb-gpio";
198 reg = <0xffc03200 0x100>;
199 resets = <&rst GPIO0_RESET>;
200 status = "disabled";
202 porta: gpio-controller@0 {
203 compatible = "snps,dw-apb-gpio-port";
204 gpio-controller;
205 #gpio-cells = <2>;
206 snps,nr-gpios = <24>;
207 reg = <0>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 interrupts = <0 110 4>;
211 };
212 };
214 gpio1: gpio@ffc03300 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "snps,dw-apb-gpio";
218 reg = <0xffc03300 0x100>;
219 resets = <&rst GPIO1_RESET>;
220 status = "disabled";
222 portb: gpio-controller@0 {
223 compatible = "snps,dw-apb-gpio-port";
224 gpio-controller;
225 #gpio-cells = <2>;
226 snps,nr-gpios = <24>;
227 reg = <0>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 interrupts = <0 111 4>;
231 };
232 };
234 i2c0: i2c@ffc02800 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "snps,designware-i2c";
238 reg = <0xffc02800 0x100>;
239 interrupts = <0 103 4>;
240 resets = <&rst I2C0_RESET>;
241 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
242 status = "disabled";
243 };
245 i2c1: i2c@ffc02900 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "snps,designware-i2c";
249 reg = <0xffc02900 0x100>;
250 interrupts = <0 104 4>;
251 resets = <&rst I2C1_RESET>;
252 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
253 status = "disabled";
254 };
256 i2c2: i2c@ffc02a00 {
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "snps,designware-i2c";
260 reg = <0xffc02a00 0x100>;
261 interrupts = <0 105 4>;
262 resets = <&rst I2C2_RESET>;
263 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
264 status = "disabled";
265 };
267 i2c3: i2c@ffc02b00 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "snps,designware-i2c";
271 reg = <0xffc02b00 0x100>;
272 interrupts = <0 106 4>;
273 resets = <&rst I2C3_RESET>;
274 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
275 status = "disabled";
276 };
278 i2c4: i2c@ffc02c00 {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "snps,designware-i2c";
282 reg = <0xffc02c00 0x100>;
283 interrupts = <0 107 4>;
284 resets = <&rst I2C4_RESET>;
285 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
286 status = "disabled";
287 };
289 mmc: dwmmc0@ff808000 {
290 #address-cells = <1>;
291 #size-cells = <0>;
292 compatible = "altr,socfpga-dw-mshc";
293 reg = <0xff808000 0x1000>;
294 interrupts = <0 96 4>;
295 fifo-depth = <0x400>;
296 resets = <&rst SDMMC_RESET>;
297 reset-names = "reset";
298 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
299 <&clkmgr STRATIX10_SDMMC_CLK>;
300 clock-names = "biu", "ciu";
301 iommus = <&smmu 5>;
302 status = "disabled";
303 };
305 ocram: sram@ffe00000 {
306 compatible = "mmio-sram";
307 reg = <0xffe00000 0x100000>;
308 };
310 pdma: pdma@ffda0000 {
311 compatible = "arm,pl330", "arm,primecell";
312 reg = <0xffda0000 0x1000>;
313 interrupts = <0 81 4>,
314 <0 82 4>,
315 <0 83 4>,
316 <0 84 4>,
317 <0 85 4>,
318 <0 86 4>,
319 <0 87 4>,
320 <0 88 4>,
321 <0 89 4>;
322 #dma-cells = <1>;
323 #dma-channels = <8>;
324 #dma-requests = <32>;
325 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
326 clock-names = "apb_pclk";
327 };
329 rst: rstmgr@ffd11000 {
330 #reset-cells = <1>;
331 compatible = "altr,stratix10-rst-mgr";
332 reg = <0xffd11000 0x1000>;
333 };
335 smmu: iommu@fa000000 {
336 compatible = "arm,mmu-500", "arm,smmu-v2";
337 reg = <0xfa000000 0x40000>;
338 #global-interrupts = <2>;
339 #iommu-cells = <1>;
340 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
341 clock-names = "iommu";
342 interrupt-parent = <&intc>;
343 interrupts = <0 128 4>, /* Global Secure Fault */
344 <0 129 4>, /* Global Non-secure Fault */
345 /* Non-secure Context Interrupts (32) */
346 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
347 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
348 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
349 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
350 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
351 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
352 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
353 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
354 stream-match-mask = <0x7ff0>;
355 status = "disabled";
356 };
358 spi0: spi@ffda4000 {
359 compatible = "snps,dw-apb-ssi";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0xffda4000 0x1000>;
363 interrupts = <0 99 4>;
364 resets = <&rst SPIM0_RESET>;
365 reg-io-width = <4>;
366 num-cs = <4>;
367 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
368 status = "disabled";
369 };
371 spi1: spi@ffda5000 {
372 compatible = "snps,dw-apb-ssi";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 reg = <0xffda5000 0x1000>;
376 interrupts = <0 100 4>;
377 resets = <&rst SPIM1_RESET>;
378 reg-io-width = <4>;
379 num-cs = <4>;
380 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
381 status = "disabled";
382 };
384 sysmgr: sysmgr@ffd12000 {
385 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
386 reg = <0xffd12000 0x228>;
387 };
389 /* Local timer */
390 timer {
391 compatible = "arm,armv8-timer";
392 interrupts = <1 13 0xf08>,
393 <1 14 0xf08>,
394 <1 11 0xf08>,
395 <1 10 0xf08>;
396 };
398 timer0: timer0@ffc03000 {
399 compatible = "snps,dw-apb-timer";
400 interrupts = <0 113 4>;
401 reg = <0xffc03000 0x100>;
402 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
403 clock-names = "timer";
404 };
406 timer1: timer1@ffc03100 {
407 compatible = "snps,dw-apb-timer";
408 interrupts = <0 114 4>;
409 reg = <0xffc03100 0x100>;
410 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
411 clock-names = "timer";
412 };
414 timer2: timer2@ffd00000 {
415 compatible = "snps,dw-apb-timer";
416 interrupts = <0 115 4>;
417 reg = <0xffd00000 0x100>;
418 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
419 clock-names = "timer";
420 };
422 timer3: timer3@ffd00100 {
423 compatible = "snps,dw-apb-timer";
424 interrupts = <0 116 4>;
425 reg = <0xffd00100 0x100>;
426 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
427 clock-names = "timer";
428 };
430 uart0: serial0@ffc02000 {
431 compatible = "snps,dw-apb-uart";
432 reg = <0xffc02000 0x100>;
433 interrupts = <0 108 4>;
434 reg-shift = <2>;
435 reg-io-width = <4>;
436 resets = <&rst UART0_RESET>;
437 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
438 status = "disabled";
439 };
441 uart1: serial1@ffc02100 {
442 compatible = "snps,dw-apb-uart";
443 reg = <0xffc02100 0x100>;
444 interrupts = <0 109 4>;
445 reg-shift = <2>;
446 reg-io-width = <4>;
447 resets = <&rst UART1_RESET>;
448 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
449 status = "disabled";
450 };
452 usbphy0: usbphy@0 {
453 #phy-cells = <0>;
454 compatible = "usb-nop-xceiv";
455 status = "okay";
456 };
458 usb0: usb@ffb00000 {
459 compatible = "snps,dwc2";
460 reg = <0xffb00000 0x40000>;
461 interrupts = <0 93 4>;
462 phys = <&usbphy0>;
463 phy-names = "usb2-phy";
464 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
465 reset-names = "dwc2", "dwc2-ecc";
466 clocks = <&clkmgr STRATIX10_USB_CLK>;
467 iommus = <&smmu 6>;
468 status = "disabled";
469 };
471 usb1: usb@ffb40000 {
472 compatible = "snps,dwc2";
473 reg = <0xffb40000 0x40000>;
474 interrupts = <0 94 4>;
475 phys = <&usbphy0>;
476 phy-names = "usb2-phy";
477 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
478 reset-names = "dwc2", "dwc2-ecc";
479 clocks = <&clkmgr STRATIX10_USB_CLK>;
480 iommus = <&smmu 7>;
481 status = "disabled";
482 };
484 watchdog0: watchdog@ffd00200 {
485 compatible = "snps,dw-wdt";
486 reg = <0xffd00200 0x100>;
487 interrupts = <0 117 4>;
488 resets = <&rst WATCHDOG0_RESET>;
489 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
490 status = "disabled";
491 };
493 watchdog1: watchdog@ffd00300 {
494 compatible = "snps,dw-wdt";
495 reg = <0xffd00300 0x100>;
496 interrupts = <0 118 4>;
497 resets = <&rst WATCHDOG1_RESET>;
498 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
499 status = "disabled";
500 };
502 watchdog2: watchdog@ffd00400 {
503 compatible = "snps,dw-wdt";
504 reg = <0xffd00400 0x100>;
505 interrupts = <0 125 4>;
506 resets = <&rst WATCHDOG2_RESET>;
507 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
508 status = "disabled";
509 };
511 watchdog3: watchdog@ffd00500 {
512 compatible = "snps,dw-wdt";
513 reg = <0xffd00500 0x100>;
514 interrupts = <0 126 4>;
515 resets = <&rst WATCHDOG3_RESET>;
516 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
517 status = "disabled";
518 };
520 sdr: sdr@f8011100 {
521 compatible = "altr,sdr-ctl", "syscon";
522 reg = <0xf8011100 0xc0>;
523 };
525 eccmgr {
526 compatible = "altr,socfpga-s10-ecc-manager",
527 "altr,socfpga-a10-ecc-manager";
528 altr,sysmgr-syscon = <&sysmgr>;
529 #address-cells = <1>;
530 #size-cells = <1>;
531 interrupts = <0 15 4>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 ranges;
536 sdramedac {
537 compatible = "altr,sdram-edac-s10";
538 altr,sdr-syscon = <&sdr>;
539 interrupts = <16 4>;
540 };
542 ocram-ecc@ff8cc000 {
543 compatible = "altr,socfpga-s10-ocram-ecc",
544 "altr,socfpga-a10-ocram-ecc";
545 reg = <0xff8cc000 0x100>;
546 altr,ecc-parent = <&ocram>;
547 interrupts = <1 4>;
548 };
550 usb0-ecc@ff8c4000 {
551 compatible = "altr,socfpga-s10-usb-ecc",
552 "altr,socfpga-usb-ecc";
553 reg = <0xff8c4000 0x100>;
554 altr,ecc-parent = <&usb0>;
555 interrupts = <2 4>;
556 };
558 emac0-rx-ecc@ff8c0000 {
559 compatible = "altr,socfpga-s10-eth-mac-ecc",
560 "altr,socfpga-eth-mac-ecc";
561 reg = <0xff8c0000 0x100>;
562 altr,ecc-parent = <&gmac0>;
563 interrupts = <4 4>;
564 };
566 emac0-tx-ecc@ff8c0400 {
567 compatible = "altr,socfpga-s10-eth-mac-ecc",
568 "altr,socfpga-eth-mac-ecc";
569 reg = <0xff8c0400 0x100>;
570 altr,ecc-parent = <&gmac0>;
571 interrupts = <5 4>;
572 };
574 };
576 qspi: spi@ff8d2000 {
577 compatible = "cdns,qspi-nor";
578 #address-cells = <1>;
579 #size-cells = <0>;
580 reg = <0xff8d2000 0x100>,
581 <0xff900000 0x100000>;
582 interrupts = <0 3 4>;
583 cdns,fifo-depth = <128>;
584 cdns,fifo-width = <4>;
585 cdns,trigger-address = <0x00000000>;
586 clocks = <&qspi_clk>;
588 status = "disabled";
589 };
591 firmware {
592 svc {
593 compatible = "intel,stratix10-svc";
594 method = "smc";
595 memory-region = <&service_reserved>;
597 fpga_mgr: fpga-mgr {
598 compatible = "intel,stratix10-soc-fpga-mgr";
599 };
600 };
601 };
602 };
603 };