arch/arm64/boot/dts/arm/juno-motherboard.dtsi

   1 /*
   2  * ARM Juno Platform motherboard peripherals
   3  *
   4  * Copyright (c) 2013-2014 ARM Ltd
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  *
   8  */
   9
  10 / {
  11         smb@8000000 {
  12                 mb_clk24mhz: clk24mhz {
  13                         compatible = "fixed-clock";
  14                         #clock-cells = <0>;
  15                         clock-frequency = <24000000>;
  16                         clock-output-names = "juno_mb:clk24mhz";
  17                 };
  18
  19                 mb_clk25mhz: clk25mhz {
  20                         compatible = "fixed-clock";
  21                         #clock-cells = <0>;
  22                         clock-frequency = <25000000>;
  23                         clock-output-names = "juno_mb:clk25mhz";
  24                 };
  25
  26                 v2m_refclk1mhz: refclk1mhz {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <1000000>;
  30                         clock-output-names = "juno_mb:refclk1mhz";
  31                 };
  32
  33                 v2m_refclk32khz: refclk32khz {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32768>;
  37                         clock-output-names = "juno_mb:refclk32khz";
  38                 };
  39
  40                 motherboard {
  41                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
  42                         #address-cells = <2>;  /* SMB chipselect number and offset */
  43                         #size-cells = <1>;
  44                         #interrupt-cells = <1>;
  45                         ranges;
  46                         model = "V2M-Juno";
  47                         arm,hbi = <0x252>;
  48                         arm,vexpress,site = <0>;
  49                         arm,v2m-memory-map = "rs1";
  50
  51                         mb_fixed_3v3: mcc-sb-3v3 {
  52                                 compatible = "regulator-fixed";
  53                                 regulator-name = "MCC_SB_3V3";
  54                                 regulator-min-microvolt = <3300000>;
  55                                 regulator-max-microvolt = <3300000>;
  56                                 regulator-always-on;
  57                         };
  58
  59                         gpio-keys {
  60                                 compatible = "gpio-keys";
  61
  62                                 power-button {
  63                                         debounce-interval = <50>;
  64                                         wakeup-source;
  65                                         linux,code = <116>;
  66                                         label = "POWER";
  67                                         gpios = <&iofpga_gpio0 0 0x4>;
  68                                 };
  69                                 home-button {
  70                                         debounce-interval = <50>;
  71                                         wakeup-source;
  72                                         linux,code = <102>;
  73                                         label = "HOME";
  74                                         gpios = <&iofpga_gpio0 1 0x4>;
  75                                 };
  76                                 rlock-button {
  77                                         debounce-interval = <50>;
  78                                         wakeup-source;
  79                                         linux,code = <152>;
  80                                         label = "RLOCK";
  81                                         gpios = <&iofpga_gpio0 2 0x4>;
  82                                 };
  83                                 vol-up-button {
  84                                         debounce-interval = <50>;
  85                                         wakeup-source;
  86                                         linux,code = <115>;
  87                                         label = "VOL+";
  88                                         gpios = <&iofpga_gpio0 3 0x4>;
  89                                 };
  90                                 vol-down-button {
  91                                         debounce-interval = <50>;
  92                                         wakeup-source;
  93                                         linux,code = <114>;
  94                                         label = "VOL-";
  95                                         gpios = <&iofpga_gpio0 4 0x4>;
  96                                 };
  97                                 nmi-button {
  98                                         debounce-interval = <50>;
  99                                         wakeup-source;
 100                                         linux,code = <99>;
 101                                         label = "NMI";
 102                                         gpios = <&iofpga_gpio0 5 0x4>;
 103                                 };
 104                         };
 105
 106                         flash@0,00000000 {
 107                                 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
 108                                 compatible = "arm,vexpress-flash", "cfi-flash";
 109                                 reg = <0 0x00000000 0x04000000>;
 110                                 bank-width = <4>;
 111                                 /*
 112                                  * Unfortunately, accessing the flash disturbs
 113                                  * the CPU idle states (suspend) and CPU
 114                                  * hotplug of the platform. For this reason,
 115                                  * flash hardware access is disabled by default.
 116                                  */
 117                                 status = "disabled";
 118                                 partitions {
 119                                         compatible = "arm,arm-firmware-suite";
 120                                 };
 121                         };
 122
 123                         ethernet@2,00000000 {
 124                                 compatible = "smsc,lan9118", "smsc,lan9115";
 125                                 reg = <2 0x00000000 0x10000>;
 126                                 interrupts = <3>;
 127                                 phy-mode = "mii";
 128                                 reg-io-width = <4>;
 129                                 smsc,irq-active-high;
 130                                 smsc,irq-push-pull;
 131                                 clocks = <&mb_clk25mhz>;
 132                                 vdd33a-supply = <&mb_fixed_3v3>;
 133                                 vddvario-supply = <&mb_fixed_3v3>;
 134                         };
 135
 136                         iofpga@3,00000000 {
 137                                 compatible = "simple-bus";
 138                                 #address-cells = <1>;
 139                                 #size-cells = <1>;
 140                                 ranges = <0 3 0 0x200000>;
 141
 142                                 v2m_sysctl: sysctl@20000 {
 143                                         compatible = "arm,sp810", "arm,primecell";
 144                                         reg = <0x020000 0x1000>;
 145                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
 146                                         clock-names = "refclk", "timclk", "apb_pclk";
 147                                         #clock-cells = <1>;
 148                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 149                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 150                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 151                                 };
 152
 153                                 apbregs@10000 {
 154                                         compatible = "syscon", "simple-mfd";
 155                                         reg = <0x010000 0x1000>;
 156
 157                                         led0 {
 158                                                 compatible = "register-bit-led";
 159                                                 offset = <0x08>;
 160                                                 mask = <0x01>;
 161                                                 label = "vexpress:0";
 162                                                 linux,default-trigger = "heartbeat";
 163                                                 default-state = "on";
 164                                         };
 165                                         led1 {
 166                                                 compatible = "register-bit-led";
 167                                                 offset = <0x08>;
 168                                                 mask = <0x02>;
 169                                                 label = "vexpress:1";
 170                                                 linux,default-trigger = "mmc0";
 171                                                 default-state = "off";
 172                                         };
 173                                         led2 {
 174                                                 compatible = "register-bit-led";
 175                                                 offset = <0x08>;
 176                                                 mask = <0x04>;
 177                                                 label = "vexpress:2";
 178                                                 linux,default-trigger = "cpu0";
 179                                                 default-state = "off";
 180                                         };
 181                                         led3 {
 182                                                 compatible = "register-bit-led";
 183                                                 offset = <0x08>;
 184                                                 mask = <0x08>;
 185                                                 label = "vexpress:3";
 186                                                 linux,default-trigger = "cpu1";
 187                                                 default-state = "off";
 188                                         };
 189                                         led4 {
 190                                                 compatible = "register-bit-led";
 191                                                 offset = <0x08>;
 192                                                 mask = <0x10>;
 193                                                 label = "vexpress:4";
 194                                                 linux,default-trigger = "cpu2";
 195                                                 default-state = "off";
 196                                         };
 197                                         led5 {
 198                                                 compatible = "register-bit-led";
 199                                                 offset = <0x08>;
 200                                                 mask = <0x20>;
 201                                                 label = "vexpress:5";
 202                                                 linux,default-trigger = "cpu3";
 203                                                 default-state = "off";
 204                                         };
 205                                         led6 {
 206                                                 compatible = "register-bit-led";
 207                                                 offset = <0x08>;
 208                                                 mask = <0x40>;
 209                                                 label = "vexpress:6";
 210                                                 default-state = "off";
 211                                         };
 212                                         led7 {
 213                                                 compatible = "register-bit-led";
 214                                                 offset = <0x08>;
 215                                                 mask = <0x80>;
 216                                                 label = "vexpress:7";
 217                                                 default-state = "off";
 218                                         };
 219                                 };
 220
 221                                 mmci@50000 {
 222                                         compatible = "arm,pl180", "arm,primecell";
 223                                         reg = <0x050000 0x1000>;
 224                                         interrupts = <5>;
 225                                         /* cd-gpios = <&v2m_mmc_gpios 0 0>;
 226                                         wp-gpios = <&v2m_mmc_gpios 1 0>; */
 227                                         max-frequency = <12000000>;
 228                                         vmmc-supply = <&mb_fixed_3v3>;
 229                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 230                                         clock-names = "mclk", "apb_pclk";
 231                                 };
 232
 233                                 kmi@60000 {
 234                                         compatible = "arm,pl050", "arm,primecell";
 235                                         reg = <0x060000 0x1000>;
 236                                         interrupts = <8>;
 237                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 238                                         clock-names = "KMIREFCLK", "apb_pclk";
 239                                 };
 240
 241                                 kmi@70000 {
 242                                         compatible = "arm,pl050", "arm,primecell";
 243                                         reg = <0x070000 0x1000>;
 244                                         interrupts = <8>;
 245                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 246                                         clock-names = "KMIREFCLK", "apb_pclk";
 247                                 };
 248
 249                                 wdt@f0000 {
 250                                         compatible = "arm,sp805", "arm,primecell";
 251                                         reg = <0x0f0000 0x10000>;
 252                                         interrupts = <7>;
 253                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 254                                         clock-names = "wdogclk", "apb_pclk";
 255                                 };
 256
 257                                 v2m_timer01: timer@110000 {
 258                                         compatible = "arm,sp804", "arm,primecell";
 259                                         reg = <0x110000 0x10000>;
 260                                         interrupts = <9>;
 261                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
 262                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 263                                 };
 264
 265                                 v2m_timer23: timer@120000 {
 266                                         compatible = "arm,sp804", "arm,primecell";
 267                                         reg = <0x120000 0x10000>;
 268                                         interrupts = <9>;
 269                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
 270                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 271                                 };
 272
 273                                 rtc@170000 {
 274                                         compatible = "arm,pl031", "arm,primecell";
 275                                         reg = <0x170000 0x10000>;
 276                                         interrupts = <0>;
 277                                         clocks = <&soc_smc50mhz>;
 278                                         clock-names = "apb_pclk";
 279                                 };
 280
 281                                 iofpga_gpio0: gpio@1d0000 {
 282                                         compatible = "arm,pl061", "arm,primecell";
 283                                         reg = <0x1d0000 0x1000>;
 284                                         interrupts = <6>;
 285                                         clocks = <&soc_smc50mhz>;
 286                                         clock-names = "apb_pclk";
 287                                         gpio-controller;
 288                                         #gpio-cells = <2>;
 289                                         interrupt-controller;
 290                                         #interrupt-cells = <2>;
 291                                 };
 292                         };
 293                 };
 294         };
 295 };