| blob | a76f620f7f35505855c438a80097b6d89df92888 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5433 SoC device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 *
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
9 * values for board specific bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
13 * additional nodes can be added to this file.
14 */
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 / {
20 compatible = "samsung,exynos5433";
21 #address-cells = <1>;
22 #size-cells = <1>;
24 interrupt-parent = <&gic>;
26 arm_a53_pmu {
27 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
28 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
33 };
35 arm_a57_pmu {
36 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
37 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
42 };
44 xxti: clock {
45 /* XXTI */
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
48 #clock-cells = <0>;
49 };
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
55 cpu0: cpu@100 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 reg = <0x100>;
60 clock-frequency = <1300000000>;
61 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
62 clock-names = "apolloclk";
63 operating-points-v2 = <&cluster_a53_opp_table>;
64 #cooling-cells = <2>;
65 };
67 cpu1: cpu@101 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 reg = <0x101>;
72 clock-frequency = <1300000000>;
73 operating-points-v2 = <&cluster_a53_opp_table>;
74 #cooling-cells = <2>;
75 };
77 cpu2: cpu@102 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a53";
80 enable-method = "psci";
81 reg = <0x102>;
82 clock-frequency = <1300000000>;
83 operating-points-v2 = <&cluster_a53_opp_table>;
84 #cooling-cells = <2>;
85 };
87 cpu3: cpu@103 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 reg = <0x103>;
92 clock-frequency = <1300000000>;
93 operating-points-v2 = <&cluster_a53_opp_table>;
94 #cooling-cells = <2>;
95 };
97 cpu4: cpu@0 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a57";
100 enable-method = "psci";
101 reg = <0x0>;
102 clock-frequency = <1900000000>;
103 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
104 clock-names = "atlasclk";
105 operating-points-v2 = <&cluster_a57_opp_table>;
106 #cooling-cells = <2>;
107 };
109 cpu5: cpu@1 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 reg = <0x1>;
114 clock-frequency = <1900000000>;
115 operating-points-v2 = <&cluster_a57_opp_table>;
116 #cooling-cells = <2>;
117 };
119 cpu6: cpu@2 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a57";
122 enable-method = "psci";
123 reg = <0x2>;
124 clock-frequency = <1900000000>;
125 operating-points-v2 = <&cluster_a57_opp_table>;
126 #cooling-cells = <2>;
127 };
129 cpu7: cpu@3 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a57";
132 enable-method = "psci";
133 reg = <0x3>;
134 clock-frequency = <1900000000>;
135 operating-points-v2 = <&cluster_a57_opp_table>;
136 #cooling-cells = <2>;
137 };
138 };
140 cluster_a53_opp_table: opp_table0 {
141 compatible = "operating-points-v2";
142 opp-shared;
144 opp-400000000 {
145 opp-hz = /bits/ 64 <400000000>;
146 opp-microvolt = <900000>;
147 };
148 opp-500000000 {
149 opp-hz = /bits/ 64 <500000000>;
150 opp-microvolt = <925000>;
151 };
152 opp-600000000 {
153 opp-hz = /bits/ 64 <600000000>;
154 opp-microvolt = <950000>;
155 };
156 opp-700000000 {
157 opp-hz = /bits/ 64 <700000000>;
158 opp-microvolt = <975000>;
159 };
160 opp-800000000 {
161 opp-hz = /bits/ 64 <800000000>;
162 opp-microvolt = <1000000>;
163 };
164 opp-900000000 {
165 opp-hz = /bits/ 64 <900000000>;
166 opp-microvolt = <1050000>;
167 };
168 opp-1000000000 {
169 opp-hz = /bits/ 64 <1000000000>;
170 opp-microvolt = <1075000>;
171 };
172 opp-1100000000 {
173 opp-hz = /bits/ 64 <1100000000>;
174 opp-microvolt = <1112500>;
175 };
176 opp-1200000000 {
177 opp-hz = /bits/ 64 <1200000000>;
178 opp-microvolt = <1112500>;
179 };
180 opp-1300000000 {
181 opp-hz = /bits/ 64 <1300000000>;
182 opp-microvolt = <1150000>;
183 };
184 };
186 cluster_a57_opp_table: opp_table1 {
187 compatible = "operating-points-v2";
188 opp-shared;
190 opp-500000000 {
191 opp-hz = /bits/ 64 <500000000>;
192 opp-microvolt = <900000>;
193 };
194 opp-600000000 {
195 opp-hz = /bits/ 64 <600000000>;
196 opp-microvolt = <900000>;
197 };
198 opp-700000000 {
199 opp-hz = /bits/ 64 <700000000>;
200 opp-microvolt = <912500>;
201 };
202 opp-800000000 {
203 opp-hz = /bits/ 64 <800000000>;
204 opp-microvolt = <912500>;
205 };
206 opp-900000000 {
207 opp-hz = /bits/ 64 <900000000>;
208 opp-microvolt = <937500>;
209 };
210 opp-1000000000 {
211 opp-hz = /bits/ 64 <1000000000>;
212 opp-microvolt = <975000>;
213 };
214 opp-1100000000 {
215 opp-hz = /bits/ 64 <1100000000>;
216 opp-microvolt = <1012500>;
217 };
218 opp-1200000000 {
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <1037500>;
221 };
222 opp-1300000000 {
223 opp-hz = /bits/ 64 <1300000000>;
224 opp-microvolt = <1062500>;
225 };
226 opp-1400000000 {
227 opp-hz = /bits/ 64 <1400000000>;
228 opp-microvolt = <1087500>;
229 };
230 opp-1500000000 {
231 opp-hz = /bits/ 64 <1500000000>;
232 opp-microvolt = <1125000>;
233 };
234 opp-1600000000 {
235 opp-hz = /bits/ 64 <1600000000>;
236 opp-microvolt = <1137500>;
237 };
238 opp-1700000000 {
239 opp-hz = /bits/ 64 <1700000000>;
240 opp-microvolt = <1175000>;
241 };
242 opp-1800000000 {
243 opp-hz = /bits/ 64 <1800000000>;
244 opp-microvolt = <1212500>;
245 };
246 opp-1900000000 {
247 opp-hz = /bits/ 64 <1900000000>;
248 opp-microvolt = <1262500>;
249 };
250 };
252 gpu: gpu@14ac0000 {
253 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
254 reg = <0x14ac0000 0x5000>;
255 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
258 interrupt-names = "job", "mmu", "gpu";
259 clocks = <&cmu_g3d CLK_ACLK_G3D>;
260 clock-names = "core";
261 power-domains = <&pd_g3d>;
262 operating-points-v2 = <&gpu_opp_table>;
263 status = "disabled";
265 gpu_opp_table: opp_table {
266 compatible = "operating-points-v2";
268 opp-160000000 {
269 opp-hz = /bits/ 64 <160000000>;
270 opp-microvolt = <1000000>;
271 };
272 opp-267000000 {
273 opp-hz = /bits/ 64 <267000000>;
274 opp-microvolt = <1000000>;
275 };
276 opp-350000000 {
277 opp-hz = /bits/ 64 <350000000>;
278 opp-microvolt = <1025000>;
279 };
280 opp-420000000 {
281 opp-hz = /bits/ 64 <420000000>;
282 opp-microvolt = <1025000>;
283 };
284 opp-500000000 {
285 opp-hz = /bits/ 64 <500000000>;
286 opp-microvolt = <1075000>;
287 };
288 opp-550000000 {
289 opp-hz = /bits/ 64 <550000000>;
290 opp-microvolt = <1125000>;
291 };
292 opp-600000000 {
293 opp-hz = /bits/ 64 <600000000>;
294 opp-microvolt = <1150000>;
295 };
296 opp-700000000 {
297 opp-hz = /bits/ 64 <700000000>;
298 opp-microvolt = <1150000>;
299 };
300 };
301 };
303 psci {
304 compatible = "arm,psci";
305 method = "smc";
306 cpu_off = <0x84000002>;
307 cpu_on = <0xC4000003>;
308 };
310 soc: soc {
311 compatible = "simple-bus";
312 #address-cells = <1>;
313 #size-cells = <1>;
314 ranges;
316 chipid@10000000 {
317 compatible = "samsung,exynos4210-chipid";
318 reg = <0x10000000 0x100>;
319 };
321 cmu_top: clock-controller@10030000 {
322 compatible = "samsung,exynos5433-cmu-top";
323 reg = <0x10030000 0x1000>;
324 #clock-cells = <1>;
326 clock-names = "oscclk",
327 "sclk_mphy_pll",
328 "sclk_mfc_pll",
329 "sclk_bus_pll";
330 clocks = <&xxti>,
331 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
332 <&cmu_mif CLK_SCLK_MFC_PLL>,
333 <&cmu_mif CLK_SCLK_BUS_PLL>;
334 };
336 cmu_cpif: clock-controller@10fc0000 {
337 compatible = "samsung,exynos5433-cmu-cpif";
338 reg = <0x10fc0000 0x1000>;
339 #clock-cells = <1>;
341 clock-names = "oscclk";
342 clocks = <&xxti>;
343 };
345 cmu_mif: clock-controller@105b0000 {
346 compatible = "samsung,exynos5433-cmu-mif";
347 reg = <0x105b0000 0x2000>;
348 #clock-cells = <1>;
350 clock-names = "oscclk",
351 "sclk_mphy_pll";
352 clocks = <&xxti>,
353 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
354 };
356 cmu_peric: clock-controller@14c80000 {
357 compatible = "samsung,exynos5433-cmu-peric";
358 reg = <0x14c80000 0x1000>;
359 #clock-cells = <1>;
360 };
362 cmu_peris: clock-controller@10040000 {
363 compatible = "samsung,exynos5433-cmu-peris";
364 reg = <0x10040000 0x1000>;
365 #clock-cells = <1>;
366 };
368 cmu_fsys: clock-controller@156e0000 {
369 compatible = "samsung,exynos5433-cmu-fsys";
370 reg = <0x156e0000 0x1000>;
371 #clock-cells = <1>;
373 clock-names = "oscclk",
374 "sclk_ufs_mphy",
375 "aclk_fsys_200",
376 "sclk_pcie_100_fsys",
377 "sclk_ufsunipro_fsys",
378 "sclk_mmc2_fsys",
379 "sclk_mmc1_fsys",
380 "sclk_mmc0_fsys",
381 "sclk_usbhost30_fsys",
382 "sclk_usbdrd30_fsys";
383 clocks = <&xxti>,
384 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
385 <&cmu_top CLK_ACLK_FSYS_200>,
386 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
387 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
388 <&cmu_top CLK_SCLK_MMC2_FSYS>,
389 <&cmu_top CLK_SCLK_MMC1_FSYS>,
390 <&cmu_top CLK_SCLK_MMC0_FSYS>,
391 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
392 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
393 };
395 cmu_g2d: clock-controller@12460000 {
396 compatible = "samsung,exynos5433-cmu-g2d";
397 reg = <0x12460000 0x1000>;
398 #clock-cells = <1>;
400 clock-names = "oscclk",
401 "aclk_g2d_266",
402 "aclk_g2d_400";
403 clocks = <&xxti>,
404 <&cmu_top CLK_ACLK_G2D_266>,
405 <&cmu_top CLK_ACLK_G2D_400>;
406 power-domains = <&pd_g2d>;
407 };
409 cmu_disp: clock-controller@13b90000 {
410 compatible = "samsung,exynos5433-cmu-disp";
411 reg = <0x13b90000 0x1000>;
412 #clock-cells = <1>;
414 clock-names = "oscclk",
415 "sclk_dsim1_disp",
416 "sclk_dsim0_disp",
417 "sclk_dsd_disp",
418 "sclk_decon_tv_eclk_disp",
419 "sclk_decon_vclk_disp",
420 "sclk_decon_eclk_disp",
421 "sclk_decon_tv_vclk_disp",
422 "aclk_disp_333";
423 clocks = <&xxti>,
424 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
425 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
426 <&cmu_mif CLK_SCLK_DSD_DISP>,
427 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
428 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
429 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
430 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
431 <&cmu_mif CLK_ACLK_DISP_333>;
432 power-domains = <&pd_disp>;
433 };
435 cmu_aud: clock-controller@114c0000 {
436 compatible = "samsung,exynos5433-cmu-aud";
437 reg = <0x114c0000 0x1000>;
438 #clock-cells = <1>;
439 clock-names = "oscclk", "fout_aud_pll";
440 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
441 power-domains = <&pd_aud>;
442 };
444 cmu_bus0: clock-controller@13600000 {
445 compatible = "samsung,exynos5433-cmu-bus0";
446 reg = <0x13600000 0x1000>;
447 #clock-cells = <1>;
449 clock-names = "aclk_bus0_400";
450 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
451 };
453 cmu_bus1: clock-controller@14800000 {
454 compatible = "samsung,exynos5433-cmu-bus1";
455 reg = <0x14800000 0x1000>;
456 #clock-cells = <1>;
458 clock-names = "aclk_bus1_400";
459 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
460 };
462 cmu_bus2: clock-controller@13400000 {
463 compatible = "samsung,exynos5433-cmu-bus2";
464 reg = <0x13400000 0x1000>;
465 #clock-cells = <1>;
467 clock-names = "oscclk", "aclk_bus2_400";
468 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
469 };
471 cmu_g3d: clock-controller@14aa0000 {
472 compatible = "samsung,exynos5433-cmu-g3d";
473 reg = <0x14aa0000 0x2000>;
474 #clock-cells = <1>;
476 clock-names = "oscclk", "aclk_g3d_400";
477 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
478 power-domains = <&pd_g3d>;
479 };
481 cmu_gscl: clock-controller@13cf0000 {
482 compatible = "samsung,exynos5433-cmu-gscl";
483 reg = <0x13cf0000 0x1000>;
484 #clock-cells = <1>;
486 clock-names = "oscclk",
487 "aclk_gscl_111",
488 "aclk_gscl_333";
489 clocks = <&xxti>,
490 <&cmu_top CLK_ACLK_GSCL_111>,
491 <&cmu_top CLK_ACLK_GSCL_333>;
492 power-domains = <&pd_gscl>;
493 };
495 cmu_apollo: clock-controller@11900000 {
496 compatible = "samsung,exynos5433-cmu-apollo";
497 reg = <0x11900000 0x2000>;
498 #clock-cells = <1>;
500 clock-names = "oscclk", "sclk_bus_pll_apollo";
501 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
502 };
504 cmu_atlas: clock-controller@11800000 {
505 compatible = "samsung,exynos5433-cmu-atlas";
506 reg = <0x11800000 0x2000>;
507 #clock-cells = <1>;
509 clock-names = "oscclk", "sclk_bus_pll_atlas";
510 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
511 };
513 cmu_mscl: clock-controller@150d0000 {
514 compatible = "samsung,exynos5433-cmu-mscl";
515 reg = <0x150d0000 0x1000>;
516 #clock-cells = <1>;
518 clock-names = "oscclk",
519 "sclk_jpeg_mscl",
520 "aclk_mscl_400";
521 clocks = <&xxti>,
522 <&cmu_top CLK_SCLK_JPEG_MSCL>,
523 <&cmu_top CLK_ACLK_MSCL_400>;
524 power-domains = <&pd_mscl>;
525 };
527 cmu_mfc: clock-controller@15280000 {
528 compatible = "samsung,exynos5433-cmu-mfc";
529 reg = <0x15280000 0x1000>;
530 #clock-cells = <1>;
532 clock-names = "oscclk", "aclk_mfc_400";
533 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
534 power-domains = <&pd_mfc>;
535 };
537 cmu_hevc: clock-controller@14f80000 {
538 compatible = "samsung,exynos5433-cmu-hevc";
539 reg = <0x14f80000 0x1000>;
540 #clock-cells = <1>;
542 clock-names = "oscclk", "aclk_hevc_400";
543 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
544 power-domains = <&pd_hevc>;
545 };
547 cmu_isp: clock-controller@146d0000 {
548 compatible = "samsung,exynos5433-cmu-isp";
549 reg = <0x146d0000 0x1000>;
550 #clock-cells = <1>;
552 clock-names = "oscclk",
553 "aclk_isp_dis_400",
554 "aclk_isp_400";
555 clocks = <&xxti>,
556 <&cmu_top CLK_ACLK_ISP_DIS_400>,
557 <&cmu_top CLK_ACLK_ISP_400>;
558 power-domains = <&pd_isp>;
559 };
561 cmu_cam0: clock-controller@120d0000 {
562 compatible = "samsung,exynos5433-cmu-cam0";
563 reg = <0x120d0000 0x1000>;
564 #clock-cells = <1>;
566 clock-names = "oscclk",
567 "aclk_cam0_333",
568 "aclk_cam0_400",
569 "aclk_cam0_552";
570 clocks = <&xxti>,
571 <&cmu_top CLK_ACLK_CAM0_333>,
572 <&cmu_top CLK_ACLK_CAM0_400>,
573 <&cmu_top CLK_ACLK_CAM0_552>;
574 power-domains = <&pd_cam0>;
575 };
577 cmu_cam1: clock-controller@145d0000 {
578 compatible = "samsung,exynos5433-cmu-cam1";
579 reg = <0x145d0000 0x1000>;
580 #clock-cells = <1>;
582 clock-names = "oscclk",
583 "sclk_isp_uart_cam1",
584 "sclk_isp_spi1_cam1",
585 "sclk_isp_spi0_cam1",
586 "aclk_cam1_333",
587 "aclk_cam1_400",
588 "aclk_cam1_552";
589 clocks = <&xxti>,
590 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
591 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
592 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
593 <&cmu_top CLK_ACLK_CAM1_333>,
594 <&cmu_top CLK_ACLK_CAM1_400>,
595 <&cmu_top CLK_ACLK_CAM1_552>;
596 power-domains = <&pd_cam1>;
597 };
599 cmu_imem: clock-controller@11060000 {
600 compatible = "samsung,exynos5433-cmu-imem";
601 reg = <0x11060000 0x1000>;
602 #clock-cells = <1>;
604 clock-names = "oscclk",
605 "aclk_imem_sssx_266",
606 "aclk_imem_266",
607 "aclk_imem_200";
608 clocks = <&xxti>,
609 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
610 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
611 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
612 };
614 slim_sss: slim-sss@11140000 {
615 compatible = "samsung,exynos5433-slim-sss";
616 reg = <0x11140000 0x1000>;
617 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
618 clock-names = "aclk", "pclk";
619 clocks = <&cmu_imem CLK_ACLK_SLIMSSS>,
620 <&cmu_imem CLK_PCLK_SLIMSSS>;
621 };
623 pd_gscl: power-domain@105c4000 {
624 compatible = "samsung,exynos5433-pd";
625 reg = <0x105c4000 0x20>;
626 #power-domain-cells = <0>;
627 label = "GSCL";
628 };
630 pd_cam0: power-domain@105c4020 {
631 compatible = "samsung,exynos5433-pd";
632 reg = <0x105c4020 0x20>;
633 #power-domain-cells = <0>;
634 power-domains = <&pd_cam1>;
635 label = "CAM0";
636 };
638 pd_mscl: power-domain@105c4040 {
639 compatible = "samsung,exynos5433-pd";
640 reg = <0x105c4040 0x20>;
641 #power-domain-cells = <0>;
642 label = "MSCL";
643 };
645 pd_g3d: power-domain@105c4060 {
646 compatible = "samsung,exynos5433-pd";
647 reg = <0x105c4060 0x20>;
648 #power-domain-cells = <0>;
649 label = "G3D";
650 };
652 pd_disp: power-domain@105c4080 {
653 compatible = "samsung,exynos5433-pd";
654 reg = <0x105c4080 0x20>;
655 #power-domain-cells = <0>;
656 label = "DISP";
657 };
659 pd_cam1: power-domain@105c40a0 {
660 compatible = "samsung,exynos5433-pd";
661 reg = <0x105c40a0 0x20>;
662 #power-domain-cells = <0>;
663 label = "CAM1";
664 };
666 pd_aud: power-domain@105c40c0 {
667 compatible = "samsung,exynos5433-pd";
668 reg = <0x105c40c0 0x20>;
669 #power-domain-cells = <0>;
670 label = "AUD";
671 };
673 pd_g2d: power-domain@105c4120 {
674 compatible = "samsung,exynos5433-pd";
675 reg = <0x105c4120 0x20>;
676 #power-domain-cells = <0>;
677 label = "G2D";
678 };
680 pd_isp: power-domain@105c4140 {
681 compatible = "samsung,exynos5433-pd";
682 reg = <0x105c4140 0x20>;
683 #power-domain-cells = <0>;
684 power-domains = <&pd_cam0>;
685 label = "ISP";
686 };
688 pd_mfc: power-domain@105c4180 {
689 compatible = "samsung,exynos5433-pd";
690 reg = <0x105c4180 0x20>;
691 #power-domain-cells = <0>;
692 label = "MFC";
693 };
695 pd_hevc: power-domain@105c41c0 {
696 compatible = "samsung,exynos5433-pd";
697 reg = <0x105c41c0 0x20>;
698 #power-domain-cells = <0>;
699 label = "HEVC";
700 };
702 tmu_atlas0: tmu@10060000 {
703 compatible = "samsung,exynos5433-tmu";
704 reg = <0x10060000 0x200>;
705 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
707 <&cmu_peris CLK_SCLK_TMU0>;
708 clock-names = "tmu_apbif", "tmu_sclk";
709 #thermal-sensor-cells = <0>;
710 status = "disabled";
711 };
713 tmu_atlas1: tmu@10068000 {
714 compatible = "samsung,exynos5433-tmu";
715 reg = <0x10068000 0x200>;
716 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
718 <&cmu_peris CLK_SCLK_TMU0>;
719 clock-names = "tmu_apbif", "tmu_sclk";
720 #thermal-sensor-cells = <0>;
721 status = "disabled";
722 };
724 tmu_g3d: tmu@10070000 {
725 compatible = "samsung,exynos5433-tmu";
726 reg = <0x10070000 0x200>;
727 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
729 <&cmu_peris CLK_SCLK_TMU1>;
730 clock-names = "tmu_apbif", "tmu_sclk";
731 #thermal-sensor-cells = <0>;
732 status = "disabled";
733 };
735 tmu_apollo: tmu@10078000 {
736 compatible = "samsung,exynos5433-tmu";
737 reg = <0x10078000 0x200>;
738 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
740 <&cmu_peris CLK_SCLK_TMU1>;
741 clock-names = "tmu_apbif", "tmu_sclk";
742 #thermal-sensor-cells = <0>;
743 status = "disabled";
744 };
746 tmu_isp: tmu@1007c000 {
747 compatible = "samsung,exynos5433-tmu";
748 reg = <0x1007c000 0x200>;
749 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
751 <&cmu_peris CLK_SCLK_TMU1>;
752 clock-names = "tmu_apbif", "tmu_sclk";
753 #thermal-sensor-cells = <0>;
754 status = "disabled";
755 };
757 mct@101c0000 {
758 compatible = "samsung,exynos4210-mct";
759 reg = <0x101c0000 0x800>;
760 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
773 clock-names = "fin_pll", "mct";
774 };
776 ppmu_d0_cpu: ppmu@10480000 {
777 compatible = "samsung,exynos-ppmu-v2";
778 reg = <0x10480000 0x2000>;
779 status = "disabled";
780 };
782 ppmu_d0_general: ppmu@10490000 {
783 compatible = "samsung,exynos-ppmu-v2";
784 reg = <0x10490000 0x2000>;
785 status = "disabled";
786 };
788 ppmu_d1_cpu: ppmu@104b0000 {
789 compatible = "samsung,exynos-ppmu-v2";
790 reg = <0x104b0000 0x2000>;
791 status = "disabled";
792 };
794 ppmu_d1_general: ppmu@104c0000 {
795 compatible = "samsung,exynos-ppmu-v2";
796 reg = <0x104c0000 0x2000>;
797 status = "disabled";
798 };
800 pinctrl_alive: pinctrl@10580000 {
801 compatible = "samsung,exynos5433-pinctrl";
802 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
804 wakeup-interrupt-controller {
805 compatible = "samsung,exynos7-wakeup-eint";
806 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
807 };
808 };
810 pinctrl_aud: pinctrl@114b0000 {
811 compatible = "samsung,exynos5433-pinctrl";
812 reg = <0x114b0000 0x1000>;
813 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
814 power-domains = <&pd_aud>;
815 };
817 pinctrl_cpif: pinctrl@10fe0000 {
818 compatible = "samsung,exynos5433-pinctrl";
819 reg = <0x10fe0000 0x1000>;
820 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
821 };
823 pinctrl_ese: pinctrl@14ca0000 {
824 compatible = "samsung,exynos5433-pinctrl";
825 reg = <0x14ca0000 0x1000>;
826 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
827 };
829 pinctrl_finger: pinctrl@14cb0000 {
830 compatible = "samsung,exynos5433-pinctrl";
831 reg = <0x14cb0000 0x1000>;
832 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
833 };
835 pinctrl_fsys: pinctrl@15690000 {
836 compatible = "samsung,exynos5433-pinctrl";
837 reg = <0x15690000 0x1000>;
838 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
839 };
841 pinctrl_imem: pinctrl@11090000 {
842 compatible = "samsung,exynos5433-pinctrl";
843 reg = <0x11090000 0x1000>;
844 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
845 };
847 pinctrl_nfc: pinctrl@14cd0000 {
848 compatible = "samsung,exynos5433-pinctrl";
849 reg = <0x14cd0000 0x1000>;
850 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
851 };
853 pinctrl_peric: pinctrl@14cc0000 {
854 compatible = "samsung,exynos5433-pinctrl";
855 reg = <0x14cc0000 0x1100>;
856 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
857 };
859 pinctrl_touch: pinctrl@14ce0000 {
860 compatible = "samsung,exynos5433-pinctrl";
861 reg = <0x14ce0000 0x1100>;
862 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
863 };
865 pmu_system_controller: system-controller@105c0000 {
866 compatible = "samsung,exynos5433-pmu", "syscon";
867 reg = <0x105c0000 0x5008>;
868 #clock-cells = <1>;
869 clock-names = "clkout16";
870 clocks = <&xxti>;
872 reboot: syscon-reboot {
873 compatible = "syscon-reboot";
874 regmap = <&pmu_system_controller>;
875 offset = <0x400>; /* SWRESET */
876 mask = <0x1>;
877 };
878 };
880 gic: interrupt-controller@11001000 {
881 compatible = "arm,gic-400";
882 #interrupt-cells = <3>;
883 interrupt-controller;
884 reg = <0x11001000 0x1000>,
885 <0x11002000 0x2000>,
886 <0x11004000 0x2000>,
887 <0x11006000 0x2000>;
888 interrupts = <GIC_PPI 9 0xf04>;
889 };
891 mipi_phy: video-phy {
892 compatible = "samsung,exynos5433-mipi-video-phy";
893 #phy-cells = <1>;
894 samsung,pmu-syscon = <&pmu_system_controller>;
895 samsung,cam0-sysreg = <&syscon_cam0>;
896 samsung,cam1-sysreg = <&syscon_cam1>;
897 samsung,disp-sysreg = <&syscon_disp>;
898 };
900 decon: decon@13800000 {
901 compatible = "samsung,exynos5433-decon";
902 reg = <0x13800000 0x2104>;
903 clocks = <&cmu_disp CLK_PCLK_DECON>,
904 <&cmu_disp CLK_ACLK_DECON>,
905 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
906 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
907 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
908 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
909 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
910 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
911 <&cmu_disp CLK_SCLK_DECON_VCLK>,
912 <&cmu_disp CLK_SCLK_DECON_ECLK>,
913 <&cmu_disp CLK_SCLK_DSD>;
914 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
915 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
916 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
917 "pclk_smmu_decon1x", "sclk_decon_vclk",
918 "sclk_decon_eclk", "dsd";
919 power-domains = <&pd_disp>;
920 interrupt-names = "fifo", "vsync", "lcd_sys";
921 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
924 samsung,disp-sysreg = <&syscon_disp>;
925 status = "disabled";
926 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
927 iommu-names = "m0", "m1";
929 ports {
930 #address-cells = <1>;
931 #size-cells = <0>;
933 port@0 {
934 reg = <0>;
935 decon_to_mic: endpoint {
936 remote-endpoint =
937 <&mic_to_decon>;
938 };
939 };
940 };
941 };
943 decon_tv: decon@13880000 {
944 compatible = "samsung,exynos5433-decon-tv";
945 reg = <0x13880000 0x20b8>;
946 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
947 <&cmu_disp CLK_ACLK_DECON_TV>,
948 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
949 <&cmu_disp CLK_ACLK_XIU_TV0X>,
950 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
951 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
952 <&cmu_disp CLK_ACLK_XIU_TV1X>,
953 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
954 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
955 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
956 <&cmu_disp CLK_SCLK_DSD>;
957 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
958 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
959 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
960 "pclk_smmu_decon1x", "sclk_decon_vclk",
961 "sclk_decon_eclk", "dsd";
962 samsung,disp-sysreg = <&syscon_disp>;
963 power-domains = <&pd_disp>;
964 interrupt-names = "fifo", "vsync", "lcd_sys";
965 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
968 status = "disabled";
969 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
970 iommu-names = "m0", "m1";
971 };
973 dsi: dsi@13900000 {
974 compatible = "samsung,exynos5433-mipi-dsi";
975 reg = <0x13900000 0xC0>;
976 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
977 phys = <&mipi_phy 1>;
978 phy-names = "dsim";
979 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
980 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
981 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
982 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
983 <&cmu_disp CLK_SCLK_DSIM0>;
984 clock-names = "bus_clk",
985 "phyclk_mipidphy0_bitclkdiv8",
986 "phyclk_mipidphy0_rxclkesc0",
987 "sclk_rgb_vclk_to_dsim0",
988 "sclk_mipi";
989 power-domains = <&pd_disp>;
990 status = "disabled";
991 #address-cells = <1>;
992 #size-cells = <0>;
994 ports {
995 #address-cells = <1>;
996 #size-cells = <0>;
998 port@0 {
999 reg = <0>;
1000 dsi_to_mic: endpoint {
1001 remote-endpoint = <&mic_to_dsi>;
1002 };
1003 };
1004 };
1005 };
1007 mic: mic@13930000 {
1008 compatible = "samsung,exynos5433-mic";
1009 reg = <0x13930000 0x48>;
1010 clocks = <&cmu_disp CLK_PCLK_MIC0>,
1011 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1012 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1013 power-domains = <&pd_disp>;
1014 samsung,disp-syscon = <&syscon_disp>;
1015 status = "disabled";
1017 ports {
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1021 port@0 {
1022 reg = <0>;
1023 mic_to_decon: endpoint {
1024 remote-endpoint =
1025 <&decon_to_mic>;
1026 };
1027 };
1029 port@1 {
1030 reg = <1>;
1031 mic_to_dsi: endpoint {
1032 remote-endpoint = <&dsi_to_mic>;
1033 };
1034 };
1035 };
1036 };
1038 hdmi: hdmi@13970000 {
1039 compatible = "samsung,exynos5433-hdmi";
1040 reg = <0x13970000 0x70000>;
1041 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&cmu_disp CLK_PCLK_HDMI>,
1043 <&cmu_disp CLK_PCLK_HDMIPHY>,
1044 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1045 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1046 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1047 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1048 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1049 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1050 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1051 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1052 "i_tmds_clk", "i_pixel_clk",
1053 "tmds_clko", "tmds_clko_user",
1054 "pixel_clko", "pixel_clko_user",
1055 "oscclk", "i_spdif_clk";
1056 phy = <&hdmiphy>;
1057 ddc = <&hsi2c_11>;
1058 samsung,syscon-phandle = <&pmu_system_controller>;
1059 samsung,sysreg-phandle = <&syscon_disp>;
1060 #sound-dai-cells = <0>;
1061 status = "disabled";
1062 };
1064 hdmiphy: hdmiphy@13af0000 {
1065 reg = <0x13af0000 0x80>;
1066 };
1068 syscon_disp: syscon@13b80000 {
1069 compatible = "syscon";
1070 reg = <0x13b80000 0x1010>;
1071 };
1073 syscon_cam0: syscon@120f0000 {
1074 compatible = "syscon";
1075 reg = <0x120f0000 0x1020>;
1076 };
1078 syscon_cam1: syscon@145f0000 {
1079 compatible = "syscon";
1080 reg = <0x145f0000 0x1038>;
1081 };
1083 gsc_0: video-scaler@13c00000 {
1084 compatible = "samsung,exynos5433-gsc";
1085 reg = <0x13c00000 0x1000>;
1086 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1087 clock-names = "pclk", "aclk", "aclk_xiu",
1088 "aclk_gsclbend", "gsd";
1089 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1090 <&cmu_gscl CLK_ACLK_GSCL0>,
1091 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1092 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1093 <&cmu_gscl CLK_ACLK_GSD>;
1094 iommus = <&sysmmu_gscl0>;
1095 power-domains = <&pd_gscl>;
1096 };
1098 gsc_1: video-scaler@13c10000 {
1099 compatible = "samsung,exynos5433-gsc";
1100 reg = <0x13c10000 0x1000>;
1101 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1102 clock-names = "pclk", "aclk", "aclk_xiu",
1103 "aclk_gsclbend", "gsd";
1104 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1105 <&cmu_gscl CLK_ACLK_GSCL1>,
1106 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1107 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1108 <&cmu_gscl CLK_ACLK_GSD>;
1109 iommus = <&sysmmu_gscl1>;
1110 power-domains = <&pd_gscl>;
1111 };
1113 gsc_2: video-scaler@13c20000 {
1114 compatible = "samsung,exynos5433-gsc";
1115 reg = <0x13c20000 0x1000>;
1116 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1117 clock-names = "pclk", "aclk", "aclk_xiu",
1118 "aclk_gsclbend", "gsd";
1119 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1120 <&cmu_gscl CLK_ACLK_GSCL2>,
1121 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1122 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1123 <&cmu_gscl CLK_ACLK_GSD>;
1124 iommus = <&sysmmu_gscl2>;
1125 power-domains = <&pd_gscl>;
1126 };
1128 scaler_0: scaler@15000000 {
1129 compatible = "samsung,exynos5433-scaler";
1130 reg = <0x15000000 0x1294>;
1131 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1132 clock-names = "pclk", "aclk", "aclk_xiu";
1133 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1134 <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1135 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1136 iommus = <&sysmmu_scaler_0>;
1137 power-domains = <&pd_mscl>;
1138 };
1140 scaler_1: scaler@15010000 {
1141 compatible = "samsung,exynos5433-scaler";
1142 reg = <0x15010000 0x1294>;
1143 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1144 clock-names = "pclk", "aclk", "aclk_xiu";
1145 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1146 <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1147 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1148 iommus = <&sysmmu_scaler_1>;
1149 power-domains = <&pd_mscl>;
1150 };
1152 jpeg: codec@15020000 {
1153 compatible = "samsung,exynos5433-jpeg";
1154 reg = <0x15020000 0x10000>;
1155 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1156 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1157 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1158 <&cmu_mscl CLK_ACLK_JPEG>,
1159 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1160 <&cmu_mscl CLK_SCLK_JPEG>;
1161 iommus = <&sysmmu_jpeg>;
1162 power-domains = <&pd_mscl>;
1163 };
1165 mfc: codec@152e0000 {
1166 compatible = "samsung,exynos5433-mfc";
1167 reg = <0x152E0000 0x10000>;
1168 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1169 clock-names = "pclk", "aclk", "aclk_xiu";
1170 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1171 <&cmu_mfc CLK_ACLK_MFC>,
1172 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1173 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1174 iommu-names = "left", "right";
1175 power-domains = <&pd_mfc>;
1176 };
1178 sysmmu_decon0x: sysmmu@13a00000 {
1179 compatible = "samsung,exynos-sysmmu";
1180 reg = <0x13a00000 0x1000>;
1181 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1182 clock-names = "pclk", "aclk";
1183 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
1184 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
1185 power-domains = <&pd_disp>;
1186 #iommu-cells = <0>;
1187 };
1189 sysmmu_decon1x: sysmmu@13a10000 {
1190 compatible = "samsung,exynos-sysmmu";
1191 reg = <0x13a10000 0x1000>;
1192 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1193 clock-names = "pclk", "aclk";
1194 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
1195 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
1196 #iommu-cells = <0>;
1197 power-domains = <&pd_disp>;
1198 };
1200 sysmmu_tv0x: sysmmu@13a20000 {
1201 compatible = "samsung,exynos-sysmmu";
1202 reg = <0x13a20000 0x1000>;
1203 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1204 clock-names = "pclk", "aclk";
1205 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1206 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
1207 #iommu-cells = <0>;
1208 power-domains = <&pd_disp>;
1209 };
1211 sysmmu_tv1x: sysmmu@13a30000 {
1212 compatible = "samsung,exynos-sysmmu";
1213 reg = <0x13a30000 0x1000>;
1214 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1215 clock-names = "pclk", "aclk";
1216 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1217 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
1218 #iommu-cells = <0>;
1219 power-domains = <&pd_disp>;
1220 };
1222 sysmmu_gscl0: sysmmu@13c80000 {
1223 compatible = "samsung,exynos-sysmmu";
1224 reg = <0x13C80000 0x1000>;
1225 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1226 clock-names = "aclk", "pclk";
1227 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1228 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1229 #iommu-cells = <0>;
1230 power-domains = <&pd_gscl>;
1231 };
1233 sysmmu_gscl1: sysmmu@13c90000 {
1234 compatible = "samsung,exynos-sysmmu";
1235 reg = <0x13C90000 0x1000>;
1236 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1237 clock-names = "aclk", "pclk";
1238 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1239 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1240 #iommu-cells = <0>;
1241 power-domains = <&pd_gscl>;
1242 };
1244 sysmmu_gscl2: sysmmu@13ca0000 {
1245 compatible = "samsung,exynos-sysmmu";
1246 reg = <0x13CA0000 0x1000>;
1247 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1248 clock-names = "aclk", "pclk";
1249 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1250 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1251 #iommu-cells = <0>;
1252 power-domains = <&pd_gscl>;
1253 };
1255 sysmmu_scaler_0: sysmmu@15040000 {
1256 compatible = "samsung,exynos-sysmmu";
1257 reg = <0x15040000 0x1000>;
1258 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1259 clock-names = "pclk", "aclk";
1260 clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>,
1261 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>;
1262 #iommu-cells = <0>;
1263 power-domains = <&pd_mscl>;
1264 };
1266 sysmmu_scaler_1: sysmmu@15050000 {
1267 compatible = "samsung,exynos-sysmmu";
1268 reg = <0x15050000 0x1000>;
1269 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1270 clock-names = "pclk", "aclk";
1271 clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>,
1272 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>;
1273 #iommu-cells = <0>;
1274 power-domains = <&pd_mscl>;
1275 };
1277 sysmmu_jpeg: sysmmu@15060000 {
1278 compatible = "samsung,exynos-sysmmu";
1279 reg = <0x15060000 0x1000>;
1280 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1281 clock-names = "pclk", "aclk";
1282 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1283 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1284 #iommu-cells = <0>;
1285 power-domains = <&pd_mscl>;
1286 };
1288 sysmmu_mfc_0: sysmmu@15200000 {
1289 compatible = "samsung,exynos-sysmmu";
1290 reg = <0x15200000 0x1000>;
1291 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1292 clock-names = "pclk", "aclk";
1293 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1294 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1295 #iommu-cells = <0>;
1296 power-domains = <&pd_mfc>;
1297 };
1299 sysmmu_mfc_1: sysmmu@15210000 {
1300 compatible = "samsung,exynos-sysmmu";
1301 reg = <0x15210000 0x1000>;
1302 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1303 clock-names = "pclk", "aclk";
1304 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1305 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1306 #iommu-cells = <0>;
1307 power-domains = <&pd_mfc>;
1308 };
1310 serial_0: serial@14c10000 {
1311 compatible = "samsung,exynos5433-uart";
1312 reg = <0x14c10000 0x100>;
1313 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&cmu_peric CLK_PCLK_UART0>,
1315 <&cmu_peric CLK_SCLK_UART0>;
1316 clock-names = "uart", "clk_uart_baud0";
1317 pinctrl-names = "default";
1318 pinctrl-0 = <&uart0_bus>;
1319 status = "disabled";
1320 };
1322 serial_1: serial@14c20000 {
1323 compatible = "samsung,exynos5433-uart";
1324 reg = <0x14c20000 0x100>;
1325 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&cmu_peric CLK_PCLK_UART1>,
1327 <&cmu_peric CLK_SCLK_UART1>;
1328 clock-names = "uart", "clk_uart_baud0";
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&uart1_bus>;
1331 status = "disabled";
1332 };
1334 serial_2: serial@14c30000 {
1335 compatible = "samsung,exynos5433-uart";
1336 reg = <0x14c30000 0x100>;
1337 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1338 clocks = <&cmu_peric CLK_PCLK_UART2>,
1339 <&cmu_peric CLK_SCLK_UART2>;
1340 clock-names = "uart", "clk_uart_baud0";
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&uart2_bus>;
1343 status = "disabled";
1344 };
1346 spi_0: spi@14d20000 {
1347 compatible = "samsung,exynos5433-spi";
1348 reg = <0x14d20000 0x100>;
1349 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1350 dmas = <&pdma0 9>, <&pdma0 8>;
1351 dma-names = "tx", "rx";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1354 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1355 <&cmu_peric CLK_SCLK_SPI0>,
1356 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1357 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1358 samsung,spi-src-clk = <0>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&spi0_bus>;
1361 num-cs = <1>;
1362 status = "disabled";
1363 };
1365 spi_1: spi@14d30000 {
1366 compatible = "samsung,exynos5433-spi";
1367 reg = <0x14d30000 0x100>;
1368 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&pdma0 11>, <&pdma0 10>;
1370 dma-names = "tx", "rx";
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1373 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1374 <&cmu_peric CLK_SCLK_SPI1>,
1375 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1376 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1377 samsung,spi-src-clk = <0>;
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&spi1_bus>;
1380 num-cs = <1>;
1381 status = "disabled";
1382 };
1384 spi_2: spi@14d40000 {
1385 compatible = "samsung,exynos5433-spi";
1386 reg = <0x14d40000 0x100>;
1387 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1388 dmas = <&pdma0 13>, <&pdma0 12>;
1389 dma-names = "tx", "rx";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1393 <&cmu_peric CLK_SCLK_SPI2>,
1394 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1395 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1396 samsung,spi-src-clk = <0>;
1397 pinctrl-names = "default";
1398 pinctrl-0 = <&spi2_bus>;
1399 num-cs = <1>;
1400 status = "disabled";
1401 };
1403 spi_3: spi@14d50000 {
1404 compatible = "samsung,exynos5433-spi";
1405 reg = <0x14d50000 0x100>;
1406 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1407 dmas = <&pdma0 23>, <&pdma0 22>;
1408 dma-names = "tx", "rx";
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1411 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1412 <&cmu_peric CLK_SCLK_SPI3>,
1413 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1414 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1415 samsung,spi-src-clk = <0>;
1416 pinctrl-names = "default";
1417 pinctrl-0 = <&spi3_bus>;
1418 num-cs = <1>;
1419 status = "disabled";
1420 };
1422 spi_4: spi@14d00000 {
1423 compatible = "samsung,exynos5433-spi";
1424 reg = <0x14d00000 0x100>;
1425 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1426 dmas = <&pdma0 25>, <&pdma0 24>;
1427 dma-names = "tx", "rx";
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1430 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1431 <&cmu_peric CLK_SCLK_SPI4>,
1432 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1433 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1434 samsung,spi-src-clk = <0>;
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&spi4_bus>;
1437 num-cs = <1>;
1438 status = "disabled";
1439 };
1441 adc: adc@14d10000 {
1442 compatible = "samsung,exynos7-adc";
1443 reg = <0x14d10000 0x100>;
1444 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1445 clock-names = "adc";
1446 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1447 #io-channel-cells = <1>;
1448 io-channel-ranges;
1449 status = "disabled";
1450 };
1452 i2s1: i2s@14d60000 {
1453 compatible = "samsung,exynos7-i2s";
1454 reg = <0x14d60000 0x100>;
1455 dmas = <&pdma0 31 &pdma0 30>;
1456 dma-names = "tx", "rx";
1457 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&cmu_peric CLK_PCLK_I2S1>,
1459 <&cmu_peric CLK_PCLK_I2S1>,
1460 <&cmu_peric CLK_SCLK_I2S1>;
1461 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1462 #clock-cells = <1>;
1463 samsung,supports-6ch;
1464 samsung,supports-rstclr;
1465 samsung,supports-tdm;
1466 samsung,supports-low-rfs;
1467 #sound-dai-cells = <1>;
1468 status = "disabled";
1469 };
1471 pwm: pwm@14dd0000 {
1472 compatible = "samsung,exynos4210-pwm";
1473 reg = <0x14dd0000 0x100>;
1474 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1479 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1480 clocks = <&cmu_peric CLK_PCLK_PWM>;
1481 clock-names = "timers";
1482 #pwm-cells = <3>;
1483 status = "disabled";
1484 };
1486 hsi2c_0: hsi2c@14e40000 {
1487 compatible = "samsung,exynos7-hsi2c";
1488 reg = <0x14e40000 0x1000>;
1489 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&hs_i2c0_bus>;
1494 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1495 clock-names = "hsi2c";
1496 status = "disabled";
1497 };
1499 hsi2c_1: hsi2c@14e50000 {
1500 compatible = "samsung,exynos7-hsi2c";
1501 reg = <0x14e50000 0x1000>;
1502 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&hs_i2c1_bus>;
1507 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1508 clock-names = "hsi2c";
1509 status = "disabled";
1510 };
1512 hsi2c_2: hsi2c@14e60000 {
1513 compatible = "samsung,exynos7-hsi2c";
1514 reg = <0x14e60000 0x1000>;
1515 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&hs_i2c2_bus>;
1520 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1521 clock-names = "hsi2c";
1522 status = "disabled";
1523 };
1525 hsi2c_3: hsi2c@14e70000 {
1526 compatible = "samsung,exynos7-hsi2c";
1527 reg = <0x14e70000 0x1000>;
1528 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1531 pinctrl-names = "default";
1532 pinctrl-0 = <&hs_i2c3_bus>;
1533 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1534 clock-names = "hsi2c";
1535 status = "disabled";
1536 };
1538 hsi2c_4: hsi2c@14ec0000 {
1539 compatible = "samsung,exynos7-hsi2c";
1540 reg = <0x14ec0000 0x1000>;
1541 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 pinctrl-names = "default";
1545 pinctrl-0 = <&hs_i2c4_bus>;
1546 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1547 clock-names = "hsi2c";
1548 status = "disabled";
1549 };
1551 hsi2c_5: hsi2c@14ed0000 {
1552 compatible = "samsung,exynos7-hsi2c";
1553 reg = <0x14ed0000 0x1000>;
1554 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1557 pinctrl-names = "default";
1558 pinctrl-0 = <&hs_i2c5_bus>;
1559 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1560 clock-names = "hsi2c";
1561 status = "disabled";
1562 };
1564 hsi2c_6: hsi2c@14ee0000 {
1565 compatible = "samsung,exynos7-hsi2c";
1566 reg = <0x14ee0000 0x1000>;
1567 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&hs_i2c6_bus>;
1572 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1573 clock-names = "hsi2c";
1574 status = "disabled";
1575 };
1577 hsi2c_7: hsi2c@14ef0000 {
1578 compatible = "samsung,exynos7-hsi2c";
1579 reg = <0x14ef0000 0x1000>;
1580 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1581 #address-cells = <1>;
1582 #size-cells = <0>;
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&hs_i2c7_bus>;
1585 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1586 clock-names = "hsi2c";
1587 status = "disabled";
1588 };
1590 hsi2c_8: hsi2c@14d90000 {
1591 compatible = "samsung,exynos7-hsi2c";
1592 reg = <0x14d90000 0x1000>;
1593 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1594 #address-cells = <1>;
1595 #size-cells = <0>;
1596 pinctrl-names = "default";
1597 pinctrl-0 = <&hs_i2c8_bus>;
1598 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1599 clock-names = "hsi2c";
1600 status = "disabled";
1601 };
1603 hsi2c_9: hsi2c@14da0000 {
1604 compatible = "samsung,exynos7-hsi2c";
1605 reg = <0x14da0000 0x1000>;
1606 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&hs_i2c9_bus>;
1611 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1612 clock-names = "hsi2c";
1613 status = "disabled";
1614 };
1616 hsi2c_10: hsi2c@14de0000 {
1617 compatible = "samsung,exynos7-hsi2c";
1618 reg = <0x14de0000 0x1000>;
1619 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1620 #address-cells = <1>;
1621 #size-cells = <0>;
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&hs_i2c10_bus>;
1624 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1625 clock-names = "hsi2c";
1626 status = "disabled";
1627 };
1629 hsi2c_11: hsi2c@14df0000 {
1630 compatible = "samsung,exynos7-hsi2c";
1631 reg = <0x14df0000 0x1000>;
1632 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1633 #address-cells = <1>;
1634 #size-cells = <0>;
1635 pinctrl-names = "default";
1636 pinctrl-0 = <&hs_i2c11_bus>;
1637 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1638 clock-names = "hsi2c";
1639 status = "disabled";
1640 };
1642 usbdrd30: usbdrd {
1643 compatible = "samsung,exynos5433-dwusb3";
1644 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1645 <&cmu_fsys CLK_SCLK_USBDRD30>,
1646 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1647 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1648 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1649 #address-cells = <1>;
1650 #size-cells = <1>;
1651 ranges;
1652 status = "disabled";
1654 usbdrd_dwc3: dwc3@15400000 {
1655 compatible = "snps,dwc3";
1656 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1657 <&cmu_fsys CLK_ACLK_USBDRD30>,
1658 <&cmu_fsys CLK_SCLK_USBDRD30>;
1659 clock-names = "ref", "bus_early", "suspend";
1660 reg = <0x15400000 0x10000>;
1661 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1662 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1663 phy-names = "usb2-phy", "usb3-phy";
1664 };
1665 };
1667 usbdrd30_phy: phy@15500000 {
1668 compatible = "samsung,exynos5433-usbdrd-phy";
1669 reg = <0x15500000 0x100>;
1670 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1671 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1672 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1673 <&cmu_fsys CLK_SCLK_USBDRD30>;
1674 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1675 "itp";
1676 #phy-cells = <1>;
1677 samsung,pmu-syscon = <&pmu_system_controller>;
1678 status = "disabled";
1679 };
1681 usbhost30_phy: phy@15580000 {
1682 compatible = "samsung,exynos5433-usbdrd-phy";
1683 reg = <0x15580000 0x100>;
1684 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1685 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1686 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1687 <&cmu_fsys CLK_SCLK_USBHOST30>;
1688 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1689 "itp";
1690 #phy-cells = <1>;
1691 samsung,pmu-syscon = <&pmu_system_controller>;
1692 status = "disabled";
1693 };
1695 usbhost30: usbhost {
1696 compatible = "samsung,exynos5433-dwusb3";
1697 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1698 <&cmu_fsys CLK_SCLK_USBHOST30>,
1699 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1700 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1701 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1702 #address-cells = <1>;
1703 #size-cells = <1>;
1704 ranges;
1705 status = "disabled";
1707 usbhost_dwc3: dwc3@15a00000 {
1708 compatible = "snps,dwc3";
1709 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1710 <&cmu_fsys CLK_ACLK_USBHOST30>,
1711 <&cmu_fsys CLK_SCLK_USBHOST30>;
1712 clock-names = "ref", "bus_early", "suspend";
1713 reg = <0x15a00000 0x10000>;
1714 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1715 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1716 phy-names = "usb2-phy", "usb3-phy";
1717 };
1718 };
1720 mshc_0: mshc@15540000 {
1721 compatible = "samsung,exynos7-dw-mshc-smu";
1722 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1725 reg = <0x15540000 0x2000>;
1726 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1727 <&cmu_fsys CLK_SCLK_MMC0>;
1728 clock-names = "biu", "ciu";
1729 fifo-depth = <0x40>;
1730 status = "disabled";
1731 };
1733 mshc_1: mshc@15550000 {
1734 compatible = "samsung,exynos7-dw-mshc-smu";
1735 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738 reg = <0x15550000 0x2000>;
1739 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1740 <&cmu_fsys CLK_SCLK_MMC1>;
1741 clock-names = "biu", "ciu";
1742 fifo-depth = <0x40>;
1743 status = "disabled";
1744 };
1746 mshc_2: mshc@15560000 {
1747 compatible = "samsung,exynos7-dw-mshc-smu";
1748 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1751 reg = <0x15560000 0x2000>;
1752 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1753 <&cmu_fsys CLK_SCLK_MMC2>;
1754 clock-names = "biu", "ciu";
1755 fifo-depth = <0x40>;
1756 status = "disabled";
1757 };
1759 amba {
1760 compatible = "simple-bus";
1761 #address-cells = <1>;
1762 #size-cells = <1>;
1763 ranges;
1765 pdma0: pdma@15610000 {
1766 compatible = "arm,pl330", "arm,primecell";
1767 reg = <0x15610000 0x1000>;
1768 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1769 clocks = <&cmu_fsys CLK_PDMA0>;
1770 clock-names = "apb_pclk";
1771 #dma-cells = <1>;
1772 #dma-channels = <8>;
1773 #dma-requests = <32>;
1774 };
1776 pdma1: pdma@15600000 {
1777 compatible = "arm,pl330", "arm,primecell";
1778 reg = <0x15600000 0x1000>;
1779 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1780 clocks = <&cmu_fsys CLK_PDMA1>;
1781 clock-names = "apb_pclk";
1782 #dma-cells = <1>;
1783 #dma-channels = <8>;
1784 #dma-requests = <32>;
1785 };
1786 };
1788 audio-subsystem@11400000 {
1789 compatible = "samsung,exynos5433-lpass";
1790 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1791 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1792 clock-names = "sfr0_ctrl";
1793 samsung,pmu-syscon = <&pmu_system_controller>;
1794 power-domains = <&pd_aud>;
1795 #address-cells = <1>;
1796 #size-cells = <1>;
1797 ranges;
1799 adma: adma@11420000 {
1800 compatible = "arm,pl330", "arm,primecell";
1801 reg = <0x11420000 0x1000>;
1802 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1803 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1804 clock-names = "apb_pclk";
1805 #dma-cells = <1>;
1806 #dma-channels = <8>;
1807 #dma-requests = <32>;
1808 power-domains = <&pd_aud>;
1809 };
1811 i2s0: i2s@11440000 {
1812 compatible = "samsung,exynos7-i2s";
1813 reg = <0x11440000 0x100>;
1814 dmas = <&adma 0 &adma 2>;
1815 dma-names = "tx", "rx";
1816 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1819 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1820 <&cmu_aud CLK_SCLK_AUD_I2S>,
1821 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1822 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1823 #clock-cells = <1>;
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&i2s0_bus>;
1826 power-domains = <&pd_aud>;
1827 #sound-dai-cells = <1>;
1828 status = "disabled";
1829 };
1831 serial_3: serial@11460000 {
1832 compatible = "samsung,exynos5433-uart";
1833 reg = <0x11460000 0x100>;
1834 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1835 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1836 <&cmu_aud CLK_SCLK_AUD_UART>;
1837 clock-names = "uart", "clk_uart_baud0";
1838 pinctrl-names = "default";
1839 pinctrl-0 = <&uart_aud_bus>;
1840 power-domains = <&pd_aud>;
1841 status = "disabled";
1842 };
1843 };
1844 };
1846 timer: timer {
1847 compatible = "arm,armv8-timer";
1848 interrupts = <GIC_PPI 13
1849 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1850 <GIC_PPI 14
1851 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1852 <GIC_PPI 11
1853 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1854 <GIC_PPI 10
1855 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1856 };
1857 };
1859 #include "exynos5433-bus.dtsi"
1860 #include "exynos5433-pinctrl.dtsi"
1861 #include "exynos5433-tmu.dtsi"