| blob | 52aae341d0da5046e997026a7bbede672b74318b |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
16 / {
17 interrupt-parent = <&gpc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 aliases {
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 serial3 = &uart4;
36 spi0 = &ecspi1;
37 spi1 = &ecspi2;
38 spi2 = &ecspi3;
39 };
41 ckil: clock-ckil {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <32768>;
45 clock-output-names = "ckil";
46 };
48 osc_25m: clock-osc-25m {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <25000000>;
52 clock-output-names = "osc_25m";
53 };
55 osc_27m: clock-osc-27m {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <27000000>;
59 clock-output-names = "osc_27m";
60 };
62 clk_ext1: clock-ext1 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <133000000>;
66 clock-output-names = "clk_ext1";
67 };
69 clk_ext2: clock-ext2 {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <133000000>;
73 clock-output-names = "clk_ext2";
74 };
76 clk_ext3: clock-ext3 {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <133000000>;
80 clock-output-names = "clk_ext3";
81 };
83 clk_ext4: clock-ext4 {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency= <133000000>;
87 clock-output-names = "clk_ext4";
88 };
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
94 A53_0: cpu@0 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53";
97 reg = <0x0>;
98 clock-latency = <61036>; /* two CLK32 periods */
99 clocks = <&clk IMX8MQ_CLK_ARM>;
100 enable-method = "psci";
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
104 nvmem-cells = <&cpu_speed_grade>;
105 nvmem-cell-names = "speed_grade";
106 };
108 A53_1: cpu@1 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a53";
111 reg = <0x1>;
112 clock-latency = <61036>; /* two CLK32 periods */
113 clocks = <&clk IMX8MQ_CLK_ARM>;
114 enable-method = "psci";
115 next-level-cache = <&A53_L2>;
116 operating-points-v2 = <&a53_opp_table>;
117 #cooling-cells = <2>;
118 };
120 A53_2: cpu@2 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a53";
123 reg = <0x2>;
124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MQ_CLK_ARM>;
126 enable-method = "psci";
127 next-level-cache = <&A53_L2>;
128 operating-points-v2 = <&a53_opp_table>;
129 #cooling-cells = <2>;
130 };
132 A53_3: cpu@3 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a53";
135 reg = <0x3>;
136 clock-latency = <61036>; /* two CLK32 periods */
137 clocks = <&clk IMX8MQ_CLK_ARM>;
138 enable-method = "psci";
139 next-level-cache = <&A53_L2>;
140 operating-points-v2 = <&a53_opp_table>;
141 #cooling-cells = <2>;
142 };
144 A53_L2: l2-cache0 {
145 compatible = "cache";
146 };
147 };
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-800000000 {
154 opp-hz = /bits/ 64 <800000000>;
155 opp-microvolt = <900000>;
156 /* Industrial only */
157 opp-supported-hw = <0xf>, <0x4>;
158 clock-latency-ns = <150000>;
159 };
161 opp-1000000000 {
162 opp-hz = /bits/ 64 <1000000000>;
163 opp-microvolt = <900000>;
164 /* Consumer only */
165 opp-supported-hw = <0xe>, <0x3>;
166 clock-latency-ns = <150000>;
167 };
169 opp-1300000000 {
170 opp-hz = /bits/ 64 <1300000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0xc>, <0x7>;
173 clock-latency-ns = <150000>;
174 };
176 opp-1500000000 {
177 opp-hz = /bits/ 64 <1500000000>;
178 opp-microvolt = <1000000>;
179 /* Consumer only but rely on speed grading */
180 opp-supported-hw = <0x8>, <0x7>;
181 clock-latency-ns = <150000>;
182 };
183 };
185 pmu {
186 compatible = "arm,cortex-a53-pmu";
187 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-parent = <&gic>;
189 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
190 };
192 psci {
193 compatible = "arm,psci-1.0";
194 method = "smc";
195 };
197 thermal-zones {
198 cpu-thermal {
199 polling-delay-passive = <250>;
200 polling-delay = <2000>;
201 thermal-sensors = <&tmu 0>;
203 trips {
204 cpu_alert: cpu-alert {
205 temperature = <80000>;
206 hysteresis = <2000>;
207 type = "passive";
208 };
210 cpu-crit {
211 temperature = <90000>;
212 hysteresis = <2000>;
213 type = "critical";
214 };
215 };
217 cooling-maps {
218 map0 {
219 trip = <&cpu_alert>;
220 cooling-device =
221 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
222 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
223 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
225 };
226 };
227 };
229 gpu-thermal {
230 polling-delay-passive = <250>;
231 polling-delay = <2000>;
232 thermal-sensors = <&tmu 1>;
234 trips {
235 gpu-crit {
236 temperature = <90000>;
237 hysteresis = <2000>;
238 type = "critical";
239 };
240 };
241 };
243 vpu-thermal {
244 polling-delay-passive = <250>;
245 polling-delay = <2000>;
246 thermal-sensors = <&tmu 2>;
248 trips {
249 vpu-crit {
250 temperature = <90000>;
251 hysteresis = <2000>;
252 type = "critical";
253 };
254 };
255 };
256 };
258 timer {
259 compatible = "arm,armv8-timer";
260 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
261 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
262 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
263 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
264 interrupt-parent = <&gic>;
265 arm,no-tick-in-suspend;
266 };
268 soc@0 {
269 compatible = "simple-bus";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges = <0x0 0x0 0x0 0x3e000000>;
273 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
275 bus@30000000 { /* AIPS1 */
276 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 ranges = <0x30000000 0x30000000 0x400000>;
281 gpio1: gpio@30200000 {
282 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
283 reg = <0x30200000 0x10000>;
284 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
287 gpio-controller;
288 #gpio-cells = <2>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 };
293 gpio2: gpio@30210000 {
294 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
295 reg = <0x30210000 0x10000>;
296 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
299 gpio-controller;
300 #gpio-cells = <2>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 };
305 gpio3: gpio@30220000 {
306 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
307 reg = <0x30220000 0x10000>;
308 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
311 gpio-controller;
312 #gpio-cells = <2>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 };
317 gpio4: gpio@30230000 {
318 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
319 reg = <0x30230000 0x10000>;
320 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
329 gpio5: gpio@30240000 {
330 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
331 reg = <0x30240000 0x10000>;
332 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 };
341 tmu: tmu@30260000 {
342 compatible = "fsl,imx8mq-tmu";
343 reg = <0x30260000 0x10000>;
344 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
345 little-endian;
346 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
347 fsl,tmu-calibration = <0x00000000 0x00000023
348 0x00000001 0x00000029
349 0x00000002 0x0000002f
350 0x00000003 0x00000035
351 0x00000004 0x0000003d
352 0x00000005 0x00000043
353 0x00000006 0x0000004b
354 0x00000007 0x00000051
355 0x00000008 0x00000057
356 0x00000009 0x0000005f
357 0x0000000a 0x00000067
358 0x0000000b 0x0000006f
360 0x00010000 0x0000001b
361 0x00010001 0x00000023
362 0x00010002 0x0000002b
363 0x00010003 0x00000033
364 0x00010004 0x0000003b
365 0x00010005 0x00000043
366 0x00010006 0x0000004b
367 0x00010007 0x00000055
368 0x00010008 0x0000005d
369 0x00010009 0x00000067
370 0x0001000a 0x00000070
372 0x00020000 0x00000017
373 0x00020001 0x00000023
374 0x00020002 0x0000002d
375 0x00020003 0x00000037
376 0x00020004 0x00000041
377 0x00020005 0x0000004b
378 0x00020006 0x00000057
379 0x00020007 0x00000063
380 0x00020008 0x0000006f
382 0x00030000 0x00000015
383 0x00030001 0x00000021
384 0x00030002 0x0000002d
385 0x00030003 0x00000039
386 0x00030004 0x00000045
387 0x00030005 0x00000053
388 0x00030006 0x0000005f
389 0x00030007 0x00000071>;
390 #thermal-sensor-cells = <1>;
391 };
393 wdog1: watchdog@30280000 {
394 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
395 reg = <0x30280000 0x10000>;
396 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
398 status = "disabled";
399 };
401 wdog2: watchdog@30290000 {
402 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
403 reg = <0x30290000 0x10000>;
404 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
406 status = "disabled";
407 };
409 wdog3: watchdog@302a0000 {
410 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
411 reg = <0x302a0000 0x10000>;
412 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
414 status = "disabled";
415 };
417 sdma2: sdma@302c0000 {
418 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
419 reg = <0x302c0000 0x10000>;
420 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
422 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
423 clock-names = "ipg", "ahb";
424 #dma-cells = <3>;
425 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
426 };
428 iomuxc: iomuxc@30330000 {
429 compatible = "fsl,imx8mq-iomuxc";
430 reg = <0x30330000 0x10000>;
431 };
433 iomuxc_gpr: syscon@30340000 {
434 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
435 reg = <0x30340000 0x10000>;
436 };
438 ocotp: ocotp-ctrl@30350000 {
439 compatible = "fsl,imx8mq-ocotp", "syscon";
440 reg = <0x30350000 0x10000>;
441 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
442 #address-cells = <1>;
443 #size-cells = <1>;
445 cpu_speed_grade: speed-grade@10 {
446 reg = <0x10 4>;
447 };
448 };
450 anatop: syscon@30360000 {
451 compatible = "fsl,imx8mq-anatop", "syscon";
452 reg = <0x30360000 0x10000>;
453 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
454 };
456 snvs: snvs@30370000 {
457 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
458 reg = <0x30370000 0x10000>;
460 snvs_rtc: snvs-rtc-lp{
461 compatible = "fsl,sec-v4.0-mon-rtc-lp";
462 regmap =<&snvs>;
463 offset = <0x34>;
464 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
467 clock-names = "snvs-rtc";
468 };
470 snvs_pwrkey: snvs-powerkey {
471 compatible = "fsl,sec-v4.0-pwrkey";
472 regmap = <&snvs>;
473 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
474 linux,keycode = <KEY_POWER>;
475 wakeup-source;
476 status = "disabled";
477 };
478 };
480 clk: clock-controller@30380000 {
481 compatible = "fsl,imx8mq-ccm";
482 reg = <0x30380000 0x10000>;
483 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
485 #clock-cells = <1>;
486 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
487 <&clk_ext1>, <&clk_ext2>,
488 <&clk_ext3>, <&clk_ext4>;
489 clock-names = "ckil", "osc_25m", "osc_27m",
490 "clk_ext1", "clk_ext2",
491 "clk_ext3", "clk_ext4";
492 };
494 src: reset-controller@30390000 {
495 compatible = "fsl,imx8mq-src", "syscon";
496 reg = <0x30390000 0x10000>;
497 #reset-cells = <1>;
498 };
500 gpc: gpc@303a0000 {
501 compatible = "fsl,imx8mq-gpc";
502 reg = <0x303a0000 0x10000>;
503 interrupt-parent = <&gic>;
504 interrupt-controller;
505 #interrupt-cells = <3>;
507 pgc {
508 #address-cells = <1>;
509 #size-cells = <0>;
511 pgc_mipi: power-domain@0 {
512 #power-domain-cells = <0>;
513 reg = <IMX8M_POWER_DOMAIN_MIPI>;
514 };
516 /*
517 * As per comment in ATF source code:
518 *
519 * PCIE1 and PCIE2 share the
520 * same reset signal, if we
521 * power down PCIE2, PCIE1
522 * will be held in reset too.
523 *
524 * So instead of creating two
525 * separate power domains for
526 * PCIE1 and PCIE2 we create a
527 * link between both and use
528 * it as a shared PCIE power
529 * domain.
530 */
531 pgc_pcie: power-domain@1 {
532 #power-domain-cells = <0>;
533 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
534 power-domains = <&pgc_pcie2>;
535 };
537 pgc_otg1: power-domain@2 {
538 #power-domain-cells = <0>;
539 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
540 };
542 pgc_otg2: power-domain@3 {
543 #power-domain-cells = <0>;
544 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
545 };
547 pgc_ddr1: power-domain@4 {
548 #power-domain-cells = <0>;
549 reg = <IMX8M_POWER_DOMAIN_DDR1>;
550 };
552 pgc_gpu: power-domain@5 {
553 #power-domain-cells = <0>;
554 reg = <IMX8M_POWER_DOMAIN_GPU>;
555 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
556 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
557 <&clk IMX8MQ_CLK_GPU_AXI>,
558 <&clk IMX8MQ_CLK_GPU_AHB>;
559 };
561 pgc_vpu: power-domain@6 {
562 #power-domain-cells = <0>;
563 reg = <IMX8M_POWER_DOMAIN_VPU>;
564 };
566 pgc_disp: power-domain@7 {
567 #power-domain-cells = <0>;
568 reg = <IMX8M_POWER_DOMAIN_DISP>;
569 };
571 pgc_mipi_csi1: power-domain@8 {
572 #power-domain-cells = <0>;
573 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
574 };
576 pgc_mipi_csi2: power-domain@9 {
577 #power-domain-cells = <0>;
578 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
579 };
581 pgc_pcie2: power-domain@a {
582 #power-domain-cells = <0>;
583 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
584 };
585 };
586 };
587 };
589 bus@30400000 { /* AIPS2 */
590 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
591 #address-cells = <1>;
592 #size-cells = <1>;
593 ranges = <0x30400000 0x30400000 0x400000>;
595 pwm1: pwm@30660000 {
596 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
597 reg = <0x30660000 0x10000>;
598 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
600 <&clk IMX8MQ_CLK_PWM1_ROOT>;
601 clock-names = "ipg", "per";
602 #pwm-cells = <2>;
603 status = "disabled";
604 };
606 pwm2: pwm@30670000 {
607 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
608 reg = <0x30670000 0x10000>;
609 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
611 <&clk IMX8MQ_CLK_PWM2_ROOT>;
612 clock-names = "ipg", "per";
613 #pwm-cells = <2>;
614 status = "disabled";
615 };
617 pwm3: pwm@30680000 {
618 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
619 reg = <0x30680000 0x10000>;
620 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
622 <&clk IMX8MQ_CLK_PWM3_ROOT>;
623 clock-names = "ipg", "per";
624 #pwm-cells = <2>;
625 status = "disabled";
626 };
628 pwm4: pwm@30690000 {
629 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
630 reg = <0x30690000 0x10000>;
631 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
633 <&clk IMX8MQ_CLK_PWM4_ROOT>;
634 clock-names = "ipg", "per";
635 #pwm-cells = <2>;
636 status = "disabled";
637 };
638 };
640 bus@30800000 { /* AIPS3 */
641 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0x30800000 0x30800000 0x400000>,
645 <0x08000000 0x08000000 0x10000000>;
647 ecspi1: spi@30820000 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
651 reg = <0x30820000 0x10000>;
652 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
654 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
655 clock-names = "ipg", "per";
656 status = "disabled";
657 };
659 ecspi2: spi@30830000 {
660 #address-cells = <1>;
661 #size-cells = <0>;
662 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
663 reg = <0x30830000 0x10000>;
664 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
666 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
667 clock-names = "ipg", "per";
668 status = "disabled";
669 };
671 ecspi3: spi@30840000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
675 reg = <0x30840000 0x10000>;
676 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
678 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
679 clock-names = "ipg", "per";
680 status = "disabled";
681 };
683 uart1: serial@30860000 {
684 compatible = "fsl,imx8mq-uart",
685 "fsl,imx6q-uart";
686 reg = <0x30860000 0x10000>;
687 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
689 <&clk IMX8MQ_CLK_UART1_ROOT>;
690 clock-names = "ipg", "per";
691 status = "disabled";
692 };
694 uart3: serial@30880000 {
695 compatible = "fsl,imx8mq-uart",
696 "fsl,imx6q-uart";
697 reg = <0x30880000 0x10000>;
698 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
700 <&clk IMX8MQ_CLK_UART3_ROOT>;
701 clock-names = "ipg", "per";
702 status = "disabled";
703 };
705 uart2: serial@30890000 {
706 compatible = "fsl,imx8mq-uart",
707 "fsl,imx6q-uart";
708 reg = <0x30890000 0x10000>;
709 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
711 <&clk IMX8MQ_CLK_UART2_ROOT>;
712 clock-names = "ipg", "per";
713 status = "disabled";
714 };
716 sai2: sai@308b0000 {
717 #sound-dai-cells = <0>;
718 compatible = "fsl,imx8mq-sai";
719 reg = <0x308b0000 0x10000>;
720 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
722 <&clk IMX8MQ_CLK_SAI2_ROOT>,
723 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
724 clock-names = "bus", "mclk1", "mclk2", "mclk3";
725 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
726 dma-names = "rx", "tx";
727 status = "disabled";
728 };
730 i2c1: i2c@30a20000 {
731 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
732 reg = <0x30a20000 0x10000>;
733 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
735 #address-cells = <1>;
736 #size-cells = <0>;
737 status = "disabled";
738 };
740 i2c2: i2c@30a30000 {
741 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
742 reg = <0x30a30000 0x10000>;
743 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 status = "disabled";
748 };
750 i2c3: i2c@30a40000 {
751 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
752 reg = <0x30a40000 0x10000>;
753 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
755 #address-cells = <1>;
756 #size-cells = <0>;
757 status = "disabled";
758 };
760 i2c4: i2c@30a50000 {
761 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
762 reg = <0x30a50000 0x10000>;
763 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
765 #address-cells = <1>;
766 #size-cells = <0>;
767 status = "disabled";
768 };
770 uart4: serial@30a60000 {
771 compatible = "fsl,imx8mq-uart",
772 "fsl,imx6q-uart";
773 reg = <0x30a60000 0x10000>;
774 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
776 <&clk IMX8MQ_CLK_UART4_ROOT>;
777 clock-names = "ipg", "per";
778 status = "disabled";
779 };
781 usdhc1: mmc@30b40000 {
782 compatible = "fsl,imx8mq-usdhc",
783 "fsl,imx7d-usdhc";
784 reg = <0x30b40000 0x10000>;
785 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MQ_CLK_DUMMY>,
787 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
788 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
789 clock-names = "ipg", "ahb", "per";
790 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
791 assigned-clock-rates = <400000000>;
792 fsl,tuning-start-tap = <20>;
793 fsl,tuning-step = <2>;
794 bus-width = <4>;
795 status = "disabled";
796 };
798 usdhc2: mmc@30b50000 {
799 compatible = "fsl,imx8mq-usdhc",
800 "fsl,imx7d-usdhc";
801 reg = <0x30b50000 0x10000>;
802 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clk IMX8MQ_CLK_DUMMY>,
804 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
805 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
806 clock-names = "ipg", "ahb", "per";
807 fsl,tuning-start-tap = <20>;
808 fsl,tuning-step = <2>;
809 bus-width = <4>;
810 status = "disabled";
811 };
813 qspi0: spi@30bb0000 {
814 #address-cells = <1>;
815 #size-cells = <0>;
816 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
817 reg = <0x30bb0000 0x10000>,
818 <0x08000000 0x10000000>;
819 reg-names = "QuadSPI", "QuadSPI-memory";
820 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
822 <&clk IMX8MQ_CLK_QSPI_ROOT>;
823 clock-names = "qspi_en", "qspi";
824 status = "disabled";
825 };
827 sdma1: sdma@30bd0000 {
828 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
829 reg = <0x30bd0000 0x10000>;
830 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
832 <&clk IMX8MQ_CLK_AHB>;
833 clock-names = "ipg", "ahb";
834 #dma-cells = <3>;
835 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
836 };
838 fec1: ethernet@30be0000 {
839 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
840 reg = <0x30be0000 0x10000>;
841 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
845 <&clk IMX8MQ_CLK_ENET1_ROOT>,
846 <&clk IMX8MQ_CLK_ENET_TIMER>,
847 <&clk IMX8MQ_CLK_ENET_REF>,
848 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
849 clock-names = "ipg", "ahb", "ptp",
850 "enet_clk_ref", "enet_out";
851 fsl,num-tx-queues = <3>;
852 fsl,num-rx-queues = <3>;
853 status = "disabled";
854 };
855 };
857 bus@32c00000 { /* AIPS4 */
858 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
859 #address-cells = <1>;
860 #size-cells = <1>;
861 ranges = <0x32c00000 0x32c00000 0x400000>;
863 irqsteer: interrupt-controller@32e2d000 {
864 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
865 reg = <0x32e2d000 0x1000>;
866 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
868 clock-names = "ipg";
869 fsl,channel = <0>;
870 fsl,num-irqs = <64>;
871 interrupt-controller;
872 #interrupt-cells = <1>;
873 };
874 };
876 gpu: gpu@38000000 {
877 compatible = "vivante,gc";
878 reg = <0x38000000 0x40000>;
879 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
881 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
882 <&clk IMX8MQ_CLK_GPU_AXI>,
883 <&clk IMX8MQ_CLK_GPU_AHB>;
884 clock-names = "core", "shader", "bus", "reg";
885 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
886 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
887 <&clk IMX8MQ_CLK_GPU_AXI>,
888 <&clk IMX8MQ_CLK_GPU_AHB>,
889 <&clk IMX8MQ_GPU_PLL_BYPASS>;
890 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
891 <&clk IMX8MQ_GPU_PLL_OUT>,
892 <&clk IMX8MQ_GPU_PLL_OUT>,
893 <&clk IMX8MQ_GPU_PLL_OUT>,
894 <&clk IMX8MQ_GPU_PLL>;
895 assigned-clock-rates = <800000000>, <800000000>,
896 <800000000>, <800000000>, <0>;
897 power-domains = <&pgc_gpu>;
898 };
900 usb_dwc3_0: usb@38100000 {
901 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
902 reg = <0x38100000 0x10000>;
903 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
904 <&clk IMX8MQ_CLK_USB_CORE_REF>,
905 <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
906 clock-names = "bus_early", "ref", "suspend";
907 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
908 <&clk IMX8MQ_CLK_USB_CORE_REF>;
909 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
910 <&clk IMX8MQ_SYS1_PLL_100M>;
911 assigned-clock-rates = <500000000>, <100000000>;
912 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
913 phys = <&usb3_phy0>, <&usb3_phy0>;
914 phy-names = "usb2-phy", "usb3-phy";
915 power-domains = <&pgc_otg1>;
916 usb3-resume-missing-cas;
917 status = "disabled";
918 };
920 usb3_phy0: usb-phy@381f0040 {
921 compatible = "fsl,imx8mq-usb-phy";
922 reg = <0x381f0040 0x40>;
923 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
924 clock-names = "phy";
925 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
926 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
927 assigned-clock-rates = <100000000>;
928 #phy-cells = <0>;
929 status = "disabled";
930 };
932 usb_dwc3_1: usb@38200000 {
933 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
934 reg = <0x38200000 0x10000>;
935 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
936 <&clk IMX8MQ_CLK_USB_CORE_REF>,
937 <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
938 clock-names = "bus_early", "ref", "suspend";
939 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
940 <&clk IMX8MQ_CLK_USB_CORE_REF>;
941 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
942 <&clk IMX8MQ_SYS1_PLL_100M>;
943 assigned-clock-rates = <500000000>, <100000000>;
944 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
945 phys = <&usb3_phy1>, <&usb3_phy1>;
946 phy-names = "usb2-phy", "usb3-phy";
947 power-domains = <&pgc_otg2>;
948 usb3-resume-missing-cas;
949 status = "disabled";
950 };
952 usb3_phy1: usb-phy@382f0040 {
953 compatible = "fsl,imx8mq-usb-phy";
954 reg = <0x382f0040 0x40>;
955 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
956 clock-names = "phy";
957 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
958 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
959 assigned-clock-rates = <100000000>;
960 #phy-cells = <0>;
961 status = "disabled";
962 };
964 pcie0: pcie@33800000 {
965 compatible = "fsl,imx8mq-pcie";
966 reg = <0x33800000 0x400000>,
967 <0x1ff00000 0x80000>;
968 reg-names = "dbi", "config";
969 #address-cells = <3>;
970 #size-cells = <2>;
971 device_type = "pci";
972 bus-range = <0x00 0xff>;
973 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
974 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
975 num-lanes = <1>;
976 num-viewport = <4>;
977 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
978 interrupt-names = "msi";
979 #interrupt-cells = <1>;
980 interrupt-map-mask = <0 0 0 0x7>;
981 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
982 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
983 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
984 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
985 fsl,max-link-speed = <2>;
986 power-domains = <&pgc_pcie>;
987 resets = <&src IMX8MQ_RESET_PCIEPHY>,
988 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
989 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
990 reset-names = "pciephy", "apps", "turnoff";
991 status = "disabled";
992 };
994 pcie1: pcie@33c00000 {
995 compatible = "fsl,imx8mq-pcie";
996 reg = <0x33c00000 0x400000>,
997 <0x27f00000 0x80000>;
998 reg-names = "dbi", "config";
999 #address-cells = <3>;
1000 #size-cells = <2>;
1001 device_type = "pci";
1002 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1003 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1004 num-lanes = <1>;
1005 num-viewport = <4>;
1006 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1007 interrupt-names = "msi";
1008 #interrupt-cells = <1>;
1009 interrupt-map-mask = <0 0 0 0x7>;
1010 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1011 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1012 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1013 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1014 fsl,max-link-speed = <2>;
1015 power-domains = <&pgc_pcie>;
1016 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1017 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1018 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1019 reset-names = "pciephy", "apps", "turnoff";
1020 status = "disabled";
1021 };
1023 gic: interrupt-controller@38800000 {
1024 compatible = "arm,gic-v3";
1025 reg = <0x38800000 0x10000>, /* GIC Dist */
1026 <0x38880000 0xc0000>, /* GICR */
1027 <0x31000000 0x2000>, /* GICC */
1028 <0x31010000 0x2000>, /* GICV */
1029 <0x31020000 0x2000>; /* GICH */
1030 #interrupt-cells = <3>;
1031 interrupt-controller;
1032 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1033 interrupt-parent = <&gic>;
1034 };
1035 };
1036 };