| blob | 05fa0b7f36bb18375a14d8255e4af2c0c02e5296 |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 gpio0 = &lsio_gpio0;
21 gpio1 = &lsio_gpio1;
22 gpio2 = &lsio_gpio2;
23 gpio3 = &lsio_gpio3;
24 gpio4 = &lsio_gpio4;
25 gpio5 = &lsio_gpio5;
26 gpio6 = &lsio_gpio6;
27 gpio7 = &lsio_gpio7;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 mmc2 = &usdhc3;
31 mu1 = &lsio_mu1;
32 serial0 = &adma_lpuart0;
33 };
35 cpus {
36 #address-cells = <2>;
37 #size-cells = <0>;
39 /* We have 1 clusters with 4 Cortex-A35 cores */
40 A35_0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a35";
43 reg = <0x0 0x0>;
44 enable-method = "psci";
45 next-level-cache = <&A35_L2>;
46 clocks = <&clk IMX_A35_CLK>;
47 operating-points-v2 = <&a35_opp_table>;
48 #cooling-cells = <2>;
49 };
51 A35_1: cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a35";
54 reg = <0x0 0x1>;
55 enable-method = "psci";
56 next-level-cache = <&A35_L2>;
57 clocks = <&clk IMX_A35_CLK>;
58 operating-points-v2 = <&a35_opp_table>;
59 #cooling-cells = <2>;
60 };
62 A35_2: cpu@2 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a35";
65 reg = <0x0 0x2>;
66 enable-method = "psci";
67 next-level-cache = <&A35_L2>;
68 clocks = <&clk IMX_A35_CLK>;
69 operating-points-v2 = <&a35_opp_table>;
70 #cooling-cells = <2>;
71 };
73 A35_3: cpu@3 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a35";
76 reg = <0x0 0x3>;
77 enable-method = "psci";
78 next-level-cache = <&A35_L2>;
79 clocks = <&clk IMX_A35_CLK>;
80 operating-points-v2 = <&a35_opp_table>;
81 #cooling-cells = <2>;
82 };
84 A35_L2: l2-cache0 {
85 compatible = "cache";
86 };
87 };
89 a35_opp_table: opp-table {
90 compatible = "operating-points-v2";
91 opp-shared;
93 opp-900000000 {
94 opp-hz = /bits/ 64 <900000000>;
95 opp-microvolt = <1000000>;
96 clock-latency-ns = <150000>;
97 };
99 opp-1200000000 {
100 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <1100000>;
102 clock-latency-ns = <150000>;
103 opp-suspend;
104 };
105 };
107 gic: interrupt-controller@51a00000 {
108 compatible = "arm,gic-v3";
109 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
110 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
111 #interrupt-cells = <3>;
112 interrupt-controller;
113 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
114 };
116 pmu {
117 compatible = "arm,armv8-pmuv3";
118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
119 };
121 psci {
122 compatible = "arm,psci-1.0";
123 method = "smc";
124 };
126 scu {
127 compatible = "fsl,imx-scu";
128 mbox-names = "tx0", "tx1", "tx2", "tx3",
129 "rx0", "rx1", "rx2", "rx3",
130 "gip3";
131 mboxes = <&lsio_mu1 0 0
132 &lsio_mu1 0 1
133 &lsio_mu1 0 2
134 &lsio_mu1 0 3
135 &lsio_mu1 1 0
136 &lsio_mu1 1 1
137 &lsio_mu1 1 2
138 &lsio_mu1 1 3
139 &lsio_mu1 3 3>;
141 clk: clock-controller {
142 compatible = "fsl,imx8qxp-clk";
143 #clock-cells = <1>;
144 clocks = <&xtal32k &xtal24m>;
145 clock-names = "xtal_32KHz", "xtal_24Mhz";
146 };
148 iomuxc: pinctrl {
149 compatible = "fsl,imx8qxp-iomuxc";
150 };
152 ocotp: imx8qx-ocotp {
153 compatible = "fsl,imx8qxp-scu-ocotp";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 };
158 pd: imx8qx-pd {
159 compatible = "fsl,imx8qxp-scu-pd";
160 #power-domain-cells = <1>;
161 };
163 rtc: rtc {
164 compatible = "fsl,imx8qxp-sc-rtc";
165 };
167 watchdog {
168 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
169 timeout-sec = <60>;
170 };
171 };
173 timer {
174 compatible = "arm,armv8-timer";
175 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
176 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
177 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
178 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
179 };
181 xtal32k: clock-xtal32k {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <32768>;
185 clock-output-names = "xtal_32KHz";
186 };
188 xtal24m: clock-xtal24m {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <24000000>;
192 clock-output-names = "xtal_24MHz";
193 };
195 adma_subsys: bus@59000000 {
196 compatible = "simple-bus";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
201 adma_lpcg: clock-controller@59000000 {
202 compatible = "fsl,imx8qxp-lpcg-adma";
203 reg = <0x59000000 0x2000000>;
204 #clock-cells = <1>;
205 };
207 adma_lpuart0: serial@5a060000 {
208 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
209 reg = <0x5a060000 0x1000>;
210 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-parent = <&gic>;
212 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
213 clock-names = "ipg";
214 power-domains = <&pd IMX_SC_R_UART_0>;
215 status = "disabled";
216 };
218 adma_lpuart1: serial@5a070000 {
219 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
220 reg = <0x5a070000 0x1000>;
221 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
222 interrupt-parent = <&gic>;
223 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
224 clock-names = "ipg";
225 power-domains = <&pd IMX_SC_R_UART_1>;
226 status = "disabled";
227 };
229 adma_lpuart2: serial@5a080000 {
230 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
231 reg = <0x5a080000 0x1000>;
232 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
233 interrupt-parent = <&gic>;
234 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
235 clock-names = "ipg";
236 power-domains = <&pd IMX_SC_R_UART_2>;
237 status = "disabled";
238 };
240 adma_lpuart3: serial@5a090000 {
241 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
242 reg = <0x5a090000 0x1000>;
243 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-parent = <&gic>;
245 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
246 clock-names = "ipg";
247 power-domains = <&pd IMX_SC_R_UART_3>;
248 status = "disabled";
249 };
251 adma_i2c0: i2c@5a800000 {
252 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
253 reg = <0x5a800000 0x4000>;
254 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
255 interrupt-parent = <&gic>;
256 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
257 clock-names = "per";
258 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
259 assigned-clock-rates = <24000000>;
260 power-domains = <&pd IMX_SC_R_I2C_0>;
261 status = "disabled";
262 };
264 adma_i2c1: i2c@5a810000 {
265 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
266 reg = <0x5a810000 0x4000>;
267 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-parent = <&gic>;
269 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
270 clock-names = "per";
271 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
272 assigned-clock-rates = <24000000>;
273 power-domains = <&pd IMX_SC_R_I2C_1>;
274 status = "disabled";
275 };
277 adma_i2c2: i2c@5a820000 {
278 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
279 reg = <0x5a820000 0x4000>;
280 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-parent = <&gic>;
282 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
283 clock-names = "per";
284 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
285 assigned-clock-rates = <24000000>;
286 power-domains = <&pd IMX_SC_R_I2C_2>;
287 status = "disabled";
288 };
290 adma_i2c3: i2c@5a830000 {
291 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
292 reg = <0x5a830000 0x4000>;
293 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-parent = <&gic>;
295 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
296 clock-names = "per";
297 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
298 assigned-clock-rates = <24000000>;
299 power-domains = <&pd IMX_SC_R_I2C_3>;
300 status = "disabled";
301 };
302 };
304 conn_subsys: bus@5b000000 {
305 compatible = "simple-bus";
306 #address-cells = <1>;
307 #size-cells = <1>;
308 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
310 conn_lpcg: clock-controller@5b200000 {
311 compatible = "fsl,imx8qxp-lpcg-conn";
312 reg = <0x5b200000 0xb0000>;
313 #clock-cells = <1>;
314 };
316 usdhc1: mmc@5b010000 {
317 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
318 interrupt-parent = <&gic>;
319 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
320 reg = <0x5b010000 0x10000>;
321 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
322 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
323 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
324 clock-names = "ipg", "per", "ahb";
325 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
326 assigned-clock-rates = <200000000>;
327 power-domains = <&pd IMX_SC_R_SDHC_0>;
328 status = "disabled";
329 };
331 usdhc2: mmc@5b020000 {
332 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
333 interrupt-parent = <&gic>;
334 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
335 reg = <0x5b020000 0x10000>;
336 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
337 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
338 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
339 clock-names = "ipg", "per", "ahb";
340 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
341 assigned-clock-rates = <200000000>;
342 power-domains = <&pd IMX_SC_R_SDHC_1>;
343 fsl,tuning-start-tap = <20>;
344 fsl,tuning-step= <2>;
345 status = "disabled";
346 };
348 usdhc3: mmc@5b030000 {
349 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
350 interrupt-parent = <&gic>;
351 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
352 reg = <0x5b030000 0x10000>;
353 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
354 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
355 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
356 clock-names = "ipg", "per", "ahb";
357 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
358 assigned-clock-rates = <200000000>;
359 power-domains = <&pd IMX_SC_R_SDHC_2>;
360 status = "disabled";
361 };
363 fec1: ethernet@5b040000 {
364 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
365 reg = <0x5b040000 0x10000>;
366 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
371 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
372 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
373 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
374 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
375 fsl,num-tx-queues=<3>;
376 fsl,num-rx-queues=<3>;
377 power-domains = <&pd IMX_SC_R_ENET_0>;
378 status = "disabled";
379 };
381 fec2: ethernet@5b050000 {
382 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
383 reg = <0x5b050000 0x10000>;
384 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
389 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
390 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
391 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
392 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
393 fsl,num-tx-queues=<3>;
394 fsl,num-rx-queues=<3>;
395 power-domains = <&pd IMX_SC_R_ENET_1>;
396 status = "disabled";
397 };
398 };
400 ddr_subsyss: bus@5c000000 {
401 compatible = "simple-bus";
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
406 ddr-pmu@5c020000 {
407 compatible = "fsl,imx8-ddr-pmu";
408 reg = <0x5c020000 0x10000>;
409 interrupt-parent = <&gic>;
410 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
411 };
412 };
414 lsio_subsys: bus@5d000000 {
415 compatible = "simple-bus";
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
420 lsio_gpio0: gpio@5d080000 {
421 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
422 reg = <0x5d080000 0x10000>;
423 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
428 power-domains = <&pd IMX_SC_R_GPIO_0>;
429 };
431 lsio_gpio1: gpio@5d090000 {
432 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
433 reg = <0x5d090000 0x10000>;
434 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 power-domains = <&pd IMX_SC_R_GPIO_1>;
440 };
442 lsio_gpio2: gpio@5d0a0000 {
443 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
444 reg = <0x5d0a0000 0x10000>;
445 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 power-domains = <&pd IMX_SC_R_GPIO_2>;
451 };
453 lsio_gpio3: gpio@5d0b0000 {
454 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
455 reg = <0x5d0b0000 0x10000>;
456 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 power-domains = <&pd IMX_SC_R_GPIO_3>;
462 };
464 lsio_gpio4: gpio@5d0c0000 {
465 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
466 reg = <0x5d0c0000 0x10000>;
467 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
468 gpio-controller;
469 #gpio-cells = <2>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 power-domains = <&pd IMX_SC_R_GPIO_4>;
473 };
475 lsio_gpio5: gpio@5d0d0000 {
476 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
477 reg = <0x5d0d0000 0x10000>;
478 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 power-domains = <&pd IMX_SC_R_GPIO_5>;
484 };
486 lsio_gpio6: gpio@5d0e0000 {
487 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
488 reg = <0x5d0e0000 0x10000>;
489 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 power-domains = <&pd IMX_SC_R_GPIO_6>;
495 };
497 lsio_gpio7: gpio@5d0f0000 {
498 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
499 reg = <0x5d0f0000 0x10000>;
500 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
501 gpio-controller;
502 #gpio-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 power-domains = <&pd IMX_SC_R_GPIO_7>;
506 };
508 lsio_mu0: mailbox@5d1b0000 {
509 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
510 reg = <0x5d1b0000 0x10000>;
511 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
512 #mbox-cells = <2>;
513 status = "disabled";
514 };
516 lsio_mu1: mailbox@5d1c0000 {
517 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
518 reg = <0x5d1c0000 0x10000>;
519 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
520 #mbox-cells = <2>;
521 };
523 lsio_mu2: mailbox@5d1d0000 {
524 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
525 reg = <0x5d1d0000 0x10000>;
526 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
527 #mbox-cells = <2>;
528 status = "disabled";
529 };
531 lsio_mu3: mailbox@5d1e0000 {
532 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
533 reg = <0x5d1e0000 0x10000>;
534 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
535 #mbox-cells = <2>;
536 status = "disabled";
537 };
539 lsio_mu4: mailbox@5d1f0000 {
540 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
541 reg = <0x5d1f0000 0x10000>;
542 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
543 #mbox-cells = <2>;
544 status = "disabled";
545 };
547 lsio_mu13: mailbox@5d280000 {
548 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
549 reg = <0x5d280000 0x10000>;
550 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
551 #mbox-cells = <2>;
552 power-domains = <&pd IMX_SC_R_MU_13A>;
553 };
555 lsio_lpcg: clock-controller@5d400000 {
556 compatible = "fsl,imx8qxp-lpcg-lsio";
557 reg = <0x5d400000 0x400000>;
558 #clock-cells = <1>;
559 };
560 };
561 };