1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
5 * Copyright (C) 2017 Hisilicon Ltd.
7 * Author: Pengcheng Li <lipengcheng8@huawei.com>
8 * Leo Yan <leo.yan@linaro.org>
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
15 reg = <0 0xf6401000 0 0x1000>;
16 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
17 clock-names = "apb_pclk";
21 soc_funnel_out: endpoint {
30 soc_funnel_in: endpoint {
39 compatible = "arm,coresight-tmc", "arm,primecell";
40 reg = <0 0xf6402000 0 0x1000>;
41 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
42 clock-names = "apb_pclk";
64 compatible = "arm,coresight-static-replicator";
65 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
66 clock-names = "apb_pclk";
70 replicator_in: endpoint {
83 replicator_out0: endpoint {
91 replicator_out1: endpoint {
100 compatible = "arm,coresight-tmc", "arm,primecell";
101 reg = <0 0xf6404000 0 0x1000>;
102 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
103 clock-names = "apb_pclk";
116 compatible = "arm,coresight-tpiu", "arm,primecell";
117 reg = <0 0xf6405000 0 0x1000>;
118 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
119 clock-names = "apb_pclk";
132 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
133 reg = <0 0xf6501000 0 0x1000>;
134 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
135 clock-names = "apb_pclk";
139 acpu_funnel_out: endpoint {
147 #address-cells = <1>;
152 acpu_funnel_in0: endpoint {
160 acpu_funnel_in1: endpoint {
168 acpu_funnel_in2: endpoint {
176 acpu_funnel_in3: endpoint {
184 acpu_funnel_in4: endpoint {
192 acpu_funnel_in5: endpoint {
200 acpu_funnel_in6: endpoint {
208 acpu_funnel_in7: endpoint {
217 compatible = "arm,coresight-etm4x", "arm,primecell";
218 reg = <0 0xf659c000 0 0x1000>;
220 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
221 clock-names = "apb_pclk";
236 compatible = "arm,coresight-etm4x", "arm,primecell";
237 reg = <0 0xf659d000 0 0x1000>;
239 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
240 clock-names = "apb_pclk";
255 compatible = "arm,coresight-etm4x", "arm,primecell";
256 reg = <0 0xf659e000 0 0x1000>;
258 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
259 clock-names = "apb_pclk";
274 compatible = "arm,coresight-etm4x", "arm,primecell";
275 reg = <0 0xf659f000 0 0x1000>;
277 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
278 clock-names = "apb_pclk";
293 compatible = "arm,coresight-etm4x", "arm,primecell";
294 reg = <0 0xf65dc000 0 0x1000>;
296 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
297 clock-names = "apb_pclk";
312 compatible = "arm,coresight-etm4x", "arm,primecell";
313 reg = <0 0xf65dd000 0 0x1000>;
315 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
316 clock-names = "apb_pclk";
331 compatible = "arm,coresight-etm4x", "arm,primecell";
332 reg = <0 0xf65de000 0 0x1000>;
334 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
335 clock-names = "apb_pclk";
350 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0 0xf65df000 0 0x1000>;
353 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
354 clock-names = "apb_pclk";