| blob | f43c43168b002560435e029dda89ea9013fca55d |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 */
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 / {
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
28 ranges;
30 /*
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
33 */
34 psci-area@4000000 {
35 reg = <0 0x4000000 0 0x200000>;
36 no-map;
37 };
38 };
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a53";
46 reg = <0>;
47 clocks = <&nb_periph_clk 16>;
48 enable-method = "psci";
49 };
50 };
52 psci {
53 compatible = "arm,psci-0.2";
54 method = "smc";
55 };
57 timer {
58 compatible = "arm,armv8-timer";
59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
63 };
65 pmu {
66 compatible = "arm,armv8-pmuv3";
67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68 };
70 soc {
71 compatible = "simple-bus";
72 #address-cells = <2>;
73 #size-cells = <2>;
74 ranges;
76 internal-regs@d0000000 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
83 wdt: watchdog@8300 {
84 compatible = "marvell,armada-3700-wdt";
85 reg = <0x8300 0x40>;
86 marvell,system-controller = <&cpu_misc>;
87 clocks = <&xtalclk>;
88 };
90 cpu_misc: system-controller@d000 {
91 compatible = "marvell,armada-3700-cpu-misc",
92 "syscon";
93 reg = <0xd000 0x1000>;
94 };
96 spi0: spi@10600 {
97 compatible = "marvell,armada-3700-spi";
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <0x10600 0xA00>;
101 clocks = <&nb_periph_clk 7>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
103 num-cs = <4>;
104 status = "disabled";
105 };
107 i2c0: i2c@11000 {
108 compatible = "marvell,armada-3700-i2c";
109 reg = <0x11000 0x24>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 clocks = <&nb_periph_clk 10>;
113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
114 mrvl,i2c-fast-mode;
115 status = "disabled";
116 };
118 i2c1: i2c@11080 {
119 compatible = "marvell,armada-3700-i2c";
120 reg = <0x11080 0x24>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 clocks = <&nb_periph_clk 9>;
124 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
125 mrvl,i2c-fast-mode;
126 status = "disabled";
127 };
129 avs: avs@11500 {
130 compatible = "marvell,armada-3700-avs",
131 "syscon";
132 reg = <0x11500 0x40>;
133 };
135 uart0: serial@12000 {
136 compatible = "marvell,armada-3700-uart";
137 reg = <0x12000 0x200>;
138 clocks = <&xtalclk>;
139 interrupts =
140 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
144 status = "disabled";
145 };
147 uart1: serial@12200 {
148 compatible = "marvell,armada-3700-uart-ext";
149 reg = <0x12200 0x30>;
150 clocks = <&xtalclk>;
151 interrupts =
152 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
153 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
154 interrupt-names = "uart-tx", "uart-rx";
155 status = "disabled";
156 };
158 nb_periph_clk: nb-periph-clk@13000 {
159 compatible = "marvell,armada-3700-periph-clock-nb";
160 reg = <0x13000 0x100>;
161 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
162 <&tbg 3>, <&xtalclk>;
163 #clock-cells = <1>;
164 };
166 sb_periph_clk: sb-periph-clk@18000 {
167 compatible = "marvell,armada-3700-periph-clock-sb";
168 reg = <0x18000 0x100>;
169 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
170 <&tbg 3>, <&xtalclk>;
171 #clock-cells = <1>;
172 };
174 tbg: tbg@13200 {
175 compatible = "marvell,armada-3700-tbg-clock";
176 reg = <0x13200 0x100>;
177 clocks = <&xtalclk>;
178 #clock-cells = <1>;
179 };
181 pinctrl_nb: pinctrl@13800 {
182 compatible = "marvell,armada3710-nb-pinctrl",
183 "syscon", "simple-mfd";
184 reg = <0x13800 0x100>, <0x13C00 0x20>;
185 /* MPP1[19:0] */
186 gpionb: gpio {
187 #gpio-cells = <2>;
188 gpio-ranges = <&pinctrl_nb 0 0 36>;
189 gpio-controller;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupts =
193 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
205 };
207 xtalclk: xtal-clk {
208 compatible = "marvell,armada-3700-xtal-clock";
209 clock-output-names = "xtal";
210 #clock-cells = <0>;
211 };
213 spi_quad_pins: spi-quad-pins {
214 groups = "spi_quad";
215 function = "spi";
216 };
218 i2c1_pins: i2c1-pins {
219 groups = "i2c1";
220 function = "i2c";
221 };
223 i2c2_pins: i2c2-pins {
224 groups = "i2c2";
225 function = "i2c";
226 };
228 uart1_pins: uart1-pins {
229 groups = "uart1";
230 function = "uart";
231 };
233 uart2_pins: uart2-pins {
234 groups = "uart2";
235 function = "uart";
236 };
238 mmc_pins: mmc-pins {
239 groups = "emmc_nb";
240 function = "emmc";
241 };
242 };
244 nb_pm: syscon@14000 {
245 compatible = "marvell,armada-3700-nb-pm",
246 "syscon";
247 reg = <0x14000 0x60>;
248 };
250 comphy: phy@18300 {
251 compatible = "marvell,comphy-a3700";
252 reg = <0x18300 0x300>,
253 <0x1F000 0x400>,
254 <0x5C000 0x400>,
255 <0xe0178 0x8>;
256 reg-names = "comphy",
257 "lane1_pcie_gbe",
258 "lane0_usb3_gbe",
259 "lane2_sata_usb3";
260 #address-cells = <1>;
261 #size-cells = <0>;
263 comphy0: phy@0 {
264 reg = <0>;
265 #phy-cells = <1>;
266 };
268 comphy1: phy@1 {
269 reg = <1>;
270 #phy-cells = <1>;
271 };
273 comphy2: phy@2 {
274 reg = <2>;
275 #phy-cells = <1>;
276 };
277 };
279 pinctrl_sb: pinctrl@18800 {
280 compatible = "marvell,armada3710-sb-pinctrl",
281 "syscon", "simple-mfd";
282 reg = <0x18800 0x100>, <0x18C00 0x20>;
283 /* MPP2[23:0] */
284 gpiosb: gpio {
285 #gpio-cells = <2>;
286 gpio-ranges = <&pinctrl_sb 0 0 30>;
287 gpio-controller;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 interrupts =
291 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
296 };
298 rgmii_pins: mii-pins {
299 groups = "rgmii";
300 function = "mii";
301 };
303 smi_pins: smi-pins {
304 groups = "smi";
305 function = "smi";
306 };
308 sdio_pins: sdio-pins {
309 groups = "sdio_sb";
310 function = "sdio";
311 };
313 pcie_reset_pins: pcie-reset-pins {
314 groups = "pcie1";
315 function = "pcie";
316 };
318 pcie_clkreq_pins: pcie-clkreq-pins {
319 groups = "pcie1_clkreq";
320 function = "pcie";
321 };
322 };
324 eth0: ethernet@30000 {
325 compatible = "marvell,armada-3700-neta";
326 reg = <0x30000 0x4000>;
327 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&sb_periph_clk 8>;
329 status = "disabled";
330 };
332 mdio: mdio@32004 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 compatible = "marvell,orion-mdio";
336 reg = <0x32004 0x4>;
337 };
339 eth1: ethernet@40000 {
340 compatible = "marvell,armada-3700-neta";
341 reg = <0x40000 0x4000>;
342 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&sb_periph_clk 7>;
344 status = "disabled";
345 };
347 usb3: usb@58000 {
348 compatible = "marvell,armada3700-xhci",
349 "generic-xhci";
350 reg = <0x58000 0x4000>;
351 marvell,usb-misc-reg = <&usb32_syscon>;
352 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&sb_periph_clk 12>;
354 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
355 phy-names = "usb3-phy", "usb2-utmi-otg-phy";
356 status = "disabled";
357 };
359 usb2_utmi_otg_phy: phy@5d000 {
360 compatible = "marvell,a3700-utmi-otg-phy";
361 reg = <0x5d000 0x800>;
362 marvell,usb-misc-reg = <&usb32_syscon>;
363 #phy-cells = <0>;
364 };
366 usb32_syscon: system-controller@5d800 {
367 compatible = "marvell,armada-3700-usb2-host-device-misc",
368 "syscon";
369 reg = <0x5d800 0x800>;
370 };
372 usb2: usb@5e000 {
373 compatible = "marvell,armada-3700-ehci";
374 reg = <0x5e000 0x1000>;
375 marvell,usb-misc-reg = <&usb2_syscon>;
376 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
377 phys = <&usb2_utmi_host_phy>;
378 phy-names = "usb2-utmi-host-phy";
379 status = "disabled";
380 };
382 usb2_utmi_host_phy: phy@5f000 {
383 compatible = "marvell,a3700-utmi-host-phy";
384 reg = <0x5f000 0x800>;
385 marvell,usb-misc-reg = <&usb2_syscon>;
386 #phy-cells = <0>;
387 };
389 usb2_syscon: system-controller@5f800 {
390 compatible = "marvell,armada-3700-usb2-host-misc",
391 "syscon";
392 reg = <0x5f800 0x800>;
393 };
395 xor@60900 {
396 compatible = "marvell,armada-3700-xor";
397 reg = <0x60900 0x100>,
398 <0x60b00 0x100>;
400 xor10 {
401 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
402 };
403 xor11 {
404 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
405 };
406 };
408 crypto: crypto@90000 {
409 compatible = "inside-secure,safexcel-eip97ies";
410 reg = <0x90000 0x20000>;
411 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "mem", "ring0", "ring1",
418 "ring2", "ring3", "eip";
419 clocks = <&nb_periph_clk 15>;
420 };
422 sdhci1: sdhci@d0000 {
423 compatible = "marvell,armada-3700-sdhci",
424 "marvell,sdhci-xenon";
425 reg = <0xd0000 0x300>,
426 <0x1e808 0x4>;
427 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&nb_periph_clk 0>;
429 clock-names = "core";
430 status = "disabled";
431 };
433 sdhci0: sdhci@d8000 {
434 compatible = "marvell,armada-3700-sdhci",
435 "marvell,sdhci-xenon";
436 reg = <0xd8000 0x300>,
437 <0x17808 0x4>;
438 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&nb_periph_clk 0>;
440 clock-names = "core";
441 status = "disabled";
442 };
444 sata: sata@e0000 {
445 compatible = "marvell,armada-3700-ahci";
446 reg = <0xe0000 0x178>;
447 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&nb_periph_clk 1>;
449 status = "disabled";
450 };
452 gic: interrupt-controller@1d00000 {
453 compatible = "arm,gic-v3";
454 #interrupt-cells = <3>;
455 interrupt-controller;
456 reg = <0x1d00000 0x10000>, /* GICD */
457 <0x1d40000 0x40000>, /* GICR */
458 <0x1d80000 0x2000>, /* GICC */
459 <0x1d90000 0x2000>, /* GICH */
460 <0x1da0000 0x20000>; /* GICV */
461 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
462 };
463 };
465 pcie0: pcie@d0070000 {
466 compatible = "marvell,armada-3700-pcie";
467 device_type = "pci";
468 status = "disabled";
469 reg = <0 0xd0070000 0 0x20000>;
470 #address-cells = <3>;
471 #size-cells = <2>;
472 bus-range = <0x00 0xff>;
473 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
474 #interrupt-cells = <1>;
475 msi-parent = <&pcie0>;
476 msi-controller;
477 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
478 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
479 interrupt-map-mask = <0 0 0 7>;
480 interrupt-map = <0 0 0 1 &pcie_intc 0>,
481 <0 0 0 2 &pcie_intc 1>,
482 <0 0 0 3 &pcie_intc 2>,
483 <0 0 0 4 &pcie_intc 3>;
484 pcie_intc: interrupt-controller {
485 interrupt-controller;
486 #interrupt-cells = <1>;
487 };
488 };
489 };
490 };