1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP110.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
14 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
15 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
19 * The contents of the node are defined below, in order to
20 * save one indentation level
22 CP110_NAME: CP110_NAME { };
25 * CPs only have one sensor in the thermal IC.
27 * The cooling maps are empty as there are no cooling devices.
30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
31 polling-delay-passive = <0>; /* Interrupt driven */
32 polling-delay = <0>; /* Interrupt driven */
34 thermal-sensors = <&CP110_LABEL(thermal) 0>;
37 CP110_LABEL(crit): crit {
38 temperature = <100000>; /* mC degrees */
39 hysteresis = <2000>; /* mC degrees */
52 compatible = "simple-bus";
53 interrupt-parent = <&CP110_LABEL(icu_nsr)>;
56 config-space@CP110_BASE {
59 compatible = "simple-bus";
60 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
62 CP110_LABEL(ethernet): ethernet@0 {
63 compatible = "marvell,armada-7k-pp22";
64 reg = <0x0 0x100000>, <0x129000 0xb000>;
65 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
66 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
67 <&CP110_LABEL(clk) 1 18>;
68 clock-names = "pp_clk", "gop_clk",
69 "mg_clk", "mg_core_clk", "axi_clk";
70 marvell,system-controller = <&CP110_LABEL(syscon0)>;
74 CP110_LABEL(eth0): eth0 {
75 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
76 <43 IRQ_TYPE_LEVEL_HIGH>,
77 <47 IRQ_TYPE_LEVEL_HIGH>,
78 <51 IRQ_TYPE_LEVEL_HIGH>,
79 <55 IRQ_TYPE_LEVEL_HIGH>,
80 <59 IRQ_TYPE_LEVEL_HIGH>,
81 <63 IRQ_TYPE_LEVEL_HIGH>,
82 <67 IRQ_TYPE_LEVEL_HIGH>,
83 <71 IRQ_TYPE_LEVEL_HIGH>,
84 <129 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-names = "hif0", "hif1", "hif2",
86 "hif3", "hif4", "hif5", "hif6", "hif7",
93 CP110_LABEL(eth1): eth1 {
94 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
95 <44 IRQ_TYPE_LEVEL_HIGH>,
96 <48 IRQ_TYPE_LEVEL_HIGH>,
97 <52 IRQ_TYPE_LEVEL_HIGH>,
98 <56 IRQ_TYPE_LEVEL_HIGH>,
99 <60 IRQ_TYPE_LEVEL_HIGH>,
100 <64 IRQ_TYPE_LEVEL_HIGH>,
101 <68 IRQ_TYPE_LEVEL_HIGH>,
102 <72 IRQ_TYPE_LEVEL_HIGH>,
103 <128 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-names = "hif0", "hif1", "hif2",
105 "hif3", "hif4", "hif5", "hif6", "hif7",
112 CP110_LABEL(eth2): eth2 {
113 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
114 <45 IRQ_TYPE_LEVEL_HIGH>,
115 <49 IRQ_TYPE_LEVEL_HIGH>,
116 <53 IRQ_TYPE_LEVEL_HIGH>,
117 <57 IRQ_TYPE_LEVEL_HIGH>,
118 <61 IRQ_TYPE_LEVEL_HIGH>,
119 <65 IRQ_TYPE_LEVEL_HIGH>,
120 <69 IRQ_TYPE_LEVEL_HIGH>,
121 <73 IRQ_TYPE_LEVEL_HIGH>,
122 <127 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-names = "hif0", "hif1", "hif2",
124 "hif3", "hif4", "hif5", "hif6", "hif7",
132 CP110_LABEL(comphy): phy@120000 {
133 compatible = "marvell,comphy-cp110";
134 reg = <0x120000 0x6000>;
135 marvell,system-controller = <&CP110_LABEL(syscon0)>;
136 #address-cells = <1>;
139 CP110_LABEL(comphy0): phy@0 {
144 CP110_LABEL(comphy1): phy@1 {
149 CP110_LABEL(comphy2): phy@2 {
154 CP110_LABEL(comphy3): phy@3 {
159 CP110_LABEL(comphy4): phy@4 {
164 CP110_LABEL(comphy5): phy@5 {
170 CP110_LABEL(mdio): mdio@12a200 {
171 #address-cells = <1>;
173 compatible = "marvell,orion-mdio";
174 reg = <0x12a200 0x10>;
175 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
176 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
180 CP110_LABEL(xmdio): mdio@12a600 {
181 #address-cells = <1>;
183 compatible = "marvell,xmdio";
184 reg = <0x12a600 0x10>;
185 clocks = <&CP110_LABEL(clk) 1 5>,
186 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
190 CP110_LABEL(icu): interrupt-controller@1e0000 {
191 compatible = "marvell,cp110-icu";
192 reg = <0x1e0000 0x440>;
193 #address-cells = <1>;
196 CP110_LABEL(icu_nsr): interrupt-controller@10 {
197 compatible = "marvell,cp110-icu-nsr";
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 msi-parent = <&gicp>;
204 CP110_LABEL(icu_sei): interrupt-controller@50 {
205 compatible = "marvell,cp110-icu-sei";
207 #interrupt-cells = <2>;
208 interrupt-controller;
213 CP110_LABEL(rtc): rtc@284000 {
214 compatible = "marvell,armada-8k-rtc";
215 reg = <0x284000 0x20>, <0x284080 0x24>;
216 reg-names = "rtc", "rtc-soc";
217 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
220 CP110_LABEL(syscon0): system-controller@440000 {
221 compatible = "syscon", "simple-mfd";
222 reg = <0x440000 0x2000>;
224 CP110_LABEL(clk): clock {
225 compatible = "marvell,cp110-clock";
229 CP110_LABEL(gpio1): gpio@100 {
230 compatible = "marvell,armada-8k-gpio";
235 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
236 interrupt-controller;
237 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
238 <85 IRQ_TYPE_LEVEL_HIGH>,
239 <84 IRQ_TYPE_LEVEL_HIGH>,
240 <83 IRQ_TYPE_LEVEL_HIGH>;
241 #interrupt-cells = <2>;
245 CP110_LABEL(gpio2): gpio@140 {
246 compatible = "marvell,armada-8k-gpio";
251 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
252 interrupt-controller;
253 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
254 <81 IRQ_TYPE_LEVEL_HIGH>,
255 <80 IRQ_TYPE_LEVEL_HIGH>,
256 <79 IRQ_TYPE_LEVEL_HIGH>;
257 #interrupt-cells = <2>;
262 CP110_LABEL(syscon1): system-controller@400000 {
263 compatible = "syscon", "simple-mfd";
264 reg = <0x400000 0x1000>;
265 #address-cells = <1>;
268 CP110_LABEL(thermal): thermal-sensor@70 {
269 compatible = "marvell,armada-cp110-thermal";
271 interrupts-extended =
272 <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
273 #thermal-sensor-cells = <1>;
277 CP110_LABEL(usb3_0): usb3@500000 {
278 compatible = "marvell,armada-8k-xhci",
280 reg = <0x500000 0x4000>;
282 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
283 clock-names = "core", "reg";
284 clocks = <&CP110_LABEL(clk) 1 22>,
285 <&CP110_LABEL(clk) 1 16>;
289 CP110_LABEL(usb3_1): usb3@510000 {
290 compatible = "marvell,armada-8k-xhci",
292 reg = <0x510000 0x4000>;
294 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
295 clock-names = "core", "reg";
296 clocks = <&CP110_LABEL(clk) 1 23>,
297 <&CP110_LABEL(clk) 1 16>;
301 CP110_LABEL(sata0): sata@540000 {
302 compatible = "marvell,armada-8k-ahci",
304 reg = <0x540000 0x30000>;
306 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&CP110_LABEL(clk) 1 15>,
308 <&CP110_LABEL(clk) 1 16>;
312 CP110_LABEL(xor0): xor@6a0000 {
313 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
314 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
316 msi-parent = <&gic_v2m0>;
317 clock-names = "core", "reg";
318 clocks = <&CP110_LABEL(clk) 1 8>,
319 <&CP110_LABEL(clk) 1 14>;
322 CP110_LABEL(xor1): xor@6c0000 {
323 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
324 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
326 msi-parent = <&gic_v2m0>;
327 clock-names = "core", "reg";
328 clocks = <&CP110_LABEL(clk) 1 7>,
329 <&CP110_LABEL(clk) 1 14>;
332 CP110_LABEL(spi0): spi@700600 {
333 compatible = "marvell,armada-380-spi";
334 reg = <0x700600 0x50>;
335 #address-cells = <0x1>;
337 clock-names = "core", "axi";
338 clocks = <&CP110_LABEL(clk) 1 21>,
339 <&CP110_LABEL(clk) 1 17>;
343 CP110_LABEL(spi1): spi@700680 {
344 compatible = "marvell,armada-380-spi";
345 reg = <0x700680 0x50>;
346 #address-cells = <1>;
348 clock-names = "core", "axi";
349 clocks = <&CP110_LABEL(clk) 1 21>,
350 <&CP110_LABEL(clk) 1 17>;
354 CP110_LABEL(i2c0): i2c@701000 {
355 compatible = "marvell,mv78230-i2c";
356 reg = <0x701000 0x20>;
357 #address-cells = <1>;
359 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
360 clock-names = "core", "reg";
361 clocks = <&CP110_LABEL(clk) 1 21>,
362 <&CP110_LABEL(clk) 1 17>;
366 CP110_LABEL(i2c1): i2c@701100 {
367 compatible = "marvell,mv78230-i2c";
368 reg = <0x701100 0x20>;
369 #address-cells = <1>;
371 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
372 clock-names = "core", "reg";
373 clocks = <&CP110_LABEL(clk) 1 21>,
374 <&CP110_LABEL(clk) 1 17>;
378 CP110_LABEL(uart0): serial@702000 {
379 compatible = "snps,dw-apb-uart";
380 reg = <0x702000 0x100>;
382 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
384 clock-names = "baudclk", "apb_pclk";
385 clocks = <&CP110_LABEL(clk) 1 21>,
386 <&CP110_LABEL(clk) 1 17>;
390 CP110_LABEL(uart1): serial@702100 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x702100 0x100>;
394 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
396 clock-names = "baudclk", "apb_pclk";
397 clocks = <&CP110_LABEL(clk) 1 21>,
398 <&CP110_LABEL(clk) 1 17>;
402 CP110_LABEL(uart2): serial@702200 {
403 compatible = "snps,dw-apb-uart";
404 reg = <0x702200 0x100>;
406 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
408 clock-names = "baudclk", "apb_pclk";
409 clocks = <&CP110_LABEL(clk) 1 21>,
410 <&CP110_LABEL(clk) 1 17>;
414 CP110_LABEL(uart3): serial@702300 {
415 compatible = "snps,dw-apb-uart";
416 reg = <0x702300 0x100>;
418 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
420 clock-names = "baudclk", "apb_pclk";
421 clocks = <&CP110_LABEL(clk) 1 21>,
422 <&CP110_LABEL(clk) 1 17>;
426 CP110_LABEL(nand_controller): nand@720000 {
428 * Due to the limitation of the pins available
429 * this controller is only usable on the CPM
430 * for A7K and on the CPS for A8K.
432 compatible = "marvell,armada-8k-nand-controller",
433 "marvell,armada370-nand-controller";
434 reg = <0x720000 0x54>;
435 #address-cells = <1>;
437 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
438 clock-names = "core", "reg";
439 clocks = <&CP110_LABEL(clk) 1 2>,
440 <&CP110_LABEL(clk) 1 17>;
441 marvell,system-controller = <&CP110_LABEL(syscon0)>;
445 CP110_LABEL(trng): trng@760000 {
446 compatible = "marvell,armada-8k-rng",
447 "inside-secure,safexcel-eip76";
448 reg = <0x760000 0x7d>;
449 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
450 clock-names = "core", "reg";
451 clocks = <&CP110_LABEL(clk) 1 25>,
452 <&CP110_LABEL(clk) 1 17>;
456 CP110_LABEL(sdhci0): sdhci@780000 {
457 compatible = "marvell,armada-cp110-sdhci";
458 reg = <0x780000 0x300>;
459 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
460 clock-names = "core", "axi";
461 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
466 CP110_LABEL(crypto): crypto@800000 {
467 compatible = "inside-secure,safexcel-eip197b";
468 reg = <0x800000 0x200000>;
469 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
470 <88 IRQ_TYPE_LEVEL_HIGH>,
471 <89 IRQ_TYPE_LEVEL_HIGH>,
472 <90 IRQ_TYPE_LEVEL_HIGH>,
473 <91 IRQ_TYPE_LEVEL_HIGH>,
474 <92 IRQ_TYPE_LEVEL_HIGH>;
475 interrupt-names = "mem", "ring0", "ring1",
476 "ring2", "ring3", "eip";
477 clock-names = "core", "reg";
478 clocks = <&CP110_LABEL(clk) 1 26>,
479 <&CP110_LABEL(clk) 1 17>;
484 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
485 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
486 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
487 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
488 reg-names = "ctrl", "config";
489 #address-cells = <3>;
491 #interrupt-cells = <1>;
494 msi-parent = <&gic_v2m0>;
496 bus-range = <0 0xff>;
499 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
500 /* non-prefetchable memory */
501 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
502 interrupt-map-mask = <0 0 0 0>;
503 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
504 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
506 clock-names = "core", "reg";
507 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
511 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
512 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
513 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
514 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
515 reg-names = "ctrl", "config";
516 #address-cells = <3>;
518 #interrupt-cells = <1>;
521 msi-parent = <&gic_v2m0>;
523 bus-range = <0 0xff>;
526 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
527 /* non-prefetchable memory */
528 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
529 interrupt-map-mask = <0 0 0 0>;
530 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
531 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
534 clock-names = "core", "reg";
535 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
539 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
540 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
541 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
542 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
543 reg-names = "ctrl", "config";
544 #address-cells = <3>;
546 #interrupt-cells = <1>;
549 msi-parent = <&gic_v2m0>;
551 bus-range = <0 0xff>;
554 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
555 /* non-prefetchable memory */
556 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
557 interrupt-map-mask = <0 0 0 0>;
558 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
559 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
562 clock-names = "core", "reg";
563 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;