arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43                 poll-interval = <100>;
  44
  45                 factory {
  46                         label = "factory";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&pio 0 0>;
  49                 };
  50
  51                 wps {
  52                         label = "wps";
  53                         linux,code = <KEY_WPS_BUTTON>;
  54                         gpios = <&pio 102 0>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0 0x40000000 0 0x20000000>;
  60         };
  61
  62         reg_1p8v: regulator-1p8v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "fixed-1.8V";
  65                 regulator-min-microvolt = <1800000>;
  66                 regulator-max-microvolt = <1800000>;
  67                 regulator-always-on;
  68         };
  69
  70         reg_3p3v: regulator-3p3v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "fixed-3.3V";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-boot-on;
  76                 regulator-always-on;
  77         };
  78
  79         reg_5v: regulator-5v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "fixed-5V";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 regulator-boot-on;
  85                 regulator-always-on;
  86         };
  87 };
  88
  89 &bch {
  90         status = "disabled";
  91 };
  92
  93 &btif {
  94         status = "okay";
  95 };
  96
  97 &cir {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&irrx_pins>;
 100         status = "okay";
 101 };
 102
 103 &eth {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&eth_pins>;
 106         status = "okay";
 107
 108         gmac1: mac@1 {
 109                 compatible = "mediatek,eth-mac";
 110                 reg = <1>;
 111                 phy-handle = <&phy5>;
 112         };
 113
 114         mdio-bus {
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117
 118                 phy5: ethernet-phy@5 {
 119                         reg = <5>;
 120                         phy-mode = "sgmii";
 121                 };
 122         };
 123 };
 124
 125 &i2c1 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&i2c1_pins>;
 128         status = "okay";
 129 };
 130
 131 &i2c2 {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&i2c2_pins>;
 134         status = "okay";
 135 };
 136
 137 &mmc0 {
 138         pinctrl-names = "default", "state_uhs";
 139         pinctrl-0 = <&emmc_pins_default>;
 140         pinctrl-1 = <&emmc_pins_uhs>;
 141         status = "okay";
 142         bus-width = <8>;
 143         max-frequency = <50000000>;
 144         cap-mmc-highspeed;
 145         mmc-hs200-1_8v;
 146         vmmc-supply = <&reg_3p3v>;
 147         vqmmc-supply = <&reg_1p8v>;
 148         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 149         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 150         non-removable;
 151 };
 152
 153 &mmc1 {
 154         pinctrl-names = "default", "state_uhs";
 155         pinctrl-0 = <&sd0_pins_default>;
 156         pinctrl-1 = <&sd0_pins_uhs>;
 157         status = "okay";
 158         bus-width = <4>;
 159         max-frequency = <50000000>;
 160         cap-sd-highspeed;
 161         r_smpl = <1>;
 162         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 163         vmmc-supply = <&reg_3p3v>;
 164         vqmmc-supply = <&reg_3p3v>;
 165         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 166         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 167 };
 168
 169 &nandc {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&parallel_nand_pins>;
 172         status = "disabled";
 173 };
 174
 175 &nor_flash {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&spi_nor_pins>;
 178         status = "disabled";
 179
 180         flash@0 {
 181                 compatible = "jedec,spi-nor";
 182                 reg = <0>;
 183         };
 184 };
 185
 186 &pcie {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pcie0_pins>;
 189         status = "okay";
 190
 191         pcie@0,0 {
 192                 status = "okay";
 193         };
 194 };
 195
 196 &pio {
 197         /* eMMC is shared pin with parallel NAND */
 198         emmc_pins_default: emmc-pins-default {
 199                 mux {
 200                         function = "emmc", "emmc_rst";
 201                         groups = "emmc";
 202                 };
 203
 204                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 205                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 206                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 207                  */
 208                 conf-cmd-dat {
 209                         pins = "NDL0", "NDL1", "NDL2",
 210                                "NDL3", "NDL4", "NDL5",
 211                                "NDL6", "NDL7", "NRB";
 212                         input-enable;
 213                         bias-pull-up;
 214                 };
 215
 216                 conf-clk {
 217                         pins = "NCLE";
 218                         bias-pull-down;
 219                 };
 220         };
 221
 222         emmc_pins_uhs: emmc-pins-uhs {
 223                 mux {
 224                         function = "emmc";
 225                         groups = "emmc";
 226                 };
 227
 228                 conf-cmd-dat {
 229                         pins = "NDL0", "NDL1", "NDL2",
 230                                "NDL3", "NDL4", "NDL5",
 231                                "NDL6", "NDL7", "NRB";
 232                         input-enable;
 233                         drive-strength = <4>;
 234                         bias-pull-up;
 235                 };
 236
 237                 conf-clk {
 238                         pins = "NCLE";
 239                         drive-strength = <4>;
 240                         bias-pull-down;
 241                 };
 242         };
 243
 244         eth_pins: eth-pins {
 245                 mux {
 246                         function = "eth";
 247                         groups = "mdc_mdio", "rgmii_via_gmac2";
 248                 };
 249         };
 250
 251         i2c1_pins: i2c1-pins {
 252                 mux {
 253                         function = "i2c";
 254                         groups =  "i2c1_0";
 255                 };
 256         };
 257
 258         i2c2_pins: i2c2-pins {
 259                 mux {
 260                         function = "i2c";
 261                         groups =  "i2c2_0";
 262                 };
 263         };
 264
 265         i2s1_pins: i2s1-pins {
 266                 mux {
 267                         function = "i2s";
 268                         groups =  "i2s_out_mclk_bclk_ws",
 269                                   "i2s1_in_data",
 270                                   "i2s1_out_data";
 271                 };
 272
 273                 conf {
 274                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 275                                "I2S_WS", "I2S_MCLK";
 276                         drive-strength = <12>;
 277                         bias-pull-down;
 278                 };
 279         };
 280
 281         irrx_pins: irrx-pins {
 282                 mux {
 283                         function = "ir";
 284                         groups =  "ir_1_rx";
 285                 };
 286         };
 287
 288         irtx_pins: irtx-pins {
 289                 mux {
 290                         function = "ir";
 291                         groups =  "ir_1_tx";
 292                 };
 293         };
 294
 295         /* Parallel nand is shared pin with eMMC */
 296         parallel_nand_pins: parallel-nand-pins {
 297                 mux {
 298                         function = "flash";
 299                         groups = "par_nand";
 300                 };
 301         };
 302
 303         pcie0_pins: pcie0-pins {
 304                 mux {
 305                         function = "pcie";
 306                         groups = "pcie0_pad_perst",
 307                                  "pcie0_1_waken",
 308                                  "pcie0_1_clkreq";
 309                 };
 310         };
 311
 312         pcie1_pins: pcie1-pins {
 313                 mux {
 314                         function = "pcie";
 315                         groups = "pcie1_pad_perst",
 316                                  "pcie1_0_waken",
 317                                  "pcie1_0_clkreq";
 318                 };
 319         };
 320
 321         pmic_bus_pins: pmic-bus-pins {
 322                 mux {
 323                         function = "pmic";
 324                         groups = "pmic_bus";
 325                 };
 326         };
 327
 328         pwm7_pins: pwm1-2-pins {
 329                 mux {
 330                         function = "pwm";
 331                         groups = "pwm_ch7_2";
 332                 };
 333         };
 334
 335         wled_pins: wled-pins {
 336                 mux {
 337                         function = "led";
 338                         groups = "wled";
 339                 };
 340         };
 341
 342         sd0_pins_default: sd0-pins-default {
 343                 mux {
 344                         function = "sd";
 345                         groups = "sd_0";
 346                 };
 347
 348                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 349                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 350                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 351                  */
 352                 conf-cmd-data {
 353                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 354                                "I2S2_IN","I2S4_OUT";
 355                         input-enable;
 356                         drive-strength = <8>;
 357                         bias-pull-up;
 358                 };
 359                 conf-clk {
 360                         pins = "I2S3_OUT";
 361                         drive-strength = <12>;
 362                         bias-pull-down;
 363                 };
 364                 conf-cd {
 365                         pins = "TXD3";
 366                         bias-pull-up;
 367                 };
 368         };
 369
 370         sd0_pins_uhs: sd0-pins-uhs {
 371                 mux {
 372                         function = "sd";
 373                         groups = "sd_0";
 374                 };
 375
 376                 conf-cmd-data {
 377                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 378                                "I2S2_IN","I2S4_OUT";
 379                         input-enable;
 380                         bias-pull-up;
 381                 };
 382
 383                 conf-clk {
 384                         pins = "I2S3_OUT";
 385                         bias-pull-down;
 386                 };
 387         };
 388
 389         /* Serial NAND is shared pin with SPI-NOR */
 390         serial_nand_pins: serial-nand-pins {
 391                 mux {
 392                         function = "flash";
 393                         groups = "snfi";
 394                 };
 395         };
 396
 397         spic0_pins: spic0-pins {
 398                 mux {
 399                         function = "spi";
 400                         groups = "spic0_0";
 401                 };
 402         };
 403
 404         spic1_pins: spic1-pins {
 405                 mux {
 406                         function = "spi";
 407                         groups = "spic1_0";
 408                 };
 409         };
 410
 411         /* SPI-NOR is shared pin with serial NAND */
 412         spi_nor_pins: spi-nor-pins {
 413                 mux {
 414                         function = "flash";
 415                         groups = "spi_nor";
 416                 };
 417         };
 418
 419         /* serial NAND is shared pin with SPI-NOR */
 420         serial_nand_pins: serial-nand-pins {
 421                 mux {
 422                         function = "flash";
 423                         groups = "snfi";
 424                 };
 425         };
 426
 427         uart0_pins: uart0-pins {
 428                 mux {
 429                         function = "uart";
 430                         groups = "uart0_0_tx_rx" ;
 431                 };
 432         };
 433
 434         uart2_pins: uart2-pins {
 435                 mux {
 436                         function = "uart";
 437                         groups = "uart2_1_tx_rx" ;
 438                 };
 439         };
 440
 441         watchdog_pins: watchdog-pins {
 442                 mux {
 443                         function = "watchdog";
 444                         groups = "watchdog";
 445                 };
 446         };
 447 };
 448
 449 &pwm {
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&pwm7_pins>;
 452         status = "okay";
 453 };
 454
 455 &pwrap {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pmic_bus_pins>;
 458
 459         status = "okay";
 460 };
 461
 462 &sata {
 463         status = "okay";
 464 };
 465
 466 &sata_phy {
 467         status = "okay";
 468 };
 469
 470 &spi0 {
 471         pinctrl-names = "default";
 472         pinctrl-0 = <&spic0_pins>;
 473         status = "okay";
 474 };
 475
 476 &spi1 {
 477         pinctrl-names = "default";
 478         pinctrl-0 = <&spic1_pins>;
 479         status = "okay";
 480 };
 481
 482 &ssusb {
 483         vusb33-supply = <&reg_3p3v>;
 484         vbus-supply = <&reg_5v>;
 485         status = "okay";
 486 };
 487
 488 &u3phy {
 489         status = "okay";
 490 };
 491
 492 &uart0 {
 493         pinctrl-names = "default";
 494         pinctrl-0 = <&uart0_pins>;
 495         status = "okay";
 496 };
 497
 498 &uart2 {
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&uart2_pins>;
 501         status = "okay";
 502 };
 503
 504 &watchdog {
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&watchdog_pins>;
 507         status = "okay";
 508 };