| blob | 5ea9fb8f2f87dfc9fcdc2876094579e1f7b5a254 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/thermal/thermal.h>
12 / {
13 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
18 aliases {
19 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
20 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
21 };
23 chosen { };
25 memory {
26 device_type = "memory";
27 /* We expect the bootloader to fill in the reg */
28 reg = <0 0 0 0>;
29 };
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
36 tz-apps@86000000 {
37 reg = <0x0 0x86000000 0x0 0x300000>;
38 no-map;
39 };
41 smem_mem: smem_region@86300000 {
42 reg = <0x0 0x86300000 0x0 0x100000>;
43 no-map;
44 };
46 hypervisor@86400000 {
47 reg = <0x0 0x86400000 0x0 0x100000>;
48 no-map;
49 };
51 tz@86500000 {
52 reg = <0x0 0x86500000 0x0 0x180000>;
53 no-map;
54 };
56 reserved@8668000 {
57 reg = <0x0 0x86680000 0x0 0x80000>;
58 no-map;
59 };
61 rmtfs@86700000 {
62 compatible = "qcom,rmtfs-mem";
63 reg = <0x0 0x86700000 0x0 0xe0000>;
64 no-map;
66 qcom,client-id = <1>;
67 };
69 rfsa@867e00000 {
70 reg = <0x0 0x867e0000 0x0 0x20000>;
71 no-map;
72 };
74 mpss_mem: mpss@86800000 {
75 reg = <0x0 0x86800000 0x0 0x2b00000>;
76 no-map;
77 };
79 wcnss_mem: wcnss@89300000 {
80 reg = <0x0 0x89300000 0x0 0x600000>;
81 no-map;
82 };
84 venus_mem: venus@89900000 {
85 reg = <0x0 0x89900000 0x0 0x600000>;
86 no-map;
87 };
89 mba_mem: mba@8ea00000 {
90 no-map;
91 reg = <0 0x8ea00000 0 0x100000>;
92 };
93 };
95 cpus {
96 #address-cells = <1>;
97 #size-cells = <0>;
99 CPU0: cpu@0 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a53";
102 reg = <0x0>;
103 next-level-cache = <&L2_0>;
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
106 clocks = <&apcs>;
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 };
111 CPU1: cpu@1 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a53";
114 reg = <0x1>;
115 next-level-cache = <&L2_0>;
116 enable-method = "psci";
117 cpu-idle-states = <&CPU_SLEEP_0>;
118 clocks = <&apcs>;
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 };
123 CPU2: cpu@2 {
124 device_type = "cpu";
125 compatible = "arm,cortex-a53";
126 reg = <0x2>;
127 next-level-cache = <&L2_0>;
128 enable-method = "psci";
129 cpu-idle-states = <&CPU_SLEEP_0>;
130 clocks = <&apcs>;
131 operating-points-v2 = <&cpu_opp_table>;
132 #cooling-cells = <2>;
133 };
135 CPU3: cpu@3 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a53";
138 reg = <0x3>;
139 next-level-cache = <&L2_0>;
140 enable-method = "psci";
141 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs>;
143 operating-points-v2 = <&cpu_opp_table>;
144 #cooling-cells = <2>;
145 };
147 L2_0: l2-cache {
148 compatible = "cache";
149 cache-level = <2>;
150 };
152 idle-states {
153 entry-method = "psci";
155 CPU_SLEEP_0: cpu-sleep-0 {
156 compatible = "arm,idle-state";
157 idle-state-name = "standalone-power-collapse";
158 arm,psci-suspend-param = <0x40000002>;
159 entry-latency-us = <130>;
160 exit-latency-us = <150>;
161 min-residency-us = <2000>;
162 local-timer-stop;
163 };
164 };
165 };
167 psci {
168 compatible = "arm,psci-1.0";
169 method = "smc";
170 };
172 pmu {
173 compatible = "arm,cortex-a53-pmu";
174 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
175 };
177 thermal-zones {
178 cpu0_1-thermal {
179 polling-delay-passive = <250>;
180 polling-delay = <1000>;
182 thermal-sensors = <&tsens 4>;
184 trips {
185 cpu0_1_alert0: trip-point@0 {
186 temperature = <75000>;
187 hysteresis = <2000>;
188 type = "passive";
189 };
190 cpu0_1_crit: cpu_crit {
191 temperature = <110000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
197 cooling-maps {
198 map0 {
199 trip = <&cpu0_1_alert0>;
200 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
203 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
204 };
205 };
206 };
208 cpu2_3-thermal {
209 polling-delay-passive = <250>;
210 polling-delay = <1000>;
212 thermal-sensors = <&tsens 3>;
214 trips {
215 cpu2_3_alert0: trip-point@0 {
216 temperature = <75000>;
217 hysteresis = <2000>;
218 type = "passive";
219 };
220 cpu2_3_crit: cpu_crit {
221 temperature = <110000>;
222 hysteresis = <2000>;
223 type = "critical";
224 };
225 };
227 cooling-maps {
228 map0 {
229 trip = <&cpu2_3_alert0>;
230 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 };
235 };
236 };
238 gpu-thermal {
239 polling-delay-passive = <250>;
240 polling-delay = <1000>;
242 thermal-sensors = <&tsens 2>;
244 trips {
245 gpu_alert0: trip-point@0 {
246 temperature = <75000>;
247 hysteresis = <2000>;
248 type = "passive";
249 };
250 gpu_crit: gpu_crit {
251 temperature = <95000>;
252 hysteresis = <2000>;
253 type = "critical";
254 };
255 };
256 };
258 camera-thermal {
259 polling-delay-passive = <250>;
260 polling-delay = <1000>;
262 thermal-sensors = <&tsens 1>;
264 trips {
265 cam_alert0: trip-point@0 {
266 temperature = <75000>;
267 hysteresis = <2000>;
268 type = "hot";
269 };
270 };
271 };
273 modem-thermal {
274 polling-delay-passive = <250>;
275 polling-delay = <1000>;
277 thermal-sensors = <&tsens 0>;
279 trips {
280 modem_alert0: trip-point@0 {
281 temperature = <85000>;
282 hysteresis = <2000>;
283 type = "hot";
284 };
285 };
286 };
288 };
290 cpu_opp_table: cpu_opp_table {
291 compatible = "operating-points-v2";
292 opp-shared;
294 opp-200000000 {
295 opp-hz = /bits/ 64 <200000000>;
296 };
297 opp-400000000 {
298 opp-hz = /bits/ 64 <400000000>;
299 };
300 opp-800000000 {
301 opp-hz = /bits/ 64 <800000000>;
302 };
303 opp-998400000 {
304 opp-hz = /bits/ 64 <998400000>;
305 };
306 };
308 gpu_opp_table: opp_table {
309 compatible = "operating-points-v2";
311 opp-400000000 {
312 opp-hz = /bits/ 64 <400000000>;
313 };
314 opp-19200000 {
315 opp-hz = /bits/ 64 <19200000>;
316 };
317 };
319 timer {
320 compatible = "arm,armv8-timer";
321 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
322 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
323 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
324 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
325 };
327 clocks {
328 xo_board: xo_board {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <19200000>;
332 };
334 sleep_clk: sleep_clk {
335 compatible = "fixed-clock";
336 #clock-cells = <0>;
337 clock-frequency = <32768>;
338 };
339 };
341 smem {
342 compatible = "qcom,smem";
344 memory-region = <&smem_mem>;
345 qcom,rpm-msg-ram = <&rpm_msg_ram>;
347 hwlocks = <&tcsr_mutex 3>;
348 };
350 firmware {
351 scm: scm {
352 compatible = "qcom,scm";
353 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
354 clock-names = "core", "bus", "iface";
355 #reset-cells = <1>;
357 qcom,dload-mode = <&tcsr 0x6100>;
358 };
359 };
361 soc: soc {
362 #address-cells = <1>;
363 #size-cells = <1>;
364 ranges = <0 0 0 0xffffffff>;
365 compatible = "simple-bus";
367 restart@4ab000 {
368 compatible = "qcom,pshold";
369 reg = <0x4ab000 0x4>;
370 };
372 msmgpio: pinctrl@1000000 {
373 compatible = "qcom,msm8916-pinctrl";
374 reg = <0x1000000 0x300000>;
375 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
376 gpio-controller;
377 #gpio-cells = <2>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
380 };
382 gcc: clock-controller@1800000 {
383 compatible = "qcom,gcc-msm8916";
384 #clock-cells = <1>;
385 #reset-cells = <1>;
386 #power-domain-cells = <1>;
387 reg = <0x1800000 0x80000>;
388 };
390 tcsr_mutex_regs: syscon@1905000 {
391 compatible = "syscon";
392 reg = <0x1905000 0x20000>;
393 };
395 tcsr: syscon@1937000 {
396 compatible = "qcom,tcsr-msm8916", "syscon";
397 reg = <0x1937000 0x30000>;
398 };
400 tcsr_mutex: hwlock {
401 compatible = "qcom,tcsr-mutex";
402 syscon = <&tcsr_mutex_regs 0 0x1000>;
403 #hwlock-cells = <1>;
404 };
406 rpm_msg_ram: memory@60000 {
407 compatible = "qcom,rpm-msg-ram";
408 reg = <0x60000 0x8000>;
409 };
411 blsp1_uart1: serial@78af000 {
412 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
413 reg = <0x78af000 0x200>;
414 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
416 clock-names = "core", "iface";
417 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
418 dma-names = "rx", "tx";
419 status = "disabled";
420 };
422 a53pll: clock@b016000 {
423 compatible = "qcom,msm8916-a53pll";
424 reg = <0xb016000 0x40>;
425 #clock-cells = <0>;
426 };
428 apcs: mailbox@b011000 {
429 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
430 reg = <0xb011000 0x1000>;
431 #mbox-cells = <1>;
432 clocks = <&a53pll>;
433 #clock-cells = <0>;
434 };
436 blsp1_uart2: serial@78b0000 {
437 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
438 reg = <0x78b0000 0x200>;
439 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
441 clock-names = "core", "iface";
442 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
443 dma-names = "rx", "tx";
444 status = "disabled";
445 };
447 blsp_dma: dma@7884000 {
448 compatible = "qcom,bam-v1.7.0";
449 reg = <0x07884000 0x23000>;
450 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
452 clock-names = "bam_clk";
453 #dma-cells = <1>;
454 qcom,ee = <0>;
455 status = "disabled";
456 };
458 blsp_spi1: spi@78b5000 {
459 compatible = "qcom,spi-qup-v2.2.1";
460 reg = <0x078b5000 0x500>;
461 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
463 <&gcc GCC_BLSP1_AHB_CLK>;
464 clock-names = "core", "iface";
465 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
466 dma-names = "rx", "tx";
467 pinctrl-names = "default", "sleep";
468 pinctrl-0 = <&spi1_default>;
469 pinctrl-1 = <&spi1_sleep>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
475 blsp_spi2: spi@78b6000 {
476 compatible = "qcom,spi-qup-v2.2.1";
477 reg = <0x078b6000 0x500>;
478 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
480 <&gcc GCC_BLSP1_AHB_CLK>;
481 clock-names = "core", "iface";
482 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
483 dma-names = "rx", "tx";
484 pinctrl-names = "default", "sleep";
485 pinctrl-0 = <&spi2_default>;
486 pinctrl-1 = <&spi2_sleep>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 status = "disabled";
490 };
492 blsp_spi3: spi@78b7000 {
493 compatible = "qcom,spi-qup-v2.2.1";
494 reg = <0x078b7000 0x500>;
495 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
497 <&gcc GCC_BLSP1_AHB_CLK>;
498 clock-names = "core", "iface";
499 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
500 dma-names = "rx", "tx";
501 pinctrl-names = "default", "sleep";
502 pinctrl-0 = <&spi3_default>;
503 pinctrl-1 = <&spi3_sleep>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 status = "disabled";
507 };
509 blsp_spi4: spi@78b8000 {
510 compatible = "qcom,spi-qup-v2.2.1";
511 reg = <0x078b8000 0x500>;
512 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
514 <&gcc GCC_BLSP1_AHB_CLK>;
515 clock-names = "core", "iface";
516 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
517 dma-names = "rx", "tx";
518 pinctrl-names = "default", "sleep";
519 pinctrl-0 = <&spi4_default>;
520 pinctrl-1 = <&spi4_sleep>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
526 blsp_spi5: spi@78b9000 {
527 compatible = "qcom,spi-qup-v2.2.1";
528 reg = <0x078b9000 0x500>;
529 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
531 <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", "iface";
533 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
534 dma-names = "rx", "tx";
535 pinctrl-names = "default", "sleep";
536 pinctrl-0 = <&spi5_default>;
537 pinctrl-1 = <&spi5_sleep>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540 status = "disabled";
541 };
543 blsp_spi6: spi@78ba000 {
544 compatible = "qcom,spi-qup-v2.2.1";
545 reg = <0x078ba000 0x500>;
546 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
550 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
551 dma-names = "rx", "tx";
552 pinctrl-names = "default", "sleep";
553 pinctrl-0 = <&spi6_default>;
554 pinctrl-1 = <&spi6_sleep>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
560 blsp_i2c2: i2c@78b6000 {
561 compatible = "qcom,i2c-qup-v2.2.1";
562 reg = <0x078b6000 0x500>;
563 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
565 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
566 clock-names = "iface", "core";
567 pinctrl-names = "default", "sleep";
568 pinctrl-0 = <&i2c2_default>;
569 pinctrl-1 = <&i2c2_sleep>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573 };
575 blsp_i2c4: i2c@78b8000 {
576 compatible = "qcom,i2c-qup-v2.2.1";
577 reg = <0x078b8000 0x500>;
578 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
580 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
581 clock-names = "iface", "core";
582 pinctrl-names = "default", "sleep";
583 pinctrl-0 = <&i2c4_default>;
584 pinctrl-1 = <&i2c4_sleep>;
585 #address-cells = <1>;
586 #size-cells = <0>;
587 status = "disabled";
588 };
590 blsp_i2c6: i2c@78ba000 {
591 compatible = "qcom,i2c-qup-v2.2.1";
592 reg = <0x078ba000 0x500>;
593 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
595 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
596 clock-names = "iface", "core";
597 pinctrl-names = "default", "sleep";
598 pinctrl-0 = <&i2c6_default>;
599 pinctrl-1 = <&i2c6_sleep>;
600 #address-cells = <1>;
601 #size-cells = <0>;
602 status = "disabled";
603 };
605 lpass: lpass@7708000 {
606 status = "disabled";
607 compatible = "qcom,lpass-cpu-apq8016";
608 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
609 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
610 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
611 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
612 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
613 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
614 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
616 clock-names = "ahbix-clk",
617 "pcnoc-mport-clk",
618 "pcnoc-sway-clk",
619 "mi2s-bit-clk0",
620 "mi2s-bit-clk1",
621 "mi2s-bit-clk2",
622 "mi2s-bit-clk3";
623 #sound-dai-cells = <1>;
625 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-names = "lpass-irq-lpaif";
627 reg = <0x07708000 0x10000>;
628 reg-names = "lpass-lpaif";
629 };
631 lpass_codec: codec{
632 compatible = "qcom,msm8916-wcd-digital-codec";
633 reg = <0x0771c000 0x400>;
634 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
635 <&gcc GCC_CODEC_DIGCODEC_CLK>;
636 clock-names = "ahbix-clk", "mclk";
637 #sound-dai-cells = <1>;
638 };
640 sdhc_1: sdhci@7824000 {
641 compatible = "qcom,sdhci-msm-v4";
642 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
643 reg-names = "hc_mem", "core_mem";
645 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-names = "hc_irq", "pwr_irq";
647 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
648 <&gcc GCC_SDCC1_AHB_CLK>,
649 <&xo_board>;
650 clock-names = "core", "iface", "xo";
651 mmc-ddr-1_8v;
652 bus-width = <8>;
653 non-removable;
654 status = "disabled";
655 };
657 sdhc_2: sdhci@7864000 {
658 compatible = "qcom,sdhci-msm-v4";
659 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
660 reg-names = "hc_mem", "core_mem";
662 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
663 interrupt-names = "hc_irq", "pwr_irq";
664 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
665 <&gcc GCC_SDCC2_AHB_CLK>,
666 <&xo_board>;
667 clock-names = "core", "iface", "xo";
668 bus-width = <4>;
669 status = "disabled";
670 };
672 otg: usb@78d9000 {
673 compatible = "qcom,ci-hdrc";
674 reg = <0x78d9000 0x200>,
675 <0x78d9200 0x200>;
676 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
679 <&gcc GCC_USB_HS_SYSTEM_CLK>;
680 clock-names = "iface", "core";
681 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
682 assigned-clock-rates = <80000000>;
683 resets = <&gcc GCC_USB_HS_BCR>;
684 reset-names = "core";
685 phy_type = "ulpi";
686 dr_mode = "otg";
687 ahb-burst-config = <0>;
688 phy-names = "usb-phy";
689 phys = <&usb_hs_phy>;
690 status = "disabled";
691 #reset-cells = <1>;
693 ulpi {
694 usb_hs_phy: phy {
695 compatible = "qcom,usb-hs-phy-msm8916",
696 "qcom,usb-hs-phy";
697 #phy-cells = <0>;
698 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
699 clock-names = "ref", "sleep";
700 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
701 reset-names = "phy", "por";
702 qcom,init-seq = /bits/ 8 <0x0 0x44
703 0x1 0x6b 0x2 0x24 0x3 0x13>;
704 };
705 };
706 };
708 intc: interrupt-controller@b000000 {
709 compatible = "qcom,msm-qgic2";
710 interrupt-controller;
711 #interrupt-cells = <3>;
712 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
713 };
715 timer@b020000 {
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges;
719 compatible = "arm,armv7-timer-mem";
720 reg = <0xb020000 0x1000>;
721 clock-frequency = <19200000>;
723 frame@b021000 {
724 frame-number = <0>;
725 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
727 reg = <0xb021000 0x1000>,
728 <0xb022000 0x1000>;
729 };
731 frame@b023000 {
732 frame-number = <1>;
733 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
734 reg = <0xb023000 0x1000>;
735 status = "disabled";
736 };
738 frame@b024000 {
739 frame-number = <2>;
740 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
741 reg = <0xb024000 0x1000>;
742 status = "disabled";
743 };
745 frame@b025000 {
746 frame-number = <3>;
747 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
748 reg = <0xb025000 0x1000>;
749 status = "disabled";
750 };
752 frame@b026000 {
753 frame-number = <4>;
754 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
755 reg = <0xb026000 0x1000>;
756 status = "disabled";
757 };
759 frame@b027000 {
760 frame-number = <5>;
761 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
762 reg = <0xb027000 0x1000>;
763 status = "disabled";
764 };
766 frame@b028000 {
767 frame-number = <6>;
768 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
769 reg = <0xb028000 0x1000>;
770 status = "disabled";
771 };
772 };
774 spmi_bus: spmi@200f000 {
775 compatible = "qcom,spmi-pmic-arb";
776 reg = <0x200f000 0x001000>,
777 <0x2400000 0x400000>,
778 <0x2c00000 0x400000>,
779 <0x3800000 0x200000>,
780 <0x200a000 0x002100>;
781 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
782 interrupt-names = "periph_irq";
783 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
784 qcom,ee = <0>;
785 qcom,channel = <0>;
786 #address-cells = <2>;
787 #size-cells = <0>;
788 interrupt-controller;
789 #interrupt-cells = <4>;
790 };
792 rng@22000 {
793 compatible = "qcom,prng";
794 reg = <0x00022000 0x200>;
795 clocks = <&gcc GCC_PRNG_AHB_CLK>;
796 clock-names = "core";
797 };
799 qfprom: qfprom@5c000 {
800 compatible = "qcom,qfprom";
801 reg = <0x5c000 0x1000>;
802 #address-cells = <1>;
803 #size-cells = <1>;
804 tsens_caldata: caldata@d0 {
805 reg = <0xd0 0x8>;
806 };
807 tsens_calsel: calsel@ec {
808 reg = <0xec 0x4>;
809 };
810 };
812 tsens: thermal-sensor@4a9000 {
813 compatible = "qcom,msm8916-tsens";
814 reg = <0x4a9000 0x1000>, /* TM */
815 <0x4a8000 0x1000>; /* SROT */
816 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
817 nvmem-cell-names = "calib", "calib_sel";
818 #qcom,sensors = <5>;
819 #thermal-sensor-cells = <1>;
820 };
822 apps_iommu: iommu@1ef0000 {
823 #address-cells = <1>;
824 #size-cells = <1>;
825 #iommu-cells = <1>;
826 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
827 ranges = <0 0x1e20000 0x40000>;
828 reg = <0x1ef0000 0x3000>;
829 clocks = <&gcc GCC_SMMU_CFG_CLK>,
830 <&gcc GCC_APSS_TCU_CLK>;
831 clock-names = "iface", "bus";
832 qcom,iommu-secure-id = <17>;
834 // vfe:
835 iommu-ctx@3000 {
836 compatible = "qcom,msm-iommu-v1-sec";
837 reg = <0x3000 0x1000>;
838 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
839 };
841 // mdp_0:
842 iommu-ctx@4000 {
843 compatible = "qcom,msm-iommu-v1-ns";
844 reg = <0x4000 0x1000>;
845 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
846 };
848 // venus_ns:
849 iommu-ctx@5000 {
850 compatible = "qcom,msm-iommu-v1-sec";
851 reg = <0x5000 0x1000>;
852 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
853 };
854 };
856 gpu_iommu: iommu@1f08000 {
857 #address-cells = <1>;
858 #size-cells = <1>;
859 #iommu-cells = <1>;
860 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
861 ranges = <0 0x1f08000 0x10000>;
862 clocks = <&gcc GCC_SMMU_CFG_CLK>,
863 <&gcc GCC_GFX_TCU_CLK>;
864 clock-names = "iface", "bus";
865 qcom,iommu-secure-id = <18>;
867 // gfx3d_user:
868 iommu-ctx@1000 {
869 compatible = "qcom,msm-iommu-v1-ns";
870 reg = <0x1000 0x1000>;
871 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
872 };
874 // gfx3d_priv:
875 iommu-ctx@2000 {
876 compatible = "qcom,msm-iommu-v1-ns";
877 reg = <0x2000 0x1000>;
878 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
879 };
880 };
882 gpu@1c00000 {
883 compatible = "qcom,adreno-306.0", "qcom,adreno";
884 reg = <0x01c00000 0x20000>;
885 reg-names = "kgsl_3d0_reg_memory";
886 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-names = "kgsl_3d0_irq";
888 clock-names =
889 "core",
890 "iface",
891 "mem",
892 "mem_iface",
893 "alt_mem_iface",
894 "gfx3d";
895 clocks =
896 <&gcc GCC_OXILI_GFX3D_CLK>,
897 <&gcc GCC_OXILI_AHB_CLK>,
898 <&gcc GCC_OXILI_GMEM_CLK>,
899 <&gcc GCC_BIMC_GFX_CLK>,
900 <&gcc GCC_BIMC_GPU_CLK>,
901 <&gcc GFX3D_CLK_SRC>;
902 power-domains = <&gcc OXILI_GDSC>;
903 operating-points-v2 = <&gpu_opp_table>;
904 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
905 };
907 mdss: mdss@1a00000 {
908 compatible = "qcom,mdss";
909 reg = <0x1a00000 0x1000>,
910 <0x1ac8000 0x3000>;
911 reg-names = "mdss_phys", "vbif_phys";
913 power-domains = <&gcc MDSS_GDSC>;
915 clocks = <&gcc GCC_MDSS_AHB_CLK>,
916 <&gcc GCC_MDSS_AXI_CLK>,
917 <&gcc GCC_MDSS_VSYNC_CLK>;
918 clock-names = "iface",
919 "bus",
920 "vsync";
922 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
924 interrupt-controller;
925 #interrupt-cells = <1>;
927 #address-cells = <1>;
928 #size-cells = <1>;
929 ranges;
931 mdp: mdp@1a01000 {
932 compatible = "qcom,mdp5";
933 reg = <0x1a01000 0x89000>;
934 reg-names = "mdp_phys";
936 interrupt-parent = <&mdss>;
937 interrupts = <0 0>;
939 clocks = <&gcc GCC_MDSS_AHB_CLK>,
940 <&gcc GCC_MDSS_AXI_CLK>,
941 <&gcc GCC_MDSS_MDP_CLK>,
942 <&gcc GCC_MDSS_VSYNC_CLK>;
943 clock-names = "iface",
944 "bus",
945 "core",
946 "vsync";
948 iommus = <&apps_iommu 4>;
950 ports {
951 #address-cells = <1>;
952 #size-cells = <0>;
954 port@0 {
955 reg = <0>;
956 mdp5_intf1_out: endpoint {
957 remote-endpoint = <&dsi0_in>;
958 };
959 };
960 };
961 };
963 dsi0: dsi@1a98000 {
964 compatible = "qcom,mdss-dsi-ctrl";
965 reg = <0x1a98000 0x25c>;
966 reg-names = "dsi_ctrl";
968 interrupt-parent = <&mdss>;
969 interrupts = <4 0>;
971 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
972 <&gcc PCLK0_CLK_SRC>;
973 assigned-clock-parents = <&dsi_phy0 0>,
974 <&dsi_phy0 1>;
976 clocks = <&gcc GCC_MDSS_MDP_CLK>,
977 <&gcc GCC_MDSS_AHB_CLK>,
978 <&gcc GCC_MDSS_AXI_CLK>,
979 <&gcc GCC_MDSS_BYTE0_CLK>,
980 <&gcc GCC_MDSS_PCLK0_CLK>,
981 <&gcc GCC_MDSS_ESC0_CLK>;
982 clock-names = "mdp_core",
983 "iface",
984 "bus",
985 "byte",
986 "pixel",
987 "core";
988 phys = <&dsi_phy0>;
989 phy-names = "dsi-phy";
991 ports {
992 #address-cells = <1>;
993 #size-cells = <0>;
995 port@0 {
996 reg = <0>;
997 dsi0_in: endpoint {
998 remote-endpoint = <&mdp5_intf1_out>;
999 };
1000 };
1002 port@1 {
1003 reg = <1>;
1004 dsi0_out: endpoint {
1005 };
1006 };
1007 };
1008 };
1010 dsi_phy0: dsi-phy@1a98300 {
1011 compatible = "qcom,dsi-phy-28nm-lp";
1012 reg = <0x1a98300 0xd4>,
1013 <0x1a98500 0x280>,
1014 <0x1a98780 0x30>;
1015 reg-names = "dsi_pll",
1016 "dsi_phy",
1017 "dsi_phy_regulator";
1019 #clock-cells = <1>;
1020 #phy-cells = <0>;
1022 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1023 <&xo_board>;
1024 clock-names = "iface", "ref";
1025 };
1026 };
1029 hexagon@4080000 {
1030 compatible = "qcom,q6v5-pil";
1031 reg = <0x04080000 0x100>,
1032 <0x04020000 0x040>;
1034 reg-names = "qdsp6", "rmb";
1036 interrupts-extended = <&intc 0 24 1>,
1037 <&hexagon_smp2p_in 0 0>,
1038 <&hexagon_smp2p_in 1 0>,
1039 <&hexagon_smp2p_in 2 0>,
1040 <&hexagon_smp2p_in 3 0>;
1041 interrupt-names = "wdog", "fatal", "ready",
1042 "handover", "stop-ack";
1044 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1045 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1046 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1047 <&xo_board>;
1048 clock-names = "iface", "bus", "mem", "xo";
1050 qcom,smem-states = <&hexagon_smp2p_out 0>;
1051 qcom,smem-state-names = "stop";
1053 resets = <&scm 0>;
1054 reset-names = "mss_restart";
1056 cx-supply = <&pm8916_s1>;
1057 mx-supply = <&pm8916_l3>;
1058 pll-supply = <&pm8916_l7>;
1060 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1062 status = "disabled";
1064 mba {
1065 memory-region = <&mba_mem>;
1066 };
1068 mpss {
1069 memory-region = <&mpss_mem>;
1070 };
1072 smd-edge {
1073 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1075 qcom,smd-edge = <0>;
1076 qcom,ipc = <&apcs 8 12>;
1077 qcom,remote-pid = <1>;
1079 label = "hexagon";
1080 };
1081 };
1083 pronto: wcnss@a21b000 {
1084 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1085 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1086 reg-names = "ccu", "dxe", "pmu";
1088 memory-region = <&wcnss_mem>;
1090 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1091 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1092 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1093 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1094 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1095 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1097 vddmx-supply = <&pm8916_l3>;
1098 vddpx-supply = <&pm8916_l7>;
1100 qcom,state = <&wcnss_smp2p_out 0>;
1101 qcom,state-names = "stop";
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&wcnss_pin_a>;
1106 status = "disabled";
1108 iris {
1109 compatible = "qcom,wcn3620";
1111 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1112 clock-names = "xo";
1114 vddxo-supply = <&pm8916_l7>;
1115 vddrfa-supply = <&pm8916_s3>;
1116 vddpa-supply = <&pm8916_l9>;
1117 vdddig-supply = <&pm8916_l5>;
1118 };
1120 smd-edge {
1121 interrupts = <0 142 1>;
1123 qcom,ipc = <&apcs 8 17>;
1124 qcom,smd-edge = <6>;
1125 qcom,remote-pid = <4>;
1127 label = "pronto";
1129 wcnss {
1130 compatible = "qcom,wcnss";
1131 qcom,smd-channels = "WCNSS_CTRL";
1133 qcom,mmio = <&pronto>;
1135 bt {
1136 compatible = "qcom,wcnss-bt";
1137 };
1139 wifi {
1140 compatible = "qcom,wcnss-wlan";
1142 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1143 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1144 interrupt-names = "tx", "rx";
1146 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1147 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1148 };
1149 };
1150 };
1151 };
1153 tpiu@820000 {
1154 compatible = "arm,coresight-tpiu", "arm,primecell";
1155 reg = <0x820000 0x1000>;
1157 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1158 clock-names = "apb_pclk", "atclk";
1160 in-ports {
1161 port {
1162 tpiu_in: endpoint {
1163 remote-endpoint = <&replicator_out1>;
1164 };
1165 };
1166 };
1167 };
1169 funnel@821000 {
1170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1171 reg = <0x821000 0x1000>;
1173 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1174 clock-names = "apb_pclk", "atclk";
1176 in-ports {
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1180 /*
1181 * Not described input ports:
1182 * 0 - connected to Resource and Power Manger CPU ETM
1183 * 1 - not-connected
1184 * 2 - connected to Modem CPU ETM
1185 * 3 - not-connected
1186 * 5 - not-connected
1187 * 6 - connected trought funnel to Wireless CPU ETM
1188 * 7 - connected to STM component
1189 */
1191 port@4 {
1192 reg = <4>;
1193 funnel0_in4: endpoint {
1194 remote-endpoint = <&funnel1_out>;
1195 };
1196 };
1197 };
1199 out-ports {
1200 port {
1201 funnel0_out: endpoint {
1202 remote-endpoint = <&etf_in>;
1203 };
1204 };
1205 };
1206 };
1208 replicator@824000 {
1209 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1210 reg = <0x824000 0x1000>;
1212 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1213 clock-names = "apb_pclk", "atclk";
1215 out-ports {
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1219 port@0 {
1220 reg = <0>;
1221 replicator_out0: endpoint {
1222 remote-endpoint = <&etr_in>;
1223 };
1224 };
1225 port@1 {
1226 reg = <1>;
1227 replicator_out1: endpoint {
1228 remote-endpoint = <&tpiu_in>;
1229 };
1230 };
1231 };
1233 in-ports {
1234 port {
1235 replicator_in: endpoint {
1236 remote-endpoint = <&etf_out>;
1237 };
1238 };
1239 };
1240 };
1242 etf@825000 {
1243 compatible = "arm,coresight-tmc", "arm,primecell";
1244 reg = <0x825000 0x1000>;
1246 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1247 clock-names = "apb_pclk", "atclk";
1249 in-ports {
1250 port {
1251 etf_in: endpoint {
1252 remote-endpoint = <&funnel0_out>;
1253 };
1254 };
1255 };
1257 out-ports {
1258 port {
1259 etf_out: endpoint {
1260 remote-endpoint = <&replicator_in>;
1261 };
1262 };
1263 };
1264 };
1266 etr@826000 {
1267 compatible = "arm,coresight-tmc", "arm,primecell";
1268 reg = <0x826000 0x1000>;
1270 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1271 clock-names = "apb_pclk", "atclk";
1273 in-ports {
1274 port {
1275 etr_in: endpoint {
1276 remote-endpoint = <&replicator_out0>;
1277 };
1278 };
1279 };
1280 };
1282 funnel@841000 { /* APSS funnel only 4 inputs are used */
1283 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1284 reg = <0x841000 0x1000>;
1286 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1287 clock-names = "apb_pclk", "atclk";
1289 in-ports {
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1293 port@0 {
1294 reg = <0>;
1295 funnel1_in0: endpoint {
1296 remote-endpoint = <&etm0_out>;
1297 };
1298 };
1299 port@1 {
1300 reg = <1>;
1301 funnel1_in1: endpoint {
1302 remote-endpoint = <&etm1_out>;
1303 };
1304 };
1305 port@2 {
1306 reg = <2>;
1307 funnel1_in2: endpoint {
1308 remote-endpoint = <&etm2_out>;
1309 };
1310 };
1311 port@3 {
1312 reg = <3>;
1313 funnel1_in3: endpoint {
1314 remote-endpoint = <&etm3_out>;
1315 };
1316 };
1317 };
1319 out-ports {
1320 port {
1321 funnel1_out: endpoint {
1322 remote-endpoint = <&funnel0_in4>;
1323 };
1324 };
1325 };
1326 };
1328 debug@850000 {
1329 compatible = "arm,coresight-cpu-debug","arm,primecell";
1330 reg = <0x850000 0x1000>;
1331 clocks = <&rpmcc RPM_QDSS_CLK>;
1332 clock-names = "apb_pclk";
1333 cpu = <&CPU0>;
1334 };
1336 debug@852000 {
1337 compatible = "arm,coresight-cpu-debug","arm,primecell";
1338 reg = <0x852000 0x1000>;
1339 clocks = <&rpmcc RPM_QDSS_CLK>;
1340 clock-names = "apb_pclk";
1341 cpu = <&CPU1>;
1342 };
1344 debug@854000 {
1345 compatible = "arm,coresight-cpu-debug","arm,primecell";
1346 reg = <0x854000 0x1000>;
1347 clocks = <&rpmcc RPM_QDSS_CLK>;
1348 clock-names = "apb_pclk";
1349 cpu = <&CPU2>;
1350 };
1352 debug@856000 {
1353 compatible = "arm,coresight-cpu-debug","arm,primecell";
1354 reg = <0x856000 0x1000>;
1355 clocks = <&rpmcc RPM_QDSS_CLK>;
1356 clock-names = "apb_pclk";
1357 cpu = <&CPU3>;
1358 };
1360 etm@85c000 {
1361 compatible = "arm,coresight-etm4x", "arm,primecell";
1362 reg = <0x85c000 0x1000>;
1364 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1365 clock-names = "apb_pclk", "atclk";
1367 cpu = <&CPU0>;
1369 out-ports {
1370 port {
1371 etm0_out: endpoint {
1372 remote-endpoint = <&funnel1_in0>;
1373 };
1374 };
1375 };
1376 };
1378 etm@85d000 {
1379 compatible = "arm,coresight-etm4x", "arm,primecell";
1380 reg = <0x85d000 0x1000>;
1382 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1383 clock-names = "apb_pclk", "atclk";
1385 cpu = <&CPU1>;
1387 out-ports {
1388 port {
1389 etm1_out: endpoint {
1390 remote-endpoint = <&funnel1_in1>;
1391 };
1392 };
1393 };
1394 };
1396 etm@85e000 {
1397 compatible = "arm,coresight-etm4x", "arm,primecell";
1398 reg = <0x85e000 0x1000>;
1400 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1401 clock-names = "apb_pclk", "atclk";
1403 cpu = <&CPU2>;
1405 out-ports {
1406 port {
1407 etm2_out: endpoint {
1408 remote-endpoint = <&funnel1_in2>;
1409 };
1410 };
1411 };
1412 };
1414 etm@85f000 {
1415 compatible = "arm,coresight-etm4x", "arm,primecell";
1416 reg = <0x85f000 0x1000>;
1418 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1419 clock-names = "apb_pclk", "atclk";
1421 cpu = <&CPU3>;
1423 out-ports {
1424 port {
1425 etm3_out: endpoint {
1426 remote-endpoint = <&funnel1_in3>;
1427 };
1428 };
1429 };
1430 };
1432 venus: video-codec@1d00000 {
1433 compatible = "qcom,msm8916-venus";
1434 reg = <0x01d00000 0xff000>;
1435 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1436 power-domains = <&gcc VENUS_GDSC>;
1437 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1438 <&gcc GCC_VENUS0_AHB_CLK>,
1439 <&gcc GCC_VENUS0_AXI_CLK>;
1440 clock-names = "core", "iface", "bus";
1441 iommus = <&apps_iommu 5>;
1442 memory-region = <&venus_mem>;
1443 status = "okay";
1445 video-decoder {
1446 compatible = "venus-decoder";
1447 };
1449 video-encoder {
1450 compatible = "venus-encoder";
1451 };
1452 };
1454 camss: camss@1b00000 {
1455 compatible = "qcom,msm8916-camss";
1456 reg = <0x1b0ac00 0x200>,
1457 <0x1b00030 0x4>,
1458 <0x1b0b000 0x200>,
1459 <0x1b00038 0x4>,
1460 <0x1b08000 0x100>,
1461 <0x1b08400 0x100>,
1462 <0x1b0a000 0x500>,
1463 <0x1b00020 0x10>,
1464 <0x1b10000 0x1000>;
1465 reg-names = "csiphy0",
1466 "csiphy0_clk_mux",
1467 "csiphy1",
1468 "csiphy1_clk_mux",
1469 "csid0",
1470 "csid1",
1471 "ispif",
1472 "csi_clk_mux",
1473 "vfe0";
1474 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1475 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1476 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1477 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1478 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1479 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1480 interrupt-names = "csiphy0",
1481 "csiphy1",
1482 "csid0",
1483 "csid1",
1484 "ispif",
1485 "vfe0";
1486 power-domains = <&gcc VFE_GDSC>;
1487 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1488 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1489 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1490 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1491 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1492 <&gcc GCC_CAMSS_CSI0_CLK>,
1493 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1494 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1495 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1496 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1497 <&gcc GCC_CAMSS_CSI1_CLK>,
1498 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1499 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1500 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1501 <&gcc GCC_CAMSS_AHB_CLK>,
1502 <&gcc GCC_CAMSS_VFE0_CLK>,
1503 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1504 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1505 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1506 clock-names = "top_ahb",
1507 "ispif_ahb",
1508 "csiphy0_timer",
1509 "csiphy1_timer",
1510 "csi0_ahb",
1511 "csi0",
1512 "csi0_phy",
1513 "csi0_pix",
1514 "csi0_rdi",
1515 "csi1_ahb",
1516 "csi1",
1517 "csi1_phy",
1518 "csi1_pix",
1519 "csi1_rdi",
1520 "ahb",
1521 "vfe0",
1522 "csi_vfe0",
1523 "vfe_ahb",
1524 "vfe_axi";
1525 vdda-supply = <&pm8916_l2>;
1526 iommus = <&apps_iommu 3>;
1527 status = "disabled";
1528 ports {
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1531 };
1532 };
1533 };
1535 smd {
1536 compatible = "qcom,smd";
1538 rpm {
1539 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1540 qcom,ipc = <&apcs 8 0>;
1541 qcom,smd-edge = <15>;
1543 rpm_requests {
1544 compatible = "qcom,rpm-msm8916";
1545 qcom,smd-channels = "rpm_requests";
1547 rpmcc: qcom,rpmcc {
1548 compatible = "qcom,rpmcc-msm8916";
1549 #clock-cells = <1>;
1550 };
1552 smd_rpm_regulators: pm8916-regulators {
1553 compatible = "qcom,rpm-pm8916-regulators";
1555 pm8916_s1: s1 {};
1556 pm8916_s3: s3 {};
1557 pm8916_s4: s4 {};
1559 pm8916_l1: l1 {};
1560 pm8916_l2: l2 {};
1561 pm8916_l3: l3 {};
1562 pm8916_l4: l4 {};
1563 pm8916_l5: l5 {};
1564 pm8916_l6: l6 {};
1565 pm8916_l7: l7 {};
1566 pm8916_l8: l8 {};
1567 pm8916_l9: l9 {};
1568 pm8916_l10: l10 {};
1569 pm8916_l11: l11 {};
1570 pm8916_l12: l12 {};
1571 pm8916_l13: l13 {};
1572 pm8916_l14: l14 {};
1573 pm8916_l15: l15 {};
1574 pm8916_l16: l16 {};
1575 pm8916_l17: l17 {};
1576 pm8916_l18: l18 {};
1577 };
1578 };
1579 };
1580 };
1582 hexagon-smp2p {
1583 compatible = "qcom,smp2p";
1584 qcom,smem = <435>, <428>;
1586 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1588 qcom,ipc = <&apcs 8 14>;
1590 qcom,local-pid = <0>;
1591 qcom,remote-pid = <1>;
1593 hexagon_smp2p_out: master-kernel {
1594 qcom,entry-name = "master-kernel";
1596 #qcom,smem-state-cells = <1>;
1597 };
1599 hexagon_smp2p_in: slave-kernel {
1600 qcom,entry-name = "slave-kernel";
1602 interrupt-controller;
1603 #interrupt-cells = <2>;
1604 };
1605 };
1607 wcnss-smp2p {
1608 compatible = "qcom,smp2p";
1609 qcom,smem = <451>, <431>;
1611 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1613 qcom,ipc = <&apcs 8 18>;
1615 qcom,local-pid = <0>;
1616 qcom,remote-pid = <4>;
1618 wcnss_smp2p_out: master-kernel {
1619 qcom,entry-name = "master-kernel";
1621 #qcom,smem-state-cells = <1>;
1622 };
1624 wcnss_smp2p_in: slave-kernel {
1625 qcom,entry-name = "slave-kernel";
1627 interrupt-controller;
1628 #interrupt-cells = <2>;
1629 };
1630 };
1632 smsm {
1633 compatible = "qcom,smsm";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1638 qcom,ipc-1 = <&apcs 8 13>;
1639 qcom,ipc-3 = <&apcs 8 19>;
1641 apps_smsm: apps@0 {
1642 reg = <0>;
1644 #qcom,smem-state-cells = <1>;
1645 };
1647 hexagon_smsm: hexagon@1 {
1648 reg = <1>;
1649 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1651 interrupt-controller;
1652 #interrupt-cells = <2>;
1653 };
1655 wcnss_smsm: wcnss@6 {
1656 reg = <6>;
1657 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1661 };
1662 };
1663 };
1665 #include "msm8916-pins.dtsi"