| blob | 96c0a481f454eaeea74536dccec9f65f7aa73c03 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
11 / {
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 chosen { };
19 memory {
20 device_type = "memory";
21 /* We expect the bootloader to fill in the reg */
22 reg = <0 0 0 0>;
23 };
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
28 ranges;
30 mba_region: mba@91500000 {
31 reg = <0x0 0x91500000 0x0 0x200000>;
32 no-map;
33 };
35 slpi_region: slpi@90b00000 {
36 reg = <0x0 0x90b00000 0x0 0xa00000>;
37 no-map;
38 };
40 venus_region: venus@90400000 {
41 reg = <0x0 0x90400000 0x0 0x700000>;
42 no-map;
43 };
45 adsp_region: adsp@8ea00000 {
46 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
47 no-map;
48 };
50 mpss_region: mpss@88800000 {
51 reg = <0x0 0x88800000 0x0 0x6200000>;
52 no-map;
53 };
55 smem_mem: smem-mem@86000000 {
56 reg = <0x0 0x86000000 0x0 0x200000>;
57 no-map;
58 };
60 memory@85800000 {
61 reg = <0x0 0x85800000 0x0 0x800000>;
62 no-map;
63 };
65 memory@86200000 {
66 reg = <0x0 0x86200000 0x0 0x2600000>;
67 no-map;
68 };
70 rmtfs@86700000 {
71 compatible = "qcom,rmtfs-mem";
73 size = <0x0 0x200000>;
74 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
75 no-map;
77 qcom,client-id = <1>;
78 qcom,vmid = <15>;
79 };
81 zap_shader_region: gpu@8f200000 {
82 compatible = "shared-dma-pool";
83 reg = <0x0 0x90b00000 0x0 0xa00000>;
84 no-map;
85 };
86 };
88 cpus {
89 #address-cells = <2>;
90 #size-cells = <0>;
92 CPU0: cpu@0 {
93 device_type = "cpu";
94 compatible = "qcom,kryo";
95 reg = <0x0 0x0>;
96 enable-method = "psci";
97 cpu-idle-states = <&CPU_SLEEP_0>;
98 capacity-dmips-mhz = <1024>;
99 next-level-cache = <&L2_0>;
100 L2_0: l2-cache {
101 compatible = "cache";
102 cache-level = <2>;
103 };
104 };
106 CPU1: cpu@1 {
107 device_type = "cpu";
108 compatible = "qcom,kryo";
109 reg = <0x0 0x1>;
110 enable-method = "psci";
111 cpu-idle-states = <&CPU_SLEEP_0>;
112 capacity-dmips-mhz = <1024>;
113 next-level-cache = <&L2_0>;
114 };
116 CPU2: cpu@100 {
117 device_type = "cpu";
118 compatible = "qcom,kryo";
119 reg = <0x0 0x100>;
120 enable-method = "psci";
121 cpu-idle-states = <&CPU_SLEEP_0>;
122 capacity-dmips-mhz = <1024>;
123 next-level-cache = <&L2_1>;
124 L2_1: l2-cache {
125 compatible = "cache";
126 cache-level = <2>;
127 };
128 };
130 CPU3: cpu@101 {
131 device_type = "cpu";
132 compatible = "qcom,kryo";
133 reg = <0x0 0x101>;
134 enable-method = "psci";
135 cpu-idle-states = <&CPU_SLEEP_0>;
136 capacity-dmips-mhz = <1024>;
137 next-level-cache = <&L2_1>;
138 };
140 cpu-map {
141 cluster0 {
142 core0 {
143 cpu = <&CPU0>;
144 };
146 core1 {
147 cpu = <&CPU1>;
148 };
149 };
151 cluster1 {
152 core0 {
153 cpu = <&CPU2>;
154 };
156 core1 {
157 cpu = <&CPU3>;
158 };
159 };
160 };
162 idle-states {
163 entry-method = "psci";
165 CPU_SLEEP_0: cpu-sleep-0 {
166 compatible = "arm,idle-state";
167 idle-state-name = "standalone-power-collapse";
168 arm,psci-suspend-param = <0x00000004>;
169 entry-latency-us = <130>;
170 exit-latency-us = <80>;
171 min-residency-us = <300>;
172 };
173 };
174 };
176 thermal-zones {
177 cpu0-thermal {
178 polling-delay-passive = <250>;
179 polling-delay = <1000>;
181 thermal-sensors = <&tsens0 3>;
183 trips {
184 cpu0_alert0: trip-point@0 {
185 temperature = <75000>;
186 hysteresis = <2000>;
187 type = "passive";
188 };
190 cpu0_crit: cpu_crit {
191 temperature = <110000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
196 };
198 cpu1-thermal {
199 polling-delay-passive = <250>;
200 polling-delay = <1000>;
202 thermal-sensors = <&tsens0 5>;
204 trips {
205 cpu1_alert0: trip-point@0 {
206 temperature = <75000>;
207 hysteresis = <2000>;
208 type = "passive";
209 };
211 cpu1_crit: cpu_crit {
212 temperature = <110000>;
213 hysteresis = <2000>;
214 type = "critical";
215 };
216 };
217 };
219 cpu2-thermal {
220 polling-delay-passive = <250>;
221 polling-delay = <1000>;
223 thermal-sensors = <&tsens0 8>;
225 trips {
226 cpu2_alert0: trip-point@0 {
227 temperature = <75000>;
228 hysteresis = <2000>;
229 type = "passive";
230 };
232 cpu2_crit: cpu_crit {
233 temperature = <110000>;
234 hysteresis = <2000>;
235 type = "critical";
236 };
237 };
238 };
240 cpu3-thermal {
241 polling-delay-passive = <250>;
242 polling-delay = <1000>;
244 thermal-sensors = <&tsens0 10>;
246 trips {
247 cpu3_alert0: trip-point@0 {
248 temperature = <75000>;
249 hysteresis = <2000>;
250 type = "passive";
251 };
253 cpu3_crit: cpu_crit {
254 temperature = <110000>;
255 hysteresis = <2000>;
256 type = "critical";
257 };
258 };
259 };
261 gpu-thermal-top {
262 polling-delay-passive = <250>;
263 polling-delay = <1000>;
265 thermal-sensors = <&tsens1 6>;
267 trips {
268 gpu1_alert0: trip-point@0 {
269 temperature = <90000>;
270 hysteresis = <2000>;
271 type = "hot";
272 };
273 };
274 };
276 gpu-thermal-bottom {
277 polling-delay-passive = <250>;
278 polling-delay = <1000>;
280 thermal-sensors = <&tsens1 7>;
282 trips {
283 gpu2_alert0: trip-point@0 {
284 temperature = <90000>;
285 hysteresis = <2000>;
286 type = "hot";
287 };
288 };
289 };
291 m4m-thermal {
292 polling-delay-passive = <250>;
293 polling-delay = <1000>;
295 thermal-sensors = <&tsens0 1>;
297 trips {
298 m4m_alert0: trip-point@0 {
299 temperature = <90000>;
300 hysteresis = <2000>;
301 type = "hot";
302 };
303 };
304 };
306 l3-or-venus-thermal {
307 polling-delay-passive = <250>;
308 polling-delay = <1000>;
310 thermal-sensors = <&tsens0 2>;
312 trips {
313 l3_or_venus_alert0: trip-point@0 {
314 temperature = <90000>;
315 hysteresis = <2000>;
316 type = "hot";
317 };
318 };
319 };
321 cluster0-l2-thermal {
322 polling-delay-passive = <250>;
323 polling-delay = <1000>;
325 thermal-sensors = <&tsens0 7>;
327 trips {
328 cluster0_l2_alert0: trip-point@0 {
329 temperature = <90000>;
330 hysteresis = <2000>;
331 type = "hot";
332 };
333 };
334 };
336 cluster1-l2-thermal {
337 polling-delay-passive = <250>;
338 polling-delay = <1000>;
340 thermal-sensors = <&tsens0 12>;
342 trips {
343 cluster1_l2_alert0: trip-point@0 {
344 temperature = <90000>;
345 hysteresis = <2000>;
346 type = "hot";
347 };
348 };
349 };
351 camera-thermal {
352 polling-delay-passive = <250>;
353 polling-delay = <1000>;
355 thermal-sensors = <&tsens1 1>;
357 trips {
358 camera_alert0: trip-point@0 {
359 temperature = <90000>;
360 hysteresis = <2000>;
361 type = "hot";
362 };
363 };
364 };
366 q6-dsp-thermal {
367 polling-delay-passive = <250>;
368 polling-delay = <1000>;
370 thermal-sensors = <&tsens1 2>;
372 trips {
373 q6_dsp_alert0: trip-point@0 {
374 temperature = <90000>;
375 hysteresis = <2000>;
376 type = "hot";
377 };
378 };
379 };
381 mem-thermal {
382 polling-delay-passive = <250>;
383 polling-delay = <1000>;
385 thermal-sensors = <&tsens1 3>;
387 trips {
388 mem_alert0: trip-point@0 {
389 temperature = <90000>;
390 hysteresis = <2000>;
391 type = "hot";
392 };
393 };
394 };
396 modemtx-thermal {
397 polling-delay-passive = <250>;
398 polling-delay = <1000>;
400 thermal-sensors = <&tsens1 4>;
402 trips {
403 modemtx_alert0: trip-point@0 {
404 temperature = <90000>;
405 hysteresis = <2000>;
406 type = "hot";
407 };
408 };
409 };
410 };
412 timer {
413 compatible = "arm,armv8-timer";
414 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
415 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
416 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
417 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
418 };
420 clocks {
421 xo_board: xo_board {
422 compatible = "fixed-clock";
423 #clock-cells = <0>;
424 clock-frequency = <19200000>;
425 clock-output-names = "xo_board";
426 };
428 sleep_clk: sleep_clk {
429 compatible = "fixed-clock";
430 #clock-cells = <0>;
431 clock-frequency = <32764>;
432 clock-output-names = "sleep_clk";
433 };
434 };
436 psci {
437 compatible = "arm,psci-1.0";
438 method = "smc";
439 };
441 firmware {
442 scm {
443 compatible = "qcom,scm-msm8996";
445 qcom,dload-mode = <&tcsr 0x13000>;
446 };
447 };
449 tcsr_mutex: hwlock {
450 compatible = "qcom,tcsr-mutex";
451 syscon = <&tcsr_mutex_regs 0 0x1000>;
452 #hwlock-cells = <1>;
453 };
455 smem {
456 compatible = "qcom,smem";
457 memory-region = <&smem_mem>;
458 hwlocks = <&tcsr_mutex 3>;
459 };
461 rpm-glink {
462 compatible = "qcom,glink-rpm";
464 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
466 qcom,rpm-msg-ram = <&rpm_msg_ram>;
468 mboxes = <&apcs_glb 0>;
470 rpm_requests {
471 compatible = "qcom,rpm-msm8996";
472 qcom,glink-channels = "rpm_requests";
474 rpmcc: qcom,rpmcc {
475 compatible = "qcom,rpmcc-msm8996";
476 #clock-cells = <1>;
477 };
479 rpmpd: power-controller {
480 compatible = "qcom,msm8996-rpmpd";
481 #power-domain-cells = <1>;
482 operating-points-v2 = <&rpmpd_opp_table>;
484 rpmpd_opp_table: opp-table {
485 compatible = "operating-points-v2";
487 rpmpd_opp1: opp1 {
488 opp-level = <1>;
489 };
491 rpmpd_opp2: opp2 {
492 opp-level = <2>;
493 };
495 rpmpd_opp3: opp3 {
496 opp-level = <3>;
497 };
499 rpmpd_opp4: opp4 {
500 opp-level = <4>;
501 };
503 rpmpd_opp5: opp5 {
504 opp-level = <5>;
505 };
507 rpmpd_opp6: opp6 {
508 opp-level = <6>;
509 };
510 };
511 };
513 pm8994-regulators {
514 compatible = "qcom,rpm-pm8994-regulators";
516 pm8994_s1: s1 {};
517 pm8994_s2: s2 {};
518 pm8994_s3: s3 {};
519 pm8994_s4: s4 {};
520 pm8994_s5: s5 {};
521 pm8994_s6: s6 {};
522 pm8994_s7: s7 {};
523 pm8994_s8: s8 {};
524 pm8994_s9: s9 {};
525 pm8994_s10: s10 {};
526 pm8994_s11: s11 {};
527 pm8994_s12: s12 {};
529 pm8994_l1: l1 {};
530 pm8994_l2: l2 {};
531 pm8994_l3: l3 {};
532 pm8994_l4: l4 {};
533 pm8994_l5: l5 {};
534 pm8994_l6: l6 {};
535 pm8994_l7: l7 {};
536 pm8994_l8: l8 {};
537 pm8994_l9: l9 {};
538 pm8994_l10: l10 {};
539 pm8994_l11: l11 {};
540 pm8994_l12: l12 {};
541 pm8994_l13: l13 {};
542 pm8994_l14: l14 {};
543 pm8994_l15: l15 {};
544 pm8994_l16: l16 {};
545 pm8994_l17: l17 {};
546 pm8994_l18: l18 {};
547 pm8994_l19: l19 {};
548 pm8994_l20: l20 {};
549 pm8994_l21: l21 {};
550 pm8994_l22: l22 {};
551 pm8994_l23: l23 {};
552 pm8994_l24: l24 {};
553 pm8994_l25: l25 {};
554 pm8994_l26: l26 {};
555 pm8994_l27: l27 {};
556 pm8994_l28: l28 {};
557 pm8994_l29: l29 {};
558 pm8994_l30: l30 {};
559 pm8994_l31: l31 {};
560 pm8994_l32: l32 {};
561 };
563 };
564 };
566 soc: soc {
567 #address-cells = <1>;
568 #size-cells = <1>;
569 ranges = <0 0 0 0xffffffff>;
570 compatible = "simple-bus";
572 rpm_msg_ram: memory@68000 {
573 compatible = "qcom,rpm-msg-ram";
574 reg = <0x68000 0x6000>;
575 };
577 rng: rng@83000 {
578 compatible = "qcom,prng-ee";
579 reg = <0x00083000 0x1000>;
580 clocks = <&gcc GCC_PRNG_AHB_CLK>;
581 clock-names = "core";
582 };
584 tcsr_mutex_regs: syscon@740000 {
585 compatible = "syscon";
586 reg = <0x740000 0x20000>;
587 };
589 tsens0: thermal-sensor@4a9000 {
590 compatible = "qcom,msm8996-tsens";
591 reg = <0x4a9000 0x1000>, /* TM */
592 <0x4a8000 0x1000>; /* SROT */
593 #qcom,sensors = <13>;
594 #thermal-sensor-cells = <1>;
595 };
597 tsens1: thermal-sensor@4ad000 {
598 compatible = "qcom,msm8996-tsens";
599 reg = <0x4ad000 0x1000>, /* TM */
600 <0x4ac000 0x1000>; /* SROT */
601 #qcom,sensors = <8>;
602 #thermal-sensor-cells = <1>;
603 };
605 tcsr: syscon@7a0000 {
606 compatible = "qcom,tcsr-msm8996", "syscon";
607 reg = <0x7a0000 0x18000>;
608 };
610 intc: interrupt-controller@9bc0000 {
611 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
612 #interrupt-cells = <3>;
613 interrupt-controller;
614 #redistributor-regions = <1>;
615 redistributor-stride = <0x0 0x40000>;
616 reg = <0x09bc0000 0x10000>,
617 <0x09c00000 0x100000>;
618 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
619 };
621 apcs_glb: mailbox@9820000 {
622 compatible = "qcom,msm8996-apcs-hmss-global";
623 reg = <0x9820000 0x1000>;
625 #mbox-cells = <1>;
626 };
628 gcc: clock-controller@300000 {
629 compatible = "qcom,gcc-msm8996";
630 #clock-cells = <1>;
631 #reset-cells = <1>;
632 #power-domain-cells = <1>;
633 reg = <0x300000 0x90000>;
634 };
636 kryocc: clock-controller@6400000 {
637 compatible = "qcom,apcc-msm8996";
638 reg = <0x6400000 0x90000>;
639 #clock-cells = <1>;
640 };
642 blsp1_uart1: serial@7570000 {
643 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
644 reg = <0x07570000 0x1000>;
645 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
647 <&gcc GCC_BLSP1_AHB_CLK>;
648 clock-names = "core", "iface";
649 status = "disabled";
650 };
652 blsp1_spi0: spi@7575000 {
653 compatible = "qcom,spi-qup-v2.2.1";
654 reg = <0x07575000 0x600>;
655 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
657 <&gcc GCC_BLSP1_AHB_CLK>;
658 clock-names = "core", "iface";
659 pinctrl-names = "default", "sleep";
660 pinctrl-0 = <&blsp1_spi0_default>;
661 pinctrl-1 = <&blsp1_spi0_sleep>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 status = "disabled";
665 };
667 blsp2_i2c0: i2c@75b5000 {
668 compatible = "qcom,i2c-qup-v2.2.1";
669 reg = <0x075b5000 0x1000>;
670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
672 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
673 clock-names = "iface", "core";
674 pinctrl-names = "default", "sleep";
675 pinctrl-0 = <&blsp2_i2c0_default>;
676 pinctrl-1 = <&blsp2_i2c0_sleep>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 status = "disabled";
680 };
682 blsp2_uart1: serial@75b0000 {
683 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
684 reg = <0x75b0000 0x1000>;
685 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
687 <&gcc GCC_BLSP2_AHB_CLK>;
688 clock-names = "core", "iface";
689 status = "disabled";
690 };
692 blsp2_i2c1: i2c@75b6000 {
693 compatible = "qcom,i2c-qup-v2.2.1";
694 reg = <0x075b6000 0x1000>;
695 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
697 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
698 clock-names = "iface", "core";
699 pinctrl-names = "default", "sleep";
700 pinctrl-0 = <&blsp2_i2c1_default>;
701 pinctrl-1 = <&blsp2_i2c1_sleep>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 status = "disabled";
705 };
707 blsp2_uart2: serial@75b1000 {
708 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
709 reg = <0x075b1000 0x1000>;
710 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
712 <&gcc GCC_BLSP2_AHB_CLK>;
713 clock-names = "core", "iface";
714 status = "disabled";
715 };
717 blsp1_i2c2: i2c@7577000 {
718 compatible = "qcom,i2c-qup-v2.2.1";
719 reg = <0x07577000 0x1000>;
720 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
722 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
723 clock-names = "iface", "core";
724 pinctrl-names = "default", "sleep";
725 pinctrl-0 = <&blsp1_i2c2_default>;
726 pinctrl-1 = <&blsp1_i2c2_sleep>;
727 #address-cells = <1>;
728 #size-cells = <0>;
729 status = "disabled";
730 };
732 blsp2_spi5: spi@75ba000{
733 compatible = "qcom,spi-qup-v2.2.1";
734 reg = <0x075ba000 0x600>;
735 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
737 <&gcc GCC_BLSP2_AHB_CLK>;
738 clock-names = "core", "iface";
739 pinctrl-names = "default", "sleep";
740 pinctrl-0 = <&blsp2_spi5_default>;
741 pinctrl-1 = <&blsp2_spi5_sleep>;
742 #address-cells = <1>;
743 #size-cells = <0>;
744 status = "disabled";
745 };
747 sdhc2: sdhci@74a4900 {
748 status = "disabled";
749 compatible = "qcom,sdhci-msm-v4";
750 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
751 reg-names = "hc_mem", "core_mem";
753 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
754 <0 221 IRQ_TYPE_LEVEL_HIGH>;
755 interrupt-names = "hc_irq", "pwr_irq";
757 clock-names = "iface", "core", "xo";
758 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
759 <&gcc GCC_SDCC2_APPS_CLK>,
760 <&xo_board>;
761 bus-width = <4>;
762 };
764 msmgpio: pinctrl@1010000 {
765 compatible = "qcom,msm8996-pinctrl";
766 reg = <0x01010000 0x300000>;
767 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
768 gpio-controller;
769 #gpio-cells = <2>;
770 interrupt-controller;
771 #interrupt-cells = <2>;
772 };
774 timer@9840000 {
775 #address-cells = <1>;
776 #size-cells = <1>;
777 ranges;
778 compatible = "arm,armv7-timer-mem";
779 reg = <0x09840000 0x1000>;
780 clock-frequency = <19200000>;
782 frame@9850000 {
783 frame-number = <0>;
784 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
786 reg = <0x09850000 0x1000>,
787 <0x09860000 0x1000>;
788 };
790 frame@9870000 {
791 frame-number = <1>;
792 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
793 reg = <0x09870000 0x1000>;
794 status = "disabled";
795 };
797 frame@9880000 {
798 frame-number = <2>;
799 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
800 reg = <0x09880000 0x1000>;
801 status = "disabled";
802 };
804 frame@9890000 {
805 frame-number = <3>;
806 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
807 reg = <0x09890000 0x1000>;
808 status = "disabled";
809 };
811 frame@98a0000 {
812 frame-number = <4>;
813 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
814 reg = <0x098a0000 0x1000>;
815 status = "disabled";
816 };
818 frame@98b0000 {
819 frame-number = <5>;
820 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
821 reg = <0x098b0000 0x1000>;
822 status = "disabled";
823 };
825 frame@98c0000 {
826 frame-number = <6>;
827 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
828 reg = <0x098c0000 0x1000>;
829 status = "disabled";
830 };
831 };
833 spmi_bus: qcom,spmi@400f000 {
834 compatible = "qcom,spmi-pmic-arb";
835 reg = <0x400f000 0x1000>,
836 <0x4400000 0x800000>,
837 <0x4c00000 0x800000>,
838 <0x5800000 0x200000>,
839 <0x400a000 0x002100>;
840 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
841 interrupt-names = "periph_irq";
842 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
843 qcom,ee = <0>;
844 qcom,channel = <0>;
845 #address-cells = <2>;
846 #size-cells = <0>;
847 interrupt-controller;
848 #interrupt-cells = <4>;
849 };
851 ufsphy: phy@627000 {
852 compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
853 reg = <0x627000 0xda8>;
854 reg-names = "phy_mem";
855 #phy-cells = <0>;
857 vdda-phy-supply = <&pm8994_l28>;
858 vdda-pll-supply = <&pm8994_l12>;
860 vdda-phy-max-microamp = <18380>;
861 vdda-pll-max-microamp = <9440>;
863 vddp-ref-clk-supply = <&pm8994_l25>;
864 vddp-ref-clk-max-microamp = <100>;
865 vddp-ref-clk-always-on;
867 clock-names = "ref_clk_src", "ref_clk";
868 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
869 <&gcc GCC_UFS_CLKREF_CLK>;
870 resets = <&ufshc 0>;
871 status = "disabled";
872 };
874 ufshc: ufshc@624000 {
875 compatible = "qcom,ufshc";
876 reg = <0x624000 0x2500>;
877 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
879 phys = <&ufsphy>;
880 phy-names = "ufsphy";
882 vcc-supply = <&pm8994_l20>;
883 vccq-supply = <&pm8994_l25>;
884 vccq2-supply = <&pm8994_s4>;
886 vcc-max-microamp = <600000>;
887 vccq-max-microamp = <450000>;
888 vccq2-max-microamp = <450000>;
890 power-domains = <&gcc UFS_GDSC>;
892 clock-names =
893 "core_clk_src",
894 "core_clk",
895 "bus_clk",
896 "bus_aggr_clk",
897 "iface_clk",
898 "core_clk_unipro_src",
899 "core_clk_unipro",
900 "core_clk_ice",
901 "ref_clk",
902 "tx_lane0_sync_clk",
903 "rx_lane0_sync_clk";
904 clocks =
905 <&gcc UFS_AXI_CLK_SRC>,
906 <&gcc GCC_UFS_AXI_CLK>,
907 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
908 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
909 <&gcc GCC_UFS_AHB_CLK>,
910 <&gcc UFS_ICE_CORE_CLK_SRC>,
911 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
912 <&gcc GCC_UFS_ICE_CORE_CLK>,
913 <&rpmcc RPM_SMD_LN_BB_CLK>,
914 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
915 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
916 freq-table-hz =
917 <100000000 200000000>,
918 <0 0>,
919 <0 0>,
920 <0 0>,
921 <0 0>,
922 <150000000 300000000>,
923 <0 0>,
924 <0 0>,
925 <0 0>,
926 <0 0>,
927 <0 0>;
929 lanes-per-direction = <1>;
930 #reset-cells = <1>;
931 status = "disabled";
933 ufs_variant {
934 compatible = "qcom,ufs_variant";
935 };
936 };
938 mmcc: clock-controller@8c0000 {
939 compatible = "qcom,mmcc-msm8996";
940 #clock-cells = <1>;
941 #reset-cells = <1>;
942 #power-domain-cells = <1>;
943 reg = <0x8c0000 0x40000>;
944 assigned-clocks = <&mmcc MMPLL9_PLL>,
945 <&mmcc MMPLL1_PLL>,
946 <&mmcc MMPLL3_PLL>,
947 <&mmcc MMPLL4_PLL>,
948 <&mmcc MMPLL5_PLL>;
949 assigned-clock-rates = <624000000>,
950 <810000000>,
951 <980000000>,
952 <960000000>,
953 <825000000>;
954 };
956 qfprom@74000 {
957 compatible = "qcom,qfprom";
958 reg = <0x74000 0x8ff>;
959 #address-cells = <1>;
960 #size-cells = <1>;
962 qusb2p_hstx_trim: hstx_trim@24e {
963 reg = <0x24e 0x2>;
964 bits = <5 4>;
965 };
967 qusb2s_hstx_trim: hstx_trim@24f {
968 reg = <0x24f 0x1>;
969 bits = <1 4>;
970 };
972 gpu_speed_bin: gpu_speed_bin@133 {
973 reg = <0x133 0x1>;
974 bits = <5 3>;
975 };
976 };
978 phy@34000 {
979 compatible = "qcom,msm8996-qmp-pcie-phy";
980 reg = <0x34000 0x488>;
981 #clock-cells = <1>;
982 #address-cells = <1>;
983 #size-cells = <1>;
984 ranges;
986 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
987 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
988 <&gcc GCC_PCIE_CLKREF_CLK>;
989 clock-names = "aux", "cfg_ahb", "ref";
991 vdda-phy-supply = <&pm8994_l28>;
992 vdda-pll-supply = <&pm8994_l12>;
994 resets = <&gcc GCC_PCIE_PHY_BCR>,
995 <&gcc GCC_PCIE_PHY_COM_BCR>,
996 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
997 reset-names = "phy", "common", "cfg";
998 status = "disabled";
1000 pciephy_0: lane@35000 {
1001 reg = <0x035000 0x130>,
1002 <0x035200 0x200>,
1003 <0x035400 0x1dc>;
1004 #phy-cells = <0>;
1006 clock-output-names = "pcie_0_pipe_clk_src";
1007 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1008 clock-names = "pipe0";
1009 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1010 reset-names = "lane0";
1011 };
1013 pciephy_1: lane@36000 {
1014 reg = <0x036000 0x130>,
1015 <0x036200 0x200>,
1016 <0x036400 0x1dc>;
1017 #phy-cells = <0>;
1019 clock-output-names = "pcie_1_pipe_clk_src";
1020 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1021 clock-names = "pipe1";
1022 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1023 reset-names = "lane1";
1024 };
1026 pciephy_2: lane@37000 {
1027 reg = <0x037000 0x130>,
1028 <0x037200 0x200>,
1029 <0x037400 0x1dc>;
1030 #phy-cells = <0>;
1032 clock-output-names = "pcie_2_pipe_clk_src";
1033 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1034 clock-names = "pipe2";
1035 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1036 reset-names = "lane2";
1037 };
1038 };
1040 phy@7410000 {
1041 compatible = "qcom,msm8996-qmp-usb3-phy";
1042 reg = <0x7410000 0x1c4>;
1043 #clock-cells = <1>;
1044 #address-cells = <1>;
1045 #size-cells = <1>;
1046 ranges;
1048 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1049 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1050 <&gcc GCC_USB3_CLKREF_CLK>;
1051 clock-names = "aux", "cfg_ahb", "ref";
1053 vdda-phy-supply = <&pm8994_l28>;
1054 vdda-pll-supply = <&pm8994_l12>;
1056 resets = <&gcc GCC_USB3_PHY_BCR>,
1057 <&gcc GCC_USB3PHY_PHY_BCR>;
1058 reset-names = "phy", "common";
1059 status = "disabled";
1061 ssusb_phy_0: lane@7410200 {
1062 reg = <0x7410200 0x200>,
1063 <0x7410400 0x130>,
1064 <0x7410600 0x1a8>;
1065 #phy-cells = <0>;
1067 clock-output-names = "usb3_phy_pipe_clk_src";
1068 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1069 clock-names = "pipe0";
1070 };
1071 };
1073 hsusb_phy1: phy@7411000 {
1074 compatible = "qcom,msm8996-qusb2-phy";
1075 reg = <0x7411000 0x180>;
1076 #phy-cells = <0>;
1078 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1079 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1080 clock-names = "cfg_ahb", "ref";
1082 vdda-pll-supply = <&pm8994_l12>;
1083 vdda-phy-dpdm-supply = <&pm8994_l24>;
1085 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1086 nvmem-cells = <&qusb2p_hstx_trim>;
1087 status = "disabled";
1088 };
1090 hsusb_phy2: phy@7412000 {
1091 compatible = "qcom,msm8996-qusb2-phy";
1092 reg = <0x7412000 0x180>;
1093 #phy-cells = <0>;
1095 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1096 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1097 clock-names = "cfg_ahb", "ref";
1099 vdda-pll-supply = <&pm8994_l12>;
1100 vdda-phy-dpdm-supply = <&pm8994_l24>;
1102 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1103 nvmem-cells = <&qusb2s_hstx_trim>;
1104 status = "disabled";
1105 };
1107 usb2: usb@76f8800 {
1108 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1109 reg = <0x76f8800 0x400>;
1110 #address-cells = <1>;
1111 #size-cells = <1>;
1112 ranges;
1114 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1115 <&gcc GCC_USB20_MASTER_CLK>,
1116 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1117 <&gcc GCC_USB20_SLEEP_CLK>,
1118 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1120 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1121 <&gcc GCC_USB20_MASTER_CLK>;
1122 assigned-clock-rates = <19200000>, <60000000>;
1124 power-domains = <&gcc USB30_GDSC>;
1125 status = "disabled";
1127 dwc3@7600000 {
1128 compatible = "snps,dwc3";
1129 reg = <0x7600000 0xcc00>;
1130 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1131 phys = <&hsusb_phy2>;
1132 phy-names = "usb2-phy";
1133 };
1134 };
1136 usb3: usb@6af8800 {
1137 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1138 reg = <0x6af8800 0x400>;
1139 #address-cells = <1>;
1140 #size-cells = <1>;
1141 ranges;
1143 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1144 <&gcc GCC_USB30_MASTER_CLK>,
1145 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1146 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1147 <&gcc GCC_USB30_SLEEP_CLK>,
1148 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1150 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1151 <&gcc GCC_USB30_MASTER_CLK>;
1152 assigned-clock-rates = <19200000>, <120000000>;
1154 power-domains = <&gcc USB30_GDSC>;
1155 status = "disabled";
1157 dwc3@6a00000 {
1158 compatible = "snps,dwc3";
1159 reg = <0x6a00000 0xcc00>;
1160 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1161 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1162 phy-names = "usb2-phy", "usb3-phy";
1163 };
1164 };
1166 vfe_smmu: arm,smmu@da0000 {
1167 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1168 reg = <0xda0000 0x10000>;
1170 #global-interrupts = <1>;
1171 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1174 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1175 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1176 <&mmcc SMMU_VFE_AXI_CLK>;
1177 clock-names = "iface",
1178 "bus";
1179 #iommu-cells = <1>;
1180 };
1182 camss: camss@a00000 {
1183 compatible = "qcom,msm8996-camss";
1184 reg = <0xa34000 0x1000>,
1185 <0xa00030 0x4>,
1186 <0xa35000 0x1000>,
1187 <0xa00038 0x4>,
1188 <0xa36000 0x1000>,
1189 <0xa00040 0x4>,
1190 <0xa30000 0x100>,
1191 <0xa30400 0x100>,
1192 <0xa30800 0x100>,
1193 <0xa30c00 0x100>,
1194 <0xa31000 0x500>,
1195 <0xa00020 0x10>,
1196 <0xa10000 0x1000>,
1197 <0xa14000 0x1000>;
1198 reg-names = "csiphy0",
1199 "csiphy0_clk_mux",
1200 "csiphy1",
1201 "csiphy1_clk_mux",
1202 "csiphy2",
1203 "csiphy2_clk_mux",
1204 "csid0",
1205 "csid1",
1206 "csid2",
1207 "csid3",
1208 "ispif",
1209 "csi_clk_mux",
1210 "vfe0",
1211 "vfe1";
1212 interrupts = <GIC_SPI 78 0>,
1213 <GIC_SPI 79 0>,
1214 <GIC_SPI 80 0>,
1215 <GIC_SPI 296 0>,
1216 <GIC_SPI 297 0>,
1217 <GIC_SPI 298 0>,
1218 <GIC_SPI 299 0>,
1219 <GIC_SPI 309 0>,
1220 <GIC_SPI 314 0>,
1221 <GIC_SPI 315 0>;
1222 interrupt-names = "csiphy0",
1223 "csiphy1",
1224 "csiphy2",
1225 "csid0",
1226 "csid1",
1227 "csid2",
1228 "csid3",
1229 "ispif",
1230 "vfe0",
1231 "vfe1";
1232 power-domains = <&mmcc VFE0_GDSC>;
1233 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1234 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1235 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1236 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1237 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1238 <&mmcc CAMSS_CSI0_AHB_CLK>,
1239 <&mmcc CAMSS_CSI0_CLK>,
1240 <&mmcc CAMSS_CSI0PHY_CLK>,
1241 <&mmcc CAMSS_CSI0PIX_CLK>,
1242 <&mmcc CAMSS_CSI0RDI_CLK>,
1243 <&mmcc CAMSS_CSI1_AHB_CLK>,
1244 <&mmcc CAMSS_CSI1_CLK>,
1245 <&mmcc CAMSS_CSI1PHY_CLK>,
1246 <&mmcc CAMSS_CSI1PIX_CLK>,
1247 <&mmcc CAMSS_CSI1RDI_CLK>,
1248 <&mmcc CAMSS_CSI2_AHB_CLK>,
1249 <&mmcc CAMSS_CSI2_CLK>,
1250 <&mmcc CAMSS_CSI2PHY_CLK>,
1251 <&mmcc CAMSS_CSI2PIX_CLK>,
1252 <&mmcc CAMSS_CSI2RDI_CLK>,
1253 <&mmcc CAMSS_CSI3_AHB_CLK>,
1254 <&mmcc CAMSS_CSI3_CLK>,
1255 <&mmcc CAMSS_CSI3PHY_CLK>,
1256 <&mmcc CAMSS_CSI3PIX_CLK>,
1257 <&mmcc CAMSS_CSI3RDI_CLK>,
1258 <&mmcc CAMSS_AHB_CLK>,
1259 <&mmcc CAMSS_VFE0_CLK>,
1260 <&mmcc CAMSS_CSI_VFE0_CLK>,
1261 <&mmcc CAMSS_VFE0_AHB_CLK>,
1262 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1263 <&mmcc CAMSS_VFE1_CLK>,
1264 <&mmcc CAMSS_CSI_VFE1_CLK>,
1265 <&mmcc CAMSS_VFE1_AHB_CLK>,
1266 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1267 <&mmcc CAMSS_VFE_AHB_CLK>,
1268 <&mmcc CAMSS_VFE_AXI_CLK>;
1269 clock-names = "top_ahb",
1270 "ispif_ahb",
1271 "csiphy0_timer",
1272 "csiphy1_timer",
1273 "csiphy2_timer",
1274 "csi0_ahb",
1275 "csi0",
1276 "csi0_phy",
1277 "csi0_pix",
1278 "csi0_rdi",
1279 "csi1_ahb",
1280 "csi1",
1281 "csi1_phy",
1282 "csi1_pix",
1283 "csi1_rdi",
1284 "csi2_ahb",
1285 "csi2",
1286 "csi2_phy",
1287 "csi2_pix",
1288 "csi2_rdi",
1289 "csi3_ahb",
1290 "csi3",
1291 "csi3_phy",
1292 "csi3_pix",
1293 "csi3_rdi",
1294 "ahb",
1295 "vfe0",
1296 "csi_vfe0",
1297 "vfe0_ahb",
1298 "vfe0_stream",
1299 "vfe1",
1300 "csi_vfe1",
1301 "vfe1_ahb",
1302 "vfe1_stream",
1303 "vfe_ahb",
1304 "vfe_axi";
1305 vdda-supply = <&pm8994_l2>;
1306 iommus = <&vfe_smmu 0>,
1307 <&vfe_smmu 1>,
1308 <&vfe_smmu 2>,
1309 <&vfe_smmu 3>;
1310 status = "disabled";
1311 ports {
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 };
1315 };
1317 adreno_smmu: arm,smmu@b40000 {
1318 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1319 reg = <0xb40000 0x10000>;
1321 #global-interrupts = <1>;
1322 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1325 #iommu-cells = <1>;
1327 clocks = <&mmcc GPU_AHB_CLK>,
1328 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1329 clock-names = "iface", "bus";
1331 power-domains = <&mmcc GPU_GDSC>;
1332 };
1334 mdp_smmu: arm,smmu@d00000 {
1335 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1336 reg = <0xd00000 0x10000>;
1338 #global-interrupts = <1>;
1339 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1342 #iommu-cells = <1>;
1343 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1344 <&mmcc SMMU_MDP_AXI_CLK>;
1345 clock-names = "iface", "bus";
1347 power-domains = <&mmcc MDSS_GDSC>;
1348 };
1350 lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
1351 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1352 reg = <0x1600000 0x20000>;
1353 #iommu-cells = <1>;
1354 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1356 #global-interrupts = <1>;
1357 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1371 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1372 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1373 clock-names = "iface", "bus";
1374 };
1376 agnoc@0 {
1377 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1378 compatible = "simple-pm-bus";
1379 #address-cells = <1>;
1380 #size-cells = <1>;
1381 ranges;
1383 pcie0: pcie@600000 {
1384 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1385 status = "disabled";
1386 power-domains = <&gcc PCIE0_GDSC>;
1387 bus-range = <0x00 0xff>;
1388 num-lanes = <1>;
1390 reg = <0x00600000 0x2000>,
1391 <0x0c000000 0xf1d>,
1392 <0x0c000f20 0xa8>,
1393 <0x0c100000 0x100000>;
1394 reg-names = "parf", "dbi", "elbi","config";
1396 phys = <&pciephy_0>;
1397 phy-names = "pciephy";
1399 #address-cells = <3>;
1400 #size-cells = <2>;
1401 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1402 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1404 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1405 interrupt-names = "msi";
1406 #interrupt-cells = <1>;
1407 interrupt-map-mask = <0 0 0 0x7>;
1408 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1409 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1410 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1411 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1413 pinctrl-names = "default", "sleep";
1414 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1415 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1418 vdda-supply = <&pm8994_l28>;
1420 linux,pci-domain = <0>;
1422 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1423 <&gcc GCC_PCIE_0_AUX_CLK>,
1424 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1425 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1426 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1428 clock-names = "pipe",
1429 "aux",
1430 "cfg",
1431 "bus_master",
1432 "bus_slave";
1434 };
1436 pcie1: pcie@608000 {
1437 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1438 power-domains = <&gcc PCIE1_GDSC>;
1439 bus-range = <0x00 0xff>;
1440 num-lanes = <1>;
1442 status = "disabled";
1444 reg = <0x00608000 0x2000>,
1445 <0x0d000000 0xf1d>,
1446 <0x0d000f20 0xa8>,
1447 <0x0d100000 0x100000>;
1449 reg-names = "parf", "dbi", "elbi","config";
1451 phys = <&pciephy_1>;
1452 phy-names = "pciephy";
1454 #address-cells = <3>;
1455 #size-cells = <2>;
1456 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1457 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1459 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1460 interrupt-names = "msi";
1461 #interrupt-cells = <1>;
1462 interrupt-map-mask = <0 0 0 0x7>;
1463 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1464 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1465 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1466 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1468 pinctrl-names = "default", "sleep";
1469 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1470 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1473 vdda-supply = <&pm8994_l28>;
1474 linux,pci-domain = <1>;
1476 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1477 <&gcc GCC_PCIE_1_AUX_CLK>,
1478 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1479 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1480 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1482 clock-names = "pipe",
1483 "aux",
1484 "cfg",
1485 "bus_master",
1486 "bus_slave";
1487 };
1489 pcie2: pcie@610000 {
1490 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1491 power-domains = <&gcc PCIE2_GDSC>;
1492 bus-range = <0x00 0xff>;
1493 num-lanes = <1>;
1494 status = "disabled";
1495 reg = <0x00610000 0x2000>,
1496 <0x0e000000 0xf1d>,
1497 <0x0e000f20 0xa8>,
1498 <0x0e100000 0x100000>;
1500 reg-names = "parf", "dbi", "elbi","config";
1502 phys = <&pciephy_2>;
1503 phy-names = "pciephy";
1505 #address-cells = <3>;
1506 #size-cells = <2>;
1507 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1508 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1510 device_type = "pci";
1512 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1513 interrupt-names = "msi";
1514 #interrupt-cells = <1>;
1515 interrupt-map-mask = <0 0 0 0x7>;
1516 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1517 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1518 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1519 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1521 pinctrl-names = "default", "sleep";
1522 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1523 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1525 vdda-supply = <&pm8994_l28>;
1527 linux,pci-domain = <2>;
1528 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1529 <&gcc GCC_PCIE_2_AUX_CLK>,
1530 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1531 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1532 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1534 clock-names = "pipe",
1535 "aux",
1536 "cfg",
1537 "bus_master",
1538 "bus_slave";
1539 };
1540 };
1542 slimbam:dma@9184000
1543 {
1544 compatible = "qcom,bam-v1.7.0";
1545 qcom,controlled-remotely;
1546 reg = <0x9184000 0x32000>;
1547 num-channels = <31>;
1548 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
1549 #dma-cells = <1>;
1550 qcom,ee = <1>;
1551 qcom,num-ees = <2>;
1552 };
1554 slim_msm: slim@91c0000 {
1555 compatible = "qcom,slim-ngd-v1.5.0";
1556 reg = <0x91c0000 0x2C000>;
1557 reg-names = "ctrl";
1558 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
1559 dmas = <&slimbam 3>, <&slimbam 4>,
1560 <&slimbam 5>, <&slimbam 6>;
1561 dma-names = "rx", "tx", "tx2", "rx2";
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1564 ngd@1 {
1565 reg = <1>;
1566 #address-cells = <1>;
1567 #size-cells = <1>;
1569 tasha_ifd: tas-ifd {
1570 compatible = "slim217,1a0";
1571 reg = <0 0>;
1572 };
1574 wcd9335: codec@1{
1575 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
1576 pinctrl-names = "default";
1578 compatible = "slim217,1a0";
1579 reg = <1 0>;
1581 interrupt-parent = <&msmgpio>;
1582 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
1583 <53 IRQ_TYPE_LEVEL_HIGH>;
1584 interrupt-names = "intr1", "intr2";
1585 interrupt-controller;
1586 #interrupt-cells = <1>;
1587 reset-gpios = <&msmgpio 64 0>;
1589 slim-ifc-dev = <&tasha_ifd>;
1591 vdd-buck-supply = <&pm8994_s4>;
1592 vdd-buck-sido-supply = <&pm8994_s4>;
1593 vdd-tx-supply = <&pm8994_s4>;
1594 vdd-rx-supply = <&pm8994_s4>;
1595 vdd-io-supply = <&pm8994_s4>;
1597 #sound-dai-cells = <1>;
1598 };
1599 };
1600 };
1602 gpu@b00000 {
1603 compatible = "qcom,adreno-530.2", "qcom,adreno";
1604 #stream-id-cells = <16>;
1606 reg = <0xb00000 0x3f000>;
1607 reg-names = "kgsl_3d0_reg_memory";
1609 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1611 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1612 <&mmcc GPU_AHB_CLK>,
1613 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1614 <&gcc GCC_BIMC_GFX_CLK>,
1615 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1617 clock-names = "core",
1618 "iface",
1619 "rbbmtimer",
1620 "mem",
1621 "mem_iface";
1623 power-domains = <&mmcc GPU_GDSC>;
1624 iommus = <&adreno_smmu 0>;
1626 nvmem-cells = <&gpu_speed_bin>;
1627 nvmem-cell-names = "speed_bin";
1629 qcom,gpu-quirk-two-pass-use-wfi;
1630 qcom,gpu-quirk-fault-detect-mask;
1632 operating-points-v2 = <&gpu_opp_table>;
1634 gpu_opp_table: opp-table {
1635 compatible ="operating-points-v2";
1637 /*
1638 * 624Mhz and 560Mhz are only available on speed
1639 * bin (1 << 0). All the rest are available on
1640 * all bins of the hardware
1641 */
1642 opp-624000000 {
1643 opp-hz = /bits/ 64 <624000000>;
1644 opp-supported-hw = <0x01>;
1645 };
1646 opp-560000000 {
1647 opp-hz = /bits/ 64 <560000000>;
1648 opp-supported-hw = <0x01>;
1649 };
1650 opp-510000000 {
1651 opp-hz = /bits/ 64 <510000000>;
1652 opp-supported-hw = <0xFF>;
1653 };
1654 opp-401800000 {
1655 opp-hz = /bits/ 64 <401800000>;
1656 opp-supported-hw = <0xFF>;
1657 };
1658 opp-315000000 {
1659 opp-hz = /bits/ 64 <315000000>;
1660 opp-supported-hw = <0xFF>;
1661 };
1662 opp-214000000 {
1663 opp-hz = /bits/ 64 <214000000>;
1664 opp-supported-hw = <0xFF>;
1665 };
1666 opp-133000000 {
1667 opp-hz = /bits/ 64 <133000000>;
1668 opp-supported-hw = <0xFF>;
1669 };
1670 };
1672 zap-shader {
1673 memory-region = <&zap_shader_region>;
1674 };
1675 };
1677 mdss: mdss@900000 {
1678 compatible = "qcom,mdss";
1680 reg = <0x900000 0x1000>,
1681 <0x9b0000 0x1040>,
1682 <0x9b8000 0x1040>;
1683 reg-names = "mdss_phys",
1684 "vbif_phys",
1685 "vbif_nrt_phys";
1687 power-domains = <&mmcc MDSS_GDSC>;
1688 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1690 interrupt-controller;
1691 #interrupt-cells = <1>;
1693 clocks = <&mmcc MDSS_AHB_CLK>;
1694 clock-names = "iface";
1696 #address-cells = <1>;
1697 #size-cells = <1>;
1698 ranges;
1700 mdp: mdp@901000 {
1701 compatible = "qcom,mdp5";
1702 reg = <0x901000 0x90000>;
1703 reg-names = "mdp_phys";
1705 interrupt-parent = <&mdss>;
1706 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1708 clocks = <&mmcc MDSS_AHB_CLK>,
1709 <&mmcc MDSS_AXI_CLK>,
1710 <&mmcc MDSS_MDP_CLK>,
1711 <&mmcc SMMU_MDP_AXI_CLK>,
1712 <&mmcc MDSS_VSYNC_CLK>;
1713 clock-names = "iface",
1714 "bus",
1715 "core",
1716 "iommu",
1717 "vsync";
1719 iommus = <&mdp_smmu 0>;
1721 ports {
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1725 port@0 {
1726 reg = <0>;
1727 mdp5_intf3_out: endpoint {
1728 remote-endpoint = <&hdmi_in>;
1729 };
1730 };
1731 };
1732 };
1734 hdmi: hdmi-tx@9a0000 {
1735 compatible = "qcom,hdmi-tx-8996";
1736 reg = <0x009a0000 0x50c>,
1737 <0x00070000 0x6158>,
1738 <0x009e0000 0xfff>;
1739 reg-names = "core_physical",
1740 "qfprom_physical",
1741 "hdcp_physical";
1743 interrupt-parent = <&mdss>;
1744 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&mmcc MDSS_MDP_CLK>,
1747 <&mmcc MDSS_AHB_CLK>,
1748 <&mmcc MDSS_HDMI_CLK>,
1749 <&mmcc MDSS_HDMI_AHB_CLK>,
1750 <&mmcc MDSS_EXTPCLK_CLK>;
1751 clock-names =
1752 "mdp_core",
1753 "iface",
1754 "core",
1755 "alt_iface",
1756 "extp";
1758 phys = <&hdmi_phy>;
1759 phy-names = "hdmi_phy";
1760 #sound-dai-cells = <1>;
1762 ports {
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1766 port@0 {
1767 reg = <0>;
1768 hdmi_in: endpoint {
1769 remote-endpoint = <&mdp5_intf3_out>;
1770 };
1771 };
1772 };
1773 };
1775 hdmi_phy: hdmi-phy@9a0600 {
1776 #phy-cells = <0>;
1777 compatible = "qcom,hdmi-phy-8996";
1778 reg = <0x9a0600 0x1c4>,
1779 <0x9a0a00 0x124>,
1780 <0x9a0c00 0x124>,
1781 <0x9a0e00 0x124>,
1782 <0x9a1000 0x124>,
1783 <0x9a1200 0x0c8>;
1784 reg-names = "hdmi_pll",
1785 "hdmi_tx_l0",
1786 "hdmi_tx_l1",
1787 "hdmi_tx_l2",
1788 "hdmi_tx_l3",
1789 "hdmi_phy";
1791 clocks = <&mmcc MDSS_AHB_CLK>,
1792 <&gcc GCC_HDMI_CLKREF_CLK>;
1793 clock-names = "iface",
1794 "ref";
1795 };
1796 };
1797 };
1799 sound: sound {
1800 };
1802 adsp-pil {
1803 compatible = "qcom,msm8996-adsp-pil";
1805 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1806 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1807 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1808 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1809 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1810 interrupt-names = "wdog", "fatal", "ready",
1811 "handover", "stop-ack";
1813 clocks = <&xo_board>;
1814 clock-names = "xo";
1816 memory-region = <&adsp_region>;
1818 qcom,smem-states = <&adsp_smp2p_out 0>;
1819 qcom,smem-state-names = "stop";
1821 smd-edge {
1822 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1824 label = "lpass";
1825 mboxes = <&apcs_glb 8>;
1826 qcom,smd-edge = <1>;
1827 qcom,remote-pid = <2>;
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1830 apr {
1831 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
1832 compatible = "qcom,apr-v2";
1833 qcom,smd-channels = "apr_audio_svc";
1834 qcom,apr-domain = <APR_DOMAIN_ADSP>;
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1838 q6core {
1839 reg = <APR_SVC_ADSP_CORE>;
1840 compatible = "qcom,q6core";
1841 };
1843 q6afe: q6afe {
1844 compatible = "qcom,q6afe";
1845 reg = <APR_SVC_AFE>;
1846 q6afedai: dais {
1847 compatible = "qcom,q6afe-dais";
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1850 #sound-dai-cells = <1>;
1851 hdmi@1 {
1852 reg = <1>;
1853 };
1854 };
1855 };
1857 q6asm: q6asm {
1858 compatible = "qcom,q6asm";
1859 reg = <APR_SVC_ASM>;
1860 q6asmdai: dais {
1861 compatible = "qcom,q6asm-dais";
1862 #sound-dai-cells = <1>;
1863 iommus = <&lpass_q6_smmu 1>;
1864 };
1865 };
1867 q6adm: q6adm {
1868 compatible = "qcom,q6adm";
1869 reg = <APR_SVC_ADM>;
1870 q6routing: routing {
1871 compatible = "qcom,q6adm-routing";
1872 #sound-dai-cells = <0>;
1873 };
1874 };
1875 };
1877 };
1878 };
1880 adsp-smp2p {
1881 compatible = "qcom,smp2p";
1882 qcom,smem = <443>, <429>;
1884 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1886 mboxes = <&apcs_glb 10>;
1888 qcom,local-pid = <0>;
1889 qcom,remote-pid = <2>;
1891 adsp_smp2p_out: master-kernel {
1892 qcom,entry-name = "master-kernel";
1893 #qcom,smem-state-cells = <1>;
1894 };
1896 adsp_smp2p_in: slave-kernel {
1897 qcom,entry-name = "slave-kernel";
1899 interrupt-controller;
1900 #interrupt-cells = <2>;
1901 };
1902 };
1904 modem-smp2p {
1905 compatible = "qcom,smp2p";
1906 qcom,smem = <435>, <428>;
1908 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1910 mboxes = <&apcs_glb 14>;
1912 qcom,local-pid = <0>;
1913 qcom,remote-pid = <1>;
1915 modem_smp2p_out: master-kernel {
1916 qcom,entry-name = "master-kernel";
1917 #qcom,smem-state-cells = <1>;
1918 };
1920 modem_smp2p_in: slave-kernel {
1921 qcom,entry-name = "slave-kernel";
1923 interrupt-controller;
1924 #interrupt-cells = <2>;
1925 };
1926 };
1928 smp2p-slpi {
1929 compatible = "qcom,smp2p";
1930 qcom,smem = <481>, <430>;
1932 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1934 mboxes = <&apcs_glb 26>;
1936 qcom,local-pid = <0>;
1937 qcom,remote-pid = <3>;
1939 slpi_smp2p_in: slave-kernel {
1940 qcom,entry-name = "slave-kernel";
1941 interrupt-controller;
1942 #interrupt-cells = <2>;
1943 };
1945 slpi_smp2p_out: master-kernel {
1946 qcom,entry-name = "master-kernel";
1947 #qcom,smem-state-cells = <1>;
1948 };
1949 };
1951 };
1952 #include "msm8996-pins.dtsi"