1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, Linaro Limited
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
33 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 cpu-idle-states = <&CPU_SLEEP_0>;
37 next-level-cache = <&L2_0>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 next-level-cache = <&L2_0>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 cpu-idle-states = <&CPU_SLEEP_0>;
67 next-level-cache = <&L2_0>;
77 entry-method = "psci";
79 CPU_SLEEP_0: cpu-sleep-0 {
80 compatible = "arm,idle-state";
81 idle-state-name = "standalone-power-collapse";
82 arm,psci-suspend-param = <0x40000003>;
83 entry-latency-us = <125>;
84 exit-latency-us = <180>;
85 min-residency-us = <595>;
93 compatible = "qcom,scm-qcs404", "qcom,scm";
99 device_type = "memory";
100 /* We expect the bootloader to fill in the size */
101 reg = <0 0x80000000 0 0>;
105 compatible = "arm,psci-1.0";
110 #address-cells = <2>;
115 reg = <0 0x85600000 0 0x90000>;
119 smem_region: memory@85f00000 {
120 reg = <0 0x85f00000 0 0x200000>;
125 reg = <0 0x86100000 0 0x300000>;
129 wlan_fw_mem: memory@86400000 {
130 reg = <0 0x86400000 0 0x1c00000>;
134 adsp_fw_mem: memory@88000000 {
135 reg = <0 0x88000000 0 0x1a00000>;
139 cdsp_fw_mem: memory@89a00000 {
140 reg = <0 0x89a00000 0 0x600000>;
144 wlan_msa_mem: memory@8a000000 {
145 reg = <0 0x8a000000 0 0x100000>;
151 compatible = "qcom,glink-rpm";
153 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
154 qcom,rpm-msg-ram = <&rpm_msg_ram>;
155 mboxes = <&apcs_glb 0>;
157 rpm_requests: glink-channel {
158 compatible = "qcom,rpm-qcs404";
159 qcom,glink-channels = "rpm_requests";
161 rpmcc: clock-controller {
162 compatible = "qcom,rpmcc-qcs404";
166 rpmpd: power-controller {
167 compatible = "qcom,qcs404-rpmpd";
168 #power-domain-cells = <1>;
169 operating-points-v2 = <&rpmpd_opp_table>;
171 rpmpd_opp_table: opp-table {
172 compatible = "operating-points-v2";
174 rpmpd_opp_ret: opp1 {
178 rpmpd_opp_ret_plus: opp2 {
182 rpmpd_opp_min_svs: opp3 {
186 rpmpd_opp_low_svs: opp4 {
190 rpmpd_opp_svs: opp5 {
194 rpmpd_opp_svs_plus: opp6 {
198 rpmpd_opp_nom: opp7 {
202 rpmpd_opp_nom_plus: opp8 {
206 rpmpd_opp_turbo: opp9 {
210 rpmpd_opp_turbo_no_cpr: opp10 {
214 rpmpd_opp_turbo_plus: opp11 {
223 compatible = "qcom,smem";
225 memory-region = <&smem_region>;
226 qcom,rpm-msg-ram = <&rpm_msg_ram>;
228 hwlocks = <&tcsr_mutex 3>;
232 compatible = "qcom,tcsr-mutex";
233 syscon = <&tcsr_mutex_regs 0 0x1000>;
238 #address-cells = <1>;
240 ranges = <0 0 0 0xffffffff>;
241 compatible = "simple-bus";
243 turingcc: clock-controller@800000 {
244 compatible = "qcom,qcs404-turingcc";
245 reg = <0x00800000 0x30000>;
246 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
254 rpm_msg_ram: memory@60000 {
255 compatible = "qcom,rpm-msg-ram";
256 reg = <0x00060000 0x6000>;
259 qfprom: qfprom@a4000 {
260 compatible = "qcom,qfprom";
261 reg = <0x000a4000 0x1000>;
262 #address-cells = <1>;
264 tsens_caldata: caldata@d0 {
270 compatible = "qcom,prng-ee";
271 reg = <0x000e3000 0x1000>;
272 clocks = <&gcc GCC_PRNG_AHB_CLK>;
273 clock-names = "core";
276 tsens: thermal-sensor@4a9000 {
277 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
278 reg = <0x004a9000 0x1000>, /* TM */
279 <0x004a8000 0x1000>; /* SROT */
280 nvmem-cells = <&tsens_caldata>;
281 nvmem-cell-names = "calib";
282 #qcom,sensors = <10>;
283 #thermal-sensor-cells = <1>;
286 remoteproc_cdsp: remoteproc@b00000 {
287 compatible = "qcom,qcs404-cdsp-pas";
288 reg = <0x00b00000 0x4040>;
290 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
291 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
292 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
293 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
294 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
295 interrupt-names = "wdog", "fatal", "ready",
296 "handover", "stop-ack";
298 clocks = <&xo_board>,
299 <&gcc GCC_CDSP_CFG_AHB_CLK>,
300 <&gcc GCC_CDSP_TBU_CLK>,
301 <&gcc GCC_BIMC_CDSP_CLK>,
302 <&turingcc TURING_WRAPPER_AON_CLK>,
303 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
304 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
305 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
315 resets = <&gcc GCC_CDSP_RESTART>;
316 reset-names = "restart";
318 qcom,halt-regs = <&tcsr 0x19004>;
320 memory-region = <&cdsp_fw_mem>;
322 qcom,smem-states = <&cdsp_smp2p_out 0>;
323 qcom,smem-state-names = "stop";
328 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
330 qcom,remote-pid = <5>;
331 mboxes = <&apcs_glb 12>;
337 tlmm: pinctrl@1000000 {
338 compatible = "qcom,qcs404-pinctrl";
339 reg = <0x01000000 0x200000>,
340 <0x01300000 0x200000>,
341 <0x07b00000 0x200000>;
342 reg-names = "south", "north", "east";
343 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
344 gpio-ranges = <&tlmm 0 0 120>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
350 blsp1_i2c0_default: blsp1-i2c0-default {
351 pins = "gpio32", "gpio33";
352 function = "blsp_i2c0";
355 blsp1_i2c1_default: blsp1-i2c1-default {
356 pins = "gpio24", "gpio25";
357 function = "blsp_i2c1";
360 blsp1_i2c2_default: blsp1-i2c2-default {
363 function = "blsp_i2c_sda_a2";
368 function = "blsp_i2c_scl_a2";
372 blsp1_i2c3_default: blsp1-i2c3-default {
373 pins = "gpio84", "gpio85";
374 function = "blsp_i2c3";
377 blsp1_i2c4_default: blsp1-i2c4-default {
378 pins = "gpio117", "gpio118";
379 function = "blsp_i2c4";
382 blsp1_uart0_default: blsp1-uart0-default {
383 pins = "gpio30", "gpio31", "gpio32", "gpio33";
384 function = "blsp_uart0";
387 blsp1_uart1_default: blsp1-uart1-default {
388 pins = "gpio22", "gpio23";
389 function = "blsp_uart1";
392 blsp1_uart2_default: blsp1-uart2-default {
395 function = "blsp_uart_rx_a2";
400 function = "blsp_uart_tx_a2";
404 blsp1_uart3_default: blsp1-uart3-default {
405 pins = "gpio82", "gpio83", "gpio84", "gpio85";
406 function = "blsp_uart3";
409 blsp2_i2c0_default: blsp2-i2c0-default {
410 pins = "gpio28", "gpio29";
411 function = "blsp_i2c5";
414 blsp1_spi0_default: blsp1-spi0-default {
415 pins = "gpio30", "gpio31", "gpio32", "gpio33";
416 function = "blsp_spi0";
419 blsp1_spi1_default: blsp1-spi1-default {
420 pins = "gpio22", "gpio23", "gpio24", "gpio25";
421 function = "blsp_spi1";
424 blsp1_spi2_default: blsp1-spi2-default {
425 pins = "gpio17", "gpio18", "gpio19", "gpio20";
426 function = "blsp_spi2";
429 blsp1_spi3_default: blsp1-spi3-default {
430 pins = "gpio82", "gpio83", "gpio84", "gpio85";
431 function = "blsp_spi3";
434 blsp1_spi4_default: blsp1-spi4-default {
435 pins = "gpio37", "gpio38", "gpio117", "gpio118";
436 function = "blsp_spi4";
439 blsp2_spi0_default: blsp2-spi0-default {
440 pins = "gpio26", "gpio27", "gpio28", "gpio29";
441 function = "blsp_spi5";
444 blsp2_uart0_default: blsp2-uart0-default {
445 pins = "gpio26", "gpio27", "gpio28", "gpio29";
446 function = "blsp_uart5";
450 gcc: clock-controller@1800000 {
451 compatible = "qcom,gcc-qcs404";
452 reg = <0x01800000 0x80000>;
456 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
457 assigned-clock-rates = <19200000>;
460 tcsr_mutex_regs: syscon@1905000 {
461 compatible = "syscon";
462 reg = <0x01905000 0x20000>;
465 tcsr: syscon@1937000 {
466 compatible = "syscon";
467 reg = <0x01937000 0x25000>;
470 spmi_bus: spmi@200f000 {
471 compatible = "qcom,spmi-pmic-arb";
472 reg = <0x0200f000 0x001000>,
473 <0x02400000 0x800000>,
474 <0x02c00000 0x800000>,
475 <0x03800000 0x200000>,
476 <0x0200a000 0x002100>;
477 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
478 interrupt-names = "periph_irq";
479 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <4>;
488 remoteproc_wcss: remoteproc@7400000 {
489 compatible = "qcom,qcs404-wcss-pas";
490 reg = <0x07400000 0x4040>;
492 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
493 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
494 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
495 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
496 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
497 interrupt-names = "wdog", "fatal", "ready",
498 "handover", "stop-ack";
500 clocks = <&xo_board>;
503 memory-region = <&wlan_fw_mem>;
505 qcom,smem-states = <&wcss_smp2p_out 0>;
506 qcom,smem-state-names = "stop";
511 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
513 qcom,remote-pid = <1>;
514 mboxes = <&apcs_glb 16>;
520 pcie_phy: phy@7786000 {
521 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
522 reg = <0x07786000 0xb8>;
524 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
525 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
527 reset-names = "phy", "pipe";
529 clock-output-names = "pcie_0_pipe_clk";
535 sdcc1: sdcc@7804000 {
536 compatible = "qcom,sdhci-msm-v5";
537 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
538 reg-names = "hc_mem", "cmdq_mem";
540 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "hc_irq", "pwr_irq";
544 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
545 <&gcc GCC_SDCC1_AHB_CLK>,
547 clock-names = "core", "iface", "xo";
552 blsp1_dma: dma@7884000 {
553 compatible = "qcom,bam-v1.7.0";
554 reg = <0x07884000 0x25000>;
555 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
557 clock-names = "bam_clk";
563 blsp1_uart0: serial@78af000 {
564 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
565 reg = <0x078af000 0x200>;
566 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
568 clock-names = "core", "iface";
569 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
570 dma-names = "rx", "tx";
571 pinctrl-names = "default";
572 pinctrl-0 = <&blsp1_uart0_default>;
576 blsp1_uart1: serial@78b0000 {
577 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
578 reg = <0x078b0000 0x200>;
579 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
581 clock-names = "core", "iface";
582 dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
583 dma-names = "rx", "tx";
584 pinctrl-names = "default";
585 pinctrl-0 = <&blsp1_uart1_default>;
589 blsp1_uart2: serial@78b1000 {
590 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
591 reg = <0x078b1000 0x200>;
592 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
594 clock-names = "core", "iface";
595 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
596 dma-names = "rx", "tx";
597 pinctrl-names = "default";
598 pinctrl-0 = <&blsp1_uart2_default>;
602 ethernet: ethernet@7a80000 {
603 compatible = "qcom,qcs404-ethqos";
604 reg = <0x07a80000 0x10000>,
606 reg-names = "stmmaceth", "rgmii";
607 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
608 clocks = <&gcc GCC_ETH_AXI_CLK>,
609 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
610 <&gcc GCC_ETH_PTP_CLK>,
611 <&gcc GCC_ETH_RGMII_CLK>;
612 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
614 interrupt-names = "macirq", "eth_lpi";
617 rx-fifo-depth = <4096>;
618 tx-fifo-depth = <4096>;
624 compatible = "qcom,wcn3990-wifi";
625 reg = <0xa000000 0x800000>;
626 reg-names = "membase";
627 memory-region = <&wlan_msa_mem>;
628 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
643 blsp1_uart3: serial@78b2000 {
644 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
645 reg = <0x078b2000 0x200>;
646 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
648 clock-names = "core", "iface";
649 dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
650 dma-names = "rx", "tx";
651 pinctrl-names = "default";
652 pinctrl-0 = <&blsp1_uart3_default>;
656 blsp1_i2c0: i2c@78b5000 {
657 compatible = "qcom,i2c-qup-v2.2.1";
658 reg = <0x078b5000 0x600>;
659 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
661 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
662 clock-names = "iface", "core";
663 pinctrl-names = "default";
664 pinctrl-0 = <&blsp1_i2c0_default>;
665 #address-cells = <1>;
670 blsp1_spi0: spi@78b5000 {
671 compatible = "qcom,spi-qup-v2.2.1";
672 reg = <0x078b5000 0x600>;
673 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
675 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
676 clock-names = "iface", "core";
677 pinctrl-names = "default";
678 pinctrl-0 = <&blsp1_spi0_default>;
679 #address-cells = <1>;
684 blsp1_i2c1: i2c@78b6000 {
685 compatible = "qcom,i2c-qup-v2.2.1";
686 reg = <0x078b6000 0x600>;
687 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
689 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
690 clock-names = "iface", "core";
691 pinctrl-names = "default";
692 pinctrl-0 = <&blsp1_i2c1_default>;
693 #address-cells = <1>;
698 blsp1_spi1: spi@78b6000 {
699 compatible = "qcom,spi-qup-v2.2.1";
700 reg = <0x078b6000 0x600>;
701 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
703 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
704 clock-names = "iface", "core";
705 pinctrl-names = "default";
706 pinctrl-0 = <&blsp1_spi1_default>;
707 #address-cells = <1>;
712 blsp1_i2c2: i2c@78b7000 {
713 compatible = "qcom,i2c-qup-v2.2.1";
714 reg = <0x078b7000 0x600>;
715 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
717 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
718 clock-names = "iface", "core";
719 pinctrl-names = "default";
720 pinctrl-0 = <&blsp1_i2c2_default>;
721 #address-cells = <1>;
726 blsp1_spi2: spi@78b7000 {
727 compatible = "qcom,spi-qup-v2.2.1";
728 reg = <0x078b7000 0x600>;
729 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
731 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
732 clock-names = "iface", "core";
733 pinctrl-names = "default";
734 pinctrl-0 = <&blsp1_spi2_default>;
735 #address-cells = <1>;
740 blsp1_i2c3: i2c@78b8000 {
741 compatible = "qcom,i2c-qup-v2.2.1";
742 reg = <0x078b8000 0x600>;
743 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
745 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
746 clock-names = "iface", "core";
747 pinctrl-names = "default";
748 pinctrl-0 = <&blsp1_i2c3_default>;
749 #address-cells = <1>;
754 blsp1_spi3: spi@78b8000 {
755 compatible = "qcom,spi-qup-v2.2.1";
756 reg = <0x078b8000 0x600>;
757 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
759 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
760 clock-names = "iface", "core";
761 pinctrl-names = "default";
762 pinctrl-0 = <&blsp1_spi3_default>;
763 #address-cells = <1>;
768 blsp1_i2c4: i2c@78b9000 {
769 compatible = "qcom,i2c-qup-v2.2.1";
770 reg = <0x078b9000 0x600>;
771 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
773 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
774 clock-names = "iface", "core";
775 pinctrl-names = "default";
776 pinctrl-0 = <&blsp1_i2c4_default>;
777 #address-cells = <1>;
782 blsp1_spi4: spi@78b9000 {
783 compatible = "qcom,spi-qup-v2.2.1";
784 reg = <0x078b9000 0x600>;
785 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
787 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
788 clock-names = "iface", "core";
789 pinctrl-names = "default";
790 pinctrl-0 = <&blsp1_spi4_default>;
791 #address-cells = <1>;
796 blsp2_dma: dma@7ac4000 {
797 compatible = "qcom,bam-v1.7.0";
798 reg = <0x07ac4000 0x17000>;
799 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
801 clock-names = "bam_clk";
807 blsp2_uart0: serial@7aef000 {
808 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
809 reg = <0x07aef000 0x200>;
810 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
812 clock-names = "core", "iface";
813 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
814 dma-names = "rx", "tx";
815 pinctrl-names = "default";
816 pinctrl-0 = <&blsp2_uart0_default>;
820 blsp2_i2c0: i2c@7af5000 {
821 compatible = "qcom,i2c-qup-v2.2.1";
822 reg = <0x07af5000 0x600>;
823 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
825 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
826 clock-names = "iface", "core";
827 pinctrl-names = "default";
828 pinctrl-0 = <&blsp2_i2c0_default>;
829 #address-cells = <1>;
834 blsp2_spi0: spi@7af5000 {
835 compatible = "qcom,spi-qup-v2.2.1";
836 reg = <0x07af5000 0x600>;
837 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
839 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
840 clock-names = "iface", "core";
841 pinctrl-names = "default";
842 pinctrl-0 = <&blsp2_spi0_default>;
843 #address-cells = <1>;
848 intc: interrupt-controller@b000000 {
849 compatible = "qcom,msm-qgic2";
850 interrupt-controller;
851 #interrupt-cells = <3>;
852 reg = <0x0b000000 0x1000>,
856 apcs_glb: mailbox@b011000 {
857 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
858 reg = <0x0b011000 0x1000>;
863 #address-cells = <1>;
866 compatible = "arm,armv7-timer-mem";
867 reg = <0x0b120000 0x1000>;
868 clock-frequency = <19200000>;
872 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
874 reg = <0x0b121000 0x1000>,
880 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
881 reg = <0x0b123000 0x1000>;
887 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
888 reg = <0x0b124000 0x1000>;
894 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
895 reg = <0x0b125000 0x1000>;
901 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
902 reg = <0x0b126000 0x1000>;
908 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
909 reg = <0xb127000 0x1000>;
915 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
916 reg = <0x0b128000 0x1000>;
921 remoteproc_adsp: remoteproc@c700000 {
922 compatible = "qcom,qcs404-adsp-pas";
923 reg = <0x0c700000 0x4040>;
925 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
926 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
927 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
928 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
929 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
930 interrupt-names = "wdog", "fatal", "ready",
931 "handover", "stop-ack";
933 clocks = <&xo_board>;
936 memory-region = <&adsp_fw_mem>;
938 qcom,smem-states = <&adsp_smp2p_out 0>;
939 qcom,smem-state-names = "stop";
944 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
946 qcom,remote-pid = <2>;
947 mboxes = <&apcs_glb 8>;
954 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
955 reg = <0x10000000 0xf1d>,
959 reg-names = "dbi", "elbi", "parf", "config";
961 linux,pci-domain = <0>;
962 bus-range = <0x00 0xff>;
964 #address-cells = <3>;
967 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
968 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
970 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "msi";
972 #interrupt-cells = <1>;
973 interrupt-map-mask = <0 0 0 0x7>;
974 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
975 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
976 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
977 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
978 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
979 <&gcc GCC_PCIE_0_AUX_CLK>,
980 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
981 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
982 clock-names = "iface", "aux", "master_bus", "slave_bus";
988 <&gcc GCC_PCIE_0_BCR>,
990 reset-names = "axi_m",
998 phy-names = "pciephy";
1000 status = "disabled";
1005 compatible = "arm,armv8-timer";
1006 interrupts = <GIC_PPI 2 0xff08>,
1013 compatible = "qcom,smp2p";
1014 qcom,smem = <443>, <429>;
1015 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1016 mboxes = <&apcs_glb 10>;
1017 qcom,local-pid = <0>;
1018 qcom,remote-pid = <2>;
1020 adsp_smp2p_out: master-kernel {
1021 qcom,entry-name = "master-kernel";
1022 #qcom,smem-state-cells = <1>;
1025 adsp_smp2p_in: slave-kernel {
1026 qcom,entry-name = "slave-kernel";
1027 interrupt-controller;
1028 #interrupt-cells = <2>;
1033 compatible = "qcom,smp2p";
1034 qcom,smem = <94>, <432>;
1035 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1036 mboxes = <&apcs_glb 14>;
1037 qcom,local-pid = <0>;
1038 qcom,remote-pid = <5>;
1040 cdsp_smp2p_out: master-kernel {
1041 qcom,entry-name = "master-kernel";
1042 #qcom,smem-state-cells = <1>;
1045 cdsp_smp2p_in: slave-kernel {
1046 qcom,entry-name = "slave-kernel";
1047 interrupt-controller;
1048 #interrupt-cells = <2>;
1053 compatible = "qcom,smp2p";
1054 qcom,smem = <435>, <428>;
1055 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1056 mboxes = <&apcs_glb 18>;
1057 qcom,local-pid = <0>;
1058 qcom,remote-pid = <1>;
1060 wcss_smp2p_out: master-kernel {
1061 qcom,entry-name = "master-kernel";
1062 #qcom,smem-state-cells = <1>;
1065 wcss_smp2p_in: slave-kernel {
1066 qcom,entry-name = "slave-kernel";
1067 interrupt-controller;
1068 #interrupt-cells = <2>;
1074 polling-delay-passive = <250>;
1075 polling-delay = <1000>;
1077 thermal-sensors = <&tsens 0>;
1080 aoss_alert0: trip-point@0 {
1081 temperature = <105000>;
1082 hysteresis = <2000>;
1089 polling-delay-passive = <250>;
1090 polling-delay = <1000>;
1092 thermal-sensors = <&tsens 1>;
1095 q6_hvx_alert0: trip-point@0 {
1096 temperature = <105000>;
1097 hysteresis = <2000>;
1104 polling-delay-passive = <250>;
1105 polling-delay = <1000>;
1107 thermal-sensors = <&tsens 2>;
1110 lpass_alert0: trip-point@0 {
1111 temperature = <105000>;
1112 hysteresis = <2000>;
1119 polling-delay-passive = <250>;
1120 polling-delay = <1000>;
1122 thermal-sensors = <&tsens 3>;
1125 wlan_alert0: trip-point@0 {
1126 temperature = <105000>;
1127 hysteresis = <2000>;
1134 polling-delay-passive = <250>;
1135 polling-delay = <1000>;
1137 thermal-sensors = <&tsens 4>;
1140 cluster_alert0: trip-point@0 {
1141 temperature = <95000>;
1142 hysteresis = <2000>;
1145 cluster_alert1: trip-point@1 {
1146 temperature = <105000>;
1147 hysteresis = <2000>;
1150 cluster_crit: cluster_crit {
1151 temperature = <120000>;
1152 hysteresis = <2000>;
1158 trip = <&cluster_alert1>;
1159 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1160 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1161 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1162 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1168 polling-delay-passive = <250>;
1169 polling-delay = <1000>;
1171 thermal-sensors = <&tsens 5>;
1174 cpu0_alert0: trip-point@0 {
1175 temperature = <95000>;
1176 hysteresis = <2000>;
1179 cpu0_alert1: trip-point@1 {
1180 temperature = <105000>;
1181 hysteresis = <2000>;
1184 cpu0_crit: cpu_crit {
1185 temperature = <120000>;
1186 hysteresis = <2000>;
1192 trip = <&cpu0_alert1>;
1193 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1194 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1195 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1196 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1202 polling-delay-passive = <250>;
1203 polling-delay = <1000>;
1205 thermal-sensors = <&tsens 6>;
1208 cpu1_alert0: trip-point@0 {
1209 temperature = <95000>;
1210 hysteresis = <2000>;
1213 cpu1_alert1: trip-point@1 {
1214 temperature = <105000>;
1215 hysteresis = <2000>;
1218 cpu1_crit: cpu_crit {
1219 temperature = <120000>;
1220 hysteresis = <2000>;
1226 trip = <&cpu1_alert1>;
1227 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1228 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1229 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1230 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1236 polling-delay-passive = <250>;
1237 polling-delay = <1000>;
1239 thermal-sensors = <&tsens 7>;
1242 cpu2_alert0: trip-point@0 {
1243 temperature = <95000>;
1244 hysteresis = <2000>;
1247 cpu2_alert1: trip-point@1 {
1248 temperature = <105000>;
1249 hysteresis = <2000>;
1252 cpu2_crit: cpu_crit {
1253 temperature = <120000>;
1254 hysteresis = <2000>;
1260 trip = <&cpu2_alert1>;
1261 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1262 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1263 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1264 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1270 polling-delay-passive = <250>;
1271 polling-delay = <1000>;
1273 thermal-sensors = <&tsens 8>;
1276 cpu3_alert0: trip-point@0 {
1277 temperature = <95000>;
1278 hysteresis = <2000>;
1281 cpu3_alert1: trip-point@1 {
1282 temperature = <105000>;
1283 hysteresis = <2000>;
1286 cpu3_crit: cpu_crit {
1287 temperature = <120000>;
1288 hysteresis = <2000>;
1294 trip = <&cpu3_alert1>;
1295 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1296 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1297 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1298 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1304 polling-delay-passive = <250>;
1305 polling-delay = <1000>;
1307 thermal-sensors = <&tsens 9>;
1310 gpu_alert0: trip-point@0 {
1311 temperature = <95000>;
1312 hysteresis = <2000>;