arch/arm64/boot/dts/realtek/rtd1295.dtsi

   1 /*
   2  * Realtek RTD1295 SoC
   3  *
   4  * Copyright (c) 2016-2017 Andreas Färber
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   7  */
   8
   9 #include "rtd129x.dtsi"
  10
  11 / {
  12         compatible = "realtek,rtd1295";
  13
  14         cpus {
  15                 #address-cells = <2>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a53";
  21                         reg = <0x0 0x0>;
  22                         next-level-cache = <&l2>;
  23                 };
  24
  25                 cpu1: cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a53";
  28                         reg = <0x0 0x1>;
  29                         next-level-cache = <&l2>;
  30                 };
  31
  32                 cpu2: cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53";
  35                         reg = <0x0 0x2>;
  36                         next-level-cache = <&l2>;
  37                 };
  38
  39                 cpu3: cpu@3 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         reg = <0x0 0x3>;
  43                         next-level-cache = <&l2>;
  44                 };
  45
  46                 l2: l2-cache {
  47                         compatible = "cache";
  48                 };
  49         };
  50
  51         reserved-memory {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 tee@10100000 {
  57                         reg = <0x10100000 0xf00000>;
  58                         no-map;
  59                 };
  60         };
  61
  62         timer {
  63                 compatible = "arm,armv8-timer";
  64                 interrupts = <GIC_PPI 13
  65                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  66                              <GIC_PPI 14
  67                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  68                              <GIC_PPI 11
  69                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  70                              <GIC_PPI 10
  71                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
  72         };
  73 };
  74
  75 &arm_pmu {
  76         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  77 };