arch/arm64/boot/dts/realtek/rtd129x.dtsi

   1 /*
   2  * Realtek RTD1293/RTD1295/RTD1296 SoC
   3  *
   4  * Copyright (c) 2016-2017 Andreas Färber
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   7  */
   8
   9 /memreserve/    0x0000000000000000 0x0000000000030000;
  10 /memreserve/    0x000000000001f000 0x0000000000001000;
  11 /memreserve/    0x0000000000030000 0x00000000000d0000;
  12 /memreserve/    0x0000000001b00000 0x00000000004be000;
  13 /memreserve/    0x0000000001ffe000 0x0000000000004000;
  14
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         interrupt-parent = <&gic>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         arm_pmu: arm-pmu {
  23                 compatible = "arm,cortex-a53-pmu";
  24                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  25         };
  26
  27         soc {
  28                 compatible = "simple-bus";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 /* Exclude up to 2 GiB of RAM */
  32                 ranges = <0x80000000 0x80000000 0x80000000>;
  33
  34                 uart0: serial@98007800 {
  35                         compatible = "snps,dw-apb-uart";
  36                         reg = <0x98007800 0x400>;
  37                         reg-shift = <2>;
  38                         reg-io-width = <4>;
  39                         clock-frequency = <27000000>;
  40                         status = "disabled";
  41                 };
  42
  43                 uart1: serial@9801b200 {
  44                         compatible = "snps,dw-apb-uart";
  45                         reg = <0x9801b200 0x100>;
  46                         reg-shift = <2>;
  47                         reg-io-width = <4>;
  48                         clock-frequency = <432000000>;
  49                         status = "disabled";
  50                 };
  51
  52                 uart2: serial@9801b400 {
  53                         compatible = "snps,dw-apb-uart";
  54                         reg = <0x9801b400 0x100>;
  55                         reg-shift = <2>;
  56                         reg-io-width = <4>;
  57                         clock-frequency = <432000000>;
  58                         status = "disabled";
  59                 };
  60
  61                 gic: interrupt-controller@ff011000 {
  62                         compatible = "arm,gic-400";
  63                         reg = <0xff011000 0x1000>,
  64                               <0xff012000 0x2000>,
  65                               <0xff014000 0x2000>,
  66                               <0xff016000 0x2000>;
  67                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  68                         interrupt-controller;
  69                         #interrupt-cells = <3>;
  70                 };
  71         };
  72 };