arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Gru (and derivatives) board device tree source
   4  *
   5  * Copyright 2016-2017 Google, Inc
   6  */
   7
   8 #include <dt-bindings/input/input.h>
   9 #include "rk3399.dtsi"
  10 #include "rk3399-op1-opp.dtsi"
  11
  12 / {
  13         chosen {
  14                 stdout-path = "serial2:115200n8";
  15         };
  16
  17         /*
  18          * Power Tree
  19          *
  20          * In general an attempt is made to include all rails called out by
  21          * the schematic as long as those rails interact in some way with
  22          * the AP.  AKA:
  23          * - Rails that only connect to the EC (or devices that the EC talks to)
  24          *   are not included.
  25          * - Rails _are_ included if the rails go to the AP even if the AP
  26          *   doesn't currently care about them / they are always on.  The idea
  27          *   here is that it makes it easier to map to the schematic or extend
  28          *   later.
  29          *
  30          * If two rails are substantially the same from the AP's point of
  31          * view, though, we won't create a full fixed regulator.  We'll just
  32          * put the child rail as an alias of the parent rail.  Sometimes rails
  33          * look the same to the AP because one of these is true:
  34          * - The EC controls the enable and the EC always enables a rail as
  35          *   long as the AP is running.
  36          * - The rails are actually connected to each other by a jumper and
  37          *   the distinction is just there to add clarity/flexibility to the
  38          *   schematic.
  39          */
  40
  41         ppvar_sys: ppvar-sys {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "ppvar_sys";
  44                 regulator-always-on;
  45                 regulator-boot-on;
  46         };
  47
  48         pp1200_lpddr: pp1200-lpddr {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "pp1200_lpddr";
  51
  52                 /* EC turns on w/ lpddr_pwr_en; always on for AP */
  53                 regulator-always-on;
  54                 regulator-boot-on;
  55                 regulator-min-microvolt = <1200000>;
  56                 regulator-max-microvolt = <1200000>;
  57
  58                 vin-supply = <&ppvar_sys>;
  59         };
  60
  61         pp1800: pp1800 {
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "pp1800";
  64
  65                 /* Always on when ppvar_sys shows power good */
  66                 regulator-always-on;
  67                 regulator-boot-on;
  68                 regulator-min-microvolt = <1800000>;
  69                 regulator-max-microvolt = <1800000>;
  70
  71                 vin-supply = <&ppvar_sys>;
  72         };
  73
  74         pp3300: pp3300 {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "pp3300";
  77
  78                 /* Always on; plain and simple */
  79                 regulator-always-on;
  80                 regulator-boot-on;
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83
  84                 vin-supply = <&ppvar_sys>;
  85         };
  86
  87         pp5000: pp5000 {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "pp5000";
  90
  91                 /* EC turns on w/ pp5000_en; always on for AP */
  92                 regulator-always-on;
  93                 regulator-boot-on;
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96
  97                 vin-supply = <&ppvar_sys>;
  98         };
  99
 100         ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
 101                 compatible = "pwm-regulator";
 102                 regulator-name = "ppvar_bigcpu_pwm";
 103
 104                 pwms = <&pwm1 0 3337 0>;
 105                 pwm-supply = <&ppvar_sys>;
 106                 pwm-dutycycle-range = <100 0>;
 107                 pwm-dutycycle-unit = <100>;
 108
 109                 /* EC turns on w/ ap_core_en; always on for AP */
 110                 regulator-always-on;
 111                 regulator-boot-on;
 112                 regulator-min-microvolt = <800107>;
 113                 regulator-max-microvolt = <1302232>;
 114         };
 115
 116         ppvar_bigcpu: ppvar-bigcpu {
 117                 compatible = "vctrl-regulator";
 118                 regulator-name = "ppvar_bigcpu";
 119
 120                 regulator-min-microvolt = <800107>;
 121                 regulator-max-microvolt = <1302232>;
 122
 123                 ctrl-supply = <&ppvar_bigcpu_pwm>;
 124                 ctrl-voltage-range = <800107 1302232>;
 125
 126                 regulator-settling-time-up-us = <322>;
 127         };
 128
 129         ppvar_litcpu_pwm: ppvar-litcpu-pwm {
 130                 compatible = "pwm-regulator";
 131                 regulator-name = "ppvar_litcpu_pwm";
 132
 133                 pwms = <&pwm2 0 3337 0>;
 134                 pwm-supply = <&ppvar_sys>;
 135                 pwm-dutycycle-range = <100 0>;
 136                 pwm-dutycycle-unit = <100>;
 137
 138                 /* EC turns on w/ ap_core_en; always on for AP */
 139                 regulator-always-on;
 140                 regulator-boot-on;
 141                 regulator-min-microvolt = <797743>;
 142                 regulator-max-microvolt = <1307837>;
 143         };
 144
 145         ppvar_litcpu: ppvar-litcpu {
 146                 compatible = "vctrl-regulator";
 147                 regulator-name = "ppvar_litcpu";
 148
 149                 regulator-min-microvolt = <797743>;
 150                 regulator-max-microvolt = <1307837>;
 151
 152                 ctrl-supply = <&ppvar_litcpu_pwm>;
 153                 ctrl-voltage-range = <797743 1307837>;
 154
 155                 regulator-settling-time-up-us = <384>;
 156         };
 157
 158         ppvar_gpu_pwm: ppvar-gpu-pwm {
 159                 compatible = "pwm-regulator";
 160                 regulator-name = "ppvar_gpu_pwm";
 161
 162                 pwms = <&pwm0 0 3337 0>;
 163                 pwm-supply = <&ppvar_sys>;
 164                 pwm-dutycycle-range = <100 0>;
 165                 pwm-dutycycle-unit = <100>;
 166
 167                 /* EC turns on w/ ap_core_en; always on for AP */
 168                 regulator-always-on;
 169                 regulator-boot-on;
 170                 regulator-min-microvolt = <786384>;
 171                 regulator-max-microvolt = <1217747>;
 172         };
 173
 174         ppvar_gpu: ppvar-gpu {
 175                 compatible = "vctrl-regulator";
 176                 regulator-name = "ppvar_gpu";
 177
 178                 regulator-min-microvolt = <786384>;
 179                 regulator-max-microvolt = <1217747>;
 180
 181                 ctrl-supply = <&ppvar_gpu_pwm>;
 182                 ctrl-voltage-range = <786384 1217747>;
 183
 184                 regulator-settling-time-up-us = <390>;
 185         };
 186
 187         /* EC turns on w/ pp900_ddrpll_en */
 188         pp900_ddrpll: pp900-ap {
 189         };
 190
 191         /* EC turns on w/ pp900_pll_en */
 192         pp900_pll: pp900-ap {
 193         };
 194
 195         /* EC turns on w/ pp900_pmu_en */
 196         pp900_pmu: pp900-ap {
 197         };
 198
 199         /* EC turns on w/ pp1800_s0_en_l */
 200         pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
 201         };
 202
 203         /* EC turns on w/ pp1800_avdd_en_l */
 204         pp1800_avdd: pp1800 {
 205         };
 206
 207         /* EC turns on w/ pp1800_lid_en_l */
 208         pp1800_lid: pp1800_mic: pp1800 {
 209         };
 210
 211         /* EC turns on w/ lpddr_pwr_en */
 212         pp1800_lpddr: pp1800 {
 213         };
 214
 215         /* EC turns on w/ pp1800_pmu_en_l */
 216         pp1800_pmu: pp1800 {
 217         };
 218
 219         /* EC turns on w/ pp1800_usb_en_l */
 220         pp1800_usb: pp1800 {
 221         };
 222
 223         pp3000_sd_slot: pp3000-sd-slot {
 224                 compatible = "regulator-fixed";
 225                 regulator-name = "pp3000_sd_slot";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&sd_slot_pwr_en>;
 228
 229                 enable-active-high;
 230                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 231
 232                 vin-supply = <&pp3000>;
 233         };
 234
 235         /*
 236          * Technically, this is a small abuse of 'regulator-gpio'; this
 237          * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
 238          * always on though, so it is sufficient to simply control the mux
 239          * here.
 240          */
 241         ppvar_sd_card_io: ppvar-sd-card-io {
 242                 compatible = "regulator-gpio";
 243                 regulator-name = "ppvar_sd_card_io";
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
 246
 247                 enable-active-high;
 248                 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 249                 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
 250                 states = <1800000 0x1
 251                           3000000 0x0>;
 252
 253                 regulator-min-microvolt = <1800000>;
 254                 regulator-max-microvolt = <3000000>;
 255         };
 256
 257         /* EC turns on w/ pp3300_trackpad_en_l */
 258         pp3300_trackpad: pp3300-trackpad {
 259         };
 260
 261         /* EC turns on w/ usb_a_en */
 262         pp5000_usb_a_vbus: pp5000 {
 263         };
 264
 265         ap_rtc_clk: ap-rtc-clk {
 266                 compatible = "fixed-clock";
 267                 clock-frequency = <32768>;
 268                 clock-output-names = "xin32k";
 269                 #clock-cells = <0>;
 270         };
 271
 272         max98357a: max98357a {
 273                 compatible = "maxim,max98357a";
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&sdmode_en>;
 276                 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 277                 sdmode-delay = <2>;
 278                 #sound-dai-cells = <0>;
 279                 status = "okay";
 280         };
 281
 282         sound: sound {
 283                 compatible = "rockchip,rk3399-gru-sound";
 284                 rockchip,cpu = <&i2s0 &i2s2>;
 285         };
 286 };
 287
 288 &cdn_dp {
 289         status = "okay";
 290 };
 291
 292 /*
 293  * Set some suspend operating points to avoid OVP in suspend
 294  *
 295  * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
 296  * from wherever they're at back to the "default" operating point (whatever
 297  * voltage we get when we set the PWM pins to "input").
 298  *
 299  * This quick transition under light load has the possibility to trigger the
 300  * regulator "over voltage protection" (OVP).
 301  *
 302  * To make extra certain that we don't hit this OVP at suspend time, we'll
 303  * transition to a voltage that's much closer to the default (~1.0 V) so that
 304  * there will not be a big jump.  Technically we only need to get within 200 mV
 305  * of the default voltage, but the speed here should be fast enough and we need
 306  * suspend/resume to be rock solid.
 307  */
 308
 309 &cluster0_opp {
 310         opp05 {
 311                 opp-suspend;
 312         };
 313 };
 314
 315 &cluster1_opp {
 316         opp06 {
 317                 opp-suspend;
 318         };
 319 };
 320
 321 &cpu_l0 {
 322         cpu-supply = <&ppvar_litcpu>;
 323 };
 324
 325 &cpu_l1 {
 326         cpu-supply = <&ppvar_litcpu>;
 327 };
 328
 329 &cpu_l2 {
 330         cpu-supply = <&ppvar_litcpu>;
 331 };
 332
 333 &cpu_l3 {
 334         cpu-supply = <&ppvar_litcpu>;
 335 };
 336
 337 &cpu_b0 {
 338         cpu-supply = <&ppvar_bigcpu>;
 339 };
 340
 341 &cpu_b1 {
 342         cpu-supply = <&ppvar_bigcpu>;
 343 };
 344
 345
 346 &cru {
 347         assigned-clocks =
 348                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 349                 <&cru PLL_NPLL>,
 350                 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 351                 <&cru PCLK_PERIHP>,
 352                 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 353                 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 354                 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 355                 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
 356                 <&cru ACLK_GIC_PRE>,
 357                 <&cru PCLK_DDR>;
 358         assigned-clock-rates =
 359                 <600000000>, <800000000>,
 360                 <1000000000>,
 361                 <150000000>, <75000000>,
 362                 <37500000>,
 363                 <100000000>, <100000000>,
 364                 <50000000>, <800000000>,
 365                 <100000000>, <50000000>,
 366                 <400000000>, <400000000>,
 367                 <200000000>,
 368                 <200000000>;
 369 };
 370
 371 &emmc_phy {
 372         status = "okay";
 373 };
 374
 375 &gpu {
 376         mali-supply = <&ppvar_gpu>;
 377         status = "okay";
 378 };
 379
 380 ap_i2c_ts: &i2c3 {
 381         status = "okay";
 382
 383         clock-frequency = <400000>;
 384
 385         /* These are relatively safe rise/fall times */
 386         i2c-scl-falling-time-ns = <50>;
 387         i2c-scl-rising-time-ns = <300>;
 388 };
 389
 390 ap_i2c_audio: &i2c8 {
 391         status = "okay";
 392
 393         clock-frequency = <400000>;
 394
 395         /* These are relatively safe rise/fall times */
 396         i2c-scl-falling-time-ns = <50>;
 397         i2c-scl-rising-time-ns = <300>;
 398
 399         codec: da7219@1a {
 400                 compatible = "dlg,da7219";
 401                 reg = <0x1a>;
 402                 interrupt-parent = <&gpio1>;
 403                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 404                 clocks = <&cru SCLK_I2S_8CH_OUT>;
 405                 clock-names = "mclk";
 406                 dlg,micbias-lvl = <2600>;
 407                 dlg,mic-amp-in-sel = "diff";
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&headset_int_l>;
 410                 VDD-supply = <&pp1800>;
 411                 VDDMIC-supply = <&pp3300>;
 412                 VDDIO-supply = <&pp1800>;
 413
 414                 da7219_aad {
 415                         dlg,adc-1bit-rpt = <1>;
 416                         dlg,btn-avg = <4>;
 417                         dlg,btn-cfg = <50>;
 418                         dlg,mic-det-thr = <500>;
 419                         dlg,jack-ins-deb = <20>;
 420                         dlg,jack-det-rate = "32ms_64ms";
 421                         dlg,jack-rem-deb = <1>;
 422
 423                         dlg,a-d-btn-thr = <0xa>;
 424                         dlg,d-b-btn-thr = <0x16>;
 425                         dlg,b-c-btn-thr = <0x21>;
 426                         dlg,c-mic-btn-thr = <0x3E>;
 427                 };
 428         };
 429 };
 430
 431 &i2s0 {
 432         status = "okay";
 433 };
 434
 435 &i2s2 {
 436         status = "okay";
 437 };
 438
 439 &io_domains {
 440         status = "okay";
 441
 442         audio-supply = <&pp1800_audio>;         /* APIO5_VDD;  3d 4a */
 443         bt656-supply = <&pp1800_ap_io>;         /* APIO2_VDD;  2a 2b */
 444         gpio1830-supply = <&pp3000_ap>;         /* APIO4_VDD;  4c 4d */
 445         sdmmc-supply = <&ppvar_sd_card_io>;     /* SDMMC0_VDD; 4b    */
 446 };
 447
 448 &pcie0 {
 449         status = "okay";
 450
 451         ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
 454         vpcie3v3-supply = <&pp3300_wifi_bt>;
 455         vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
 456         vpcie0v9-supply = <&pp900_pcie>;
 457
 458         pci_rootport: pcie@0,0 {
 459                 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
 460                 #address-cells = <3>;
 461                 #size-cells = <2>;
 462                 ranges;
 463         };
 464 };
 465
 466 &pcie_phy {
 467         status = "okay";
 468 };
 469
 470 &pmu_io_domains {
 471         status = "okay";
 472
 473         pmu1830-supply = <&pp1800_pmu>;         /* PMUIO2_VDD */
 474 };
 475
 476 &pwm0 {
 477         status = "okay";
 478 };
 479
 480 &pwm1 {
 481         status = "okay";
 482 };
 483
 484 &pwm2 {
 485         status = "okay";
 486 };
 487
 488 &pwm3 {
 489         status = "okay";
 490 };
 491
 492 &sdhci {
 493         /*
 494          * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
 495          * same (or nearly the same) performance for all eMMC that are intended
 496          * to be used.
 497          */
 498         assigned-clock-rates = <150000000>;
 499
 500         bus-width = <8>;
 501         mmc-hs400-1_8v;
 502         mmc-hs400-enhanced-strobe;
 503         non-removable;
 504         status = "okay";
 505 };
 506
 507 &sdmmc {
 508         status = "okay";
 509
 510         /*
 511          * Note: configure "sdmmc_cd" as card detect even though it's actually
 512          * hooked to ground.  Because we specified "cd-gpios" below dw_mmc
 513          * should be ignoring card detect anyway.  Specifying the pin as
 514          * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
 515          * turned on that the system will still make sure the port is
 516          * configured as SDMMC and not JTAG.
 517          */
 518         pinctrl-names = "default";
 519         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
 520                      &sdmmc_bus4>;
 521
 522         bus-width = <4>;
 523         cap-mmc-highspeed;
 524         cap-sd-highspeed;
 525         cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 526         disable-wp;
 527         sd-uhs-sdr12;
 528         sd-uhs-sdr25;
 529         sd-uhs-sdr50;
 530         sd-uhs-sdr104;
 531         vmmc-supply = <&pp3000_sd_slot>;
 532         vqmmc-supply = <&ppvar_sd_card_io>;
 533 };
 534
 535 &spi1 {
 536         status = "okay";
 537
 538         pinctrl-names = "default", "sleep";
 539         pinctrl-1 = <&spi1_sleep>;
 540
 541         spiflash@0 {
 542                 compatible = "jedec,spi-nor";
 543                 reg = <0>;
 544
 545                 /* May run faster once verified. */
 546                 spi-max-frequency = <10000000>;
 547         };
 548 };
 549
 550 &spi2 {
 551         status = "okay";
 552 };
 553
 554 &spi5 {
 555         status = "okay";
 556
 557         cros_ec: ec@0 {
 558                 compatible = "google,cros-ec-spi";
 559                 reg = <0>;
 560                 interrupt-parent = <&gpio0>;
 561                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&ec_ap_int_l>;
 564                 spi-max-frequency = <3000000>;
 565
 566                 i2c_tunnel: i2c-tunnel {
 567                         compatible = "google,cros-ec-i2c-tunnel";
 568                         google,remote-bus = <4>;
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 usbc_extcon0: extcon@0 {
 574                         compatible = "google,extcon-usbc-cros-ec";
 575                         google,usb-port-id = <0>;
 576
 577                         #extcon-cells = <0>;
 578                 };
 579         };
 580 };
 581
 582 &tsadc {
 583         status = "okay";
 584
 585         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 586         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 587 };
 588
 589 &tcphy0 {
 590         status = "okay";
 591         extcon = <&usbc_extcon0>;
 592 };
 593
 594 &u2phy0 {
 595         status = "okay";
 596 };
 597
 598 &u2phy0_host {
 599         status = "okay";
 600 };
 601
 602 &u2phy1_host {
 603         status = "okay";
 604 };
 605
 606 &u2phy0_otg {
 607         status = "okay";
 608 };
 609
 610 &u2phy1_otg {
 611         status = "okay";
 612 };
 613
 614 &uart2 {
 615         status = "okay";
 616 };
 617
 618 &usb_host0_ohci {
 619         status = "okay";
 620 };
 621
 622 &usbdrd3_0 {
 623         status = "okay";
 624         extcon = <&usbc_extcon0>;
 625 };
 626
 627 &usbdrd_dwc3_0 {
 628         status = "okay";
 629         dr_mode = "host";
 630 };
 631
 632 &vopb {
 633         status = "okay";
 634 };
 635
 636 &vopb_mmu {
 637         status = "okay";
 638 };
 639
 640 &vopl {
 641         status = "okay";
 642 };
 643
 644 &vopl_mmu {
 645         status = "okay";
 646 };
 647
 648 #include <arm/cros-ec-keyboard.dtsi>
 649 #include <arm/cros-ec-sbs.dtsi>
 650
 651 &pinctrl {
 652         /*
 653          * pinctrl settings for pins that have no real owners.
 654          *
 655          * At the moment settings are identical for S0 and S3, but if we later
 656          * need to configure things differently for S3 we'll adjust here.
 657          */
 658         pinctrl-names = "default";
 659         pinctrl-0 = <
 660                 &ap_pwroff      /* AP will auto-assert this when in S3 */
 661                 &clk_32k        /* This pin is always 32k on gru boards */
 662         >;
 663
 664         pcfg_output_low: pcfg-output-low {
 665                 output-low;
 666         };
 667
 668         pcfg_output_high: pcfg-output-high {
 669                 output-high;
 670         };
 671
 672         pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 673                 bias-disable;
 674                 drive-strength = <8>;
 675         };
 676
 677         backlight-enable {
 678                 bl_en: bl-en {
 679                         rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
 680                 };
 681         };
 682
 683         cros-ec {
 684                 ec_ap_int_l: ec-ap-int-l {
 685                         rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
 686                 };
 687         };
 688
 689         discrete-regulators {
 690                 sd_io_pwr_en: sd-io-pwr-en {
 691                         rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
 692                                          &pcfg_pull_none>;
 693                 };
 694
 695                 sd_pwr_1800_sel: sd-pwr-1800-sel {
 696                         rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
 697                                          &pcfg_pull_none>;
 698                 };
 699
 700                 sd_slot_pwr_en: sd-slot-pwr-en {
 701                         rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
 702                                          &pcfg_pull_none>;
 703                 };
 704         };
 705
 706         codec {
 707                 /* Has external pullup */
 708                 headset_int_l: headset-int-l {
 709                         rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
 710                 };
 711
 712                 mic_int: mic-int {
 713                         rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
 714                 };
 715         };
 716
 717         max98357a {
 718                 sdmode_en: sdmode-en {
 719                         rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
 720                 };
 721         };
 722
 723         pcie {
 724                 pcie_clkreqn_cpm: pci-clkreqn-cpm {
 725                         /*
 726                          * Since our pcie doesn't support ClockPM(CPM), we want
 727                          * to hack this as gpio, so the EP could be able to
 728                          * de-assert it along and make ClockPM(CPM) work.
 729                          */
 730                         rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 731                 };
 732         };
 733
 734         sdmmc {
 735                 /*
 736                  * We run sdmmc at max speed; bump up drive strength.
 737                  * We also have external pulls, so disable the internal ones.
 738                  */
 739                 sdmmc_bus4: sdmmc-bus4 {
 740                         rockchip,pins =
 741                                 <4 RK_PB0 1 &pcfg_pull_none_8ma>,
 742                                 <4 RK_PB1 1 &pcfg_pull_none_8ma>,
 743                                 <4 RK_PB2 1 &pcfg_pull_none_8ma>,
 744                                 <4 RK_PB3 1 &pcfg_pull_none_8ma>;
 745                 };
 746
 747                 sdmmc_clk: sdmmc-clk {
 748                         rockchip,pins =
 749                                 <4 RK_PB4 1 &pcfg_pull_none_8ma>;
 750                 };
 751
 752                 sdmmc_cmd: sdmmc-cmd {
 753                         rockchip,pins =
 754                                 <4 RK_PB5 1 &pcfg_pull_none_8ma>;
 755                 };
 756
 757                 /*
 758                  * In our case the official card detect is hooked to ground
 759                  * to avoid getting access to JTAG just by sticking something
 760                  * in the SD card slot (see the force_jtag bit in the TRM).
 761                  *
 762                  * We still configure it as card detect because it doesn't
 763                  * hurt and dw_mmc will ignore it.  We make sure to disable
 764                  * the pull though so we don't burn needless power.
 765                  */
 766                 sdmmc_cd: sdmmc-cd {
 767                         rockchip,pins =
 768                                 <0 RK_PA7 1 &pcfg_pull_none>;
 769                 };
 770
 771                 /* This is where we actually hook up CD; has external pull */
 772                 sdmmc_cd_gpio: sdmmc-cd-gpio {
 773                         rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 774                 };
 775         };
 776
 777         spi1 {
 778                 spi1_sleep: spi1-sleep {
 779                         /*
 780                          * Pull down SPI1 CLK/CS/RX/TX during suspend, to
 781                          * prevent leakage.
 782                          */
 783                         rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
 784                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
 785                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
 786                                         <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
 787                 };
 788         };
 789
 790         touchscreen {
 791                 touch_int_l: touch-int-l {
 792                         rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
 793                 };
 794
 795                 touch_reset_l: touch-reset-l {
 796                         rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 797                 };
 798         };
 799
 800         trackpad {
 801                 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
 802                         rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
 803                 };
 804
 805                 trackpad_int_l: trackpad-int-l {
 806                         rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
 807                 };
 808         };
 809
 810         wifi: wifi {
 811                 wlan_module_reset_l: wlan-module-reset-l {
 812                         rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
 813                 };
 814
 815                 bt_host_wake_l: bt-host-wake-l {
 816                         /* Kevin has an external pull up, but Gru does not */
 817                         rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
 818                 };
 819         };
 820
 821         write-protect {
 822                 ap_fw_wp: ap-fw-wp {
 823                         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 824                 };
 825         };
 826 };