| blob | cede1ad81be23857ae4e55c6d7df23a468a7a374 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 */
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
14 / {
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 aliases {
22 ethernet0 = &gmac;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&cpu_l0>;
47 };
48 core1 {
49 cpu = <&cpu_l1>;
50 };
51 core2 {
52 cpu = <&cpu_l2>;
53 };
54 core3 {
55 cpu = <&cpu_l3>;
56 };
57 };
59 cluster1 {
60 core0 {
61 cpu = <&cpu_b0>;
62 };
63 core1 {
64 cpu = <&cpu_b1>;
65 };
66 };
67 };
69 cpu_l0: cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a53";
72 reg = <0x0 0x0>;
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
75 clocks = <&cru ARMCLKL>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
79 };
81 cpu_l1: cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 reg = <0x0 0x1>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
87 clocks = <&cru ARMCLKL>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
91 };
93 cpu_l2: cpu@2 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a53";
96 reg = <0x0 0x2>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
99 clocks = <&cru ARMCLKL>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
103 };
105 cpu_l3: cpu@3 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53";
108 reg = <0x0 0x3>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
111 clocks = <&cru ARMCLKL>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
115 };
117 cpu_b0: cpu@100 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a72";
120 reg = <0x0 0x100>;
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
123 clocks = <&cru ARMCLKB>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
127 };
129 cpu_b1: cpu@101 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a72";
132 reg = <0x0 0x101>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 clocks = <&cru ARMCLKB>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <436>;
138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
139 };
141 idle-states {
142 entry-method = "psci";
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
151 };
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
160 };
161 };
162 };
164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
167 };
169 pmu_a53 {
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
172 };
174 pmu_a72 {
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
177 };
179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
184 timer {
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
190 arm,no-tick-in-suspend;
191 };
193 xin24m: xin24m {
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
198 };
200 amba {
201 compatible = "simple-bus";
202 #address-cells = <2>;
203 #size-cells = <2>;
204 ranges;
206 dmac_bus: dma-controller@ff6d0000 {
207 compatible = "arm,pl330", "arm,primecell";
208 reg = <0x0 0xff6d0000 0x0 0x4000>;
209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
211 #dma-cells = <1>;
212 clocks = <&cru ACLK_DMAC0_PERILP>;
213 clock-names = "apb_pclk";
214 };
216 dmac_peri: dma-controller@ff6e0000 {
217 compatible = "arm,pl330", "arm,primecell";
218 reg = <0x0 0xff6e0000 0x0 0x4000>;
219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
221 #dma-cells = <1>;
222 clocks = <&cru ACLK_DMAC1_PERILP>;
223 clock-names = "apb_pclk";
224 };
225 };
227 pcie0: pcie@f8000000 {
228 compatible = "rockchip,rk3399-pcie";
229 reg = <0x0 0xf8000000 0x0 0x2000000>,
230 <0x0 0xfd000000 0x0 0x1000000>;
231 reg-names = "axi-base", "apb-base";
232 #address-cells = <3>;
233 #size-cells = <2>;
234 #interrupt-cells = <1>;
235 aspm-no-l0s;
236 bus-range = <0x0 0x1f>;
237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
239 clock-names = "aclk", "aclk-perf",
240 "hclk", "pm";
241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
244 interrupt-names = "sys", "legacy", "client";
245 interrupt-map-mask = <0 0 0 7>;
246 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
247 <0 0 0 2 &pcie0_intc 1>,
248 <0 0 0 3 &pcie0_intc 2>,
249 <0 0 0 4 &pcie0_intc 3>;
250 linux,pci-domain = <0>;
251 max-link-speed = <1>;
252 msi-map = <0x0 &its 0x0 0x1000>;
253 phys = <&pcie_phy 0>, <&pcie_phy 1>,
254 <&pcie_phy 2>, <&pcie_phy 3>;
255 phy-names = "pcie-phy-0", "pcie-phy-1",
256 "pcie-phy-2", "pcie-phy-3";
257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
262 <&cru SRST_A_PCIE>;
263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
264 "pm", "pclk", "aclk";
265 status = "disabled";
267 pcie0_intc: interrupt-controller {
268 interrupt-controller;
269 #address-cells = <0>;
270 #interrupt-cells = <1>;
271 };
272 };
274 gmac: ethernet@fe300000 {
275 compatible = "rockchip,rk3399-gmac";
276 reg = <0x0 0xfe300000 0x0 0x10000>;
277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
278 interrupt-names = "macirq";
279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
282 <&cru PCLK_GMAC>;
283 clock-names = "stmmaceth", "mac_clk_rx",
284 "mac_clk_tx", "clk_mac_ref",
285 "clk_mac_refout", "aclk_mac",
286 "pclk_mac";
287 power-domains = <&power RK3399_PD_GMAC>;
288 resets = <&cru SRST_A_GMAC>;
289 reset-names = "stmmaceth";
290 rockchip,grf = <&grf>;
291 status = "disabled";
292 };
294 sdio0: dwmmc@fe310000 {
295 compatible = "rockchip,rk3399-dw-mshc",
296 "rockchip,rk3288-dw-mshc";
297 reg = <0x0 0xfe310000 0x0 0x4000>;
298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
299 max-frequency = <150000000>;
300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
303 fifo-depth = <0x100>;
304 power-domains = <&power RK3399_PD_SDIOAUDIO>;
305 resets = <&cru SRST_SDIO0>;
306 reset-names = "reset";
307 status = "disabled";
308 };
310 sdmmc: dwmmc@fe320000 {
311 compatible = "rockchip,rk3399-dw-mshc",
312 "rockchip,rk3288-dw-mshc";
313 reg = <0x0 0xfe320000 0x0 0x4000>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
315 max-frequency = <150000000>;
316 assigned-clocks = <&cru HCLK_SD>;
317 assigned-clock-rates = <200000000>;
318 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
319 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
321 fifo-depth = <0x100>;
322 power-domains = <&power RK3399_PD_SD>;
323 resets = <&cru SRST_SDMMC>;
324 reset-names = "reset";
325 status = "disabled";
326 };
328 sdhci: sdhci@fe330000 {
329 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
330 reg = <0x0 0xfe330000 0x0 0x10000>;
331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
332 arasan,soc-ctl-syscon = <&grf>;
333 assigned-clocks = <&cru SCLK_EMMC>;
334 assigned-clock-rates = <200000000>;
335 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
336 clock-names = "clk_xin", "clk_ahb";
337 clock-output-names = "emmc_cardclock";
338 #clock-cells = <0>;
339 phys = <&emmc_phy>;
340 phy-names = "phy_arasan";
341 power-domains = <&power RK3399_PD_EMMC>;
342 disable-cqe-dcmd;
343 status = "disabled";
344 };
346 usb_host0_ehci: usb@fe380000 {
347 compatible = "generic-ehci";
348 reg = <0x0 0xfe380000 0x0 0x20000>;
349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
350 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
351 <&u2phy0>;
352 clock-names = "usbhost", "arbiter",
353 "utmi";
354 phys = <&u2phy0_host>;
355 phy-names = "usb";
356 status = "disabled";
357 };
359 usb_host0_ohci: usb@fe3a0000 {
360 compatible = "generic-ohci";
361 reg = <0x0 0xfe3a0000 0x0 0x20000>;
362 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
363 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
364 <&u2phy0>;
365 clock-names = "usbhost", "arbiter",
366 "utmi";
367 phys = <&u2phy0_host>;
368 phy-names = "usb";
369 status = "disabled";
370 };
372 usb_host1_ehci: usb@fe3c0000 {
373 compatible = "generic-ehci";
374 reg = <0x0 0xfe3c0000 0x0 0x20000>;
375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
376 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
377 <&u2phy1>;
378 clock-names = "usbhost", "arbiter",
379 "utmi";
380 phys = <&u2phy1_host>;
381 phy-names = "usb";
382 status = "disabled";
383 };
385 usb_host1_ohci: usb@fe3e0000 {
386 compatible = "generic-ohci";
387 reg = <0x0 0xfe3e0000 0x0 0x20000>;
388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
390 <&u2phy1>;
391 clock-names = "usbhost", "arbiter",
392 "utmi";
393 phys = <&u2phy1_host>;
394 phy-names = "usb";
395 status = "disabled";
396 };
398 usbdrd3_0: usb@fe800000 {
399 compatible = "rockchip,rk3399-dwc3";
400 #address-cells = <2>;
401 #size-cells = <2>;
402 ranges;
403 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
404 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
405 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
406 clock-names = "ref_clk", "suspend_clk",
407 "bus_clk", "aclk_usb3_rksoc_axi_perf",
408 "aclk_usb3", "grf_clk";
409 resets = <&cru SRST_A_USB3_OTG0>;
410 reset-names = "usb3-otg";
411 status = "disabled";
413 usbdrd_dwc3_0: dwc3 {
414 compatible = "snps,dwc3";
415 reg = <0x0 0xfe800000 0x0 0x100000>;
416 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
418 <&cru SCLK_USB3OTG0_SUSPEND>;
419 clock-names = "ref", "bus_early", "suspend";
420 dr_mode = "otg";
421 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
422 phy-names = "usb2-phy", "usb3-phy";
423 phy_type = "utmi_wide";
424 snps,dis_enblslpm_quirk;
425 snps,dis-u2-freeclk-exists-quirk;
426 snps,dis_u2_susphy_quirk;
427 snps,dis-del-phy-power-chg-quirk;
428 snps,dis-tx-ipgap-linecheck-quirk;
429 power-domains = <&power RK3399_PD_USB3>;
430 status = "disabled";
431 };
432 };
434 usbdrd3_1: usb@fe900000 {
435 compatible = "rockchip,rk3399-dwc3";
436 #address-cells = <2>;
437 #size-cells = <2>;
438 ranges;
439 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
440 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
441 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
442 clock-names = "ref_clk", "suspend_clk",
443 "bus_clk", "aclk_usb3_rksoc_axi_perf",
444 "aclk_usb3", "grf_clk";
445 resets = <&cru SRST_A_USB3_OTG1>;
446 reset-names = "usb3-otg";
447 status = "disabled";
449 usbdrd_dwc3_1: dwc3 {
450 compatible = "snps,dwc3";
451 reg = <0x0 0xfe900000 0x0 0x100000>;
452 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
453 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
454 <&cru SCLK_USB3OTG1_SUSPEND>;
455 clock-names = "ref", "bus_early", "suspend";
456 dr_mode = "otg";
457 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
458 phy-names = "usb2-phy", "usb3-phy";
459 phy_type = "utmi_wide";
460 snps,dis_enblslpm_quirk;
461 snps,dis-u2-freeclk-exists-quirk;
462 snps,dis_u2_susphy_quirk;
463 snps,dis-del-phy-power-chg-quirk;
464 snps,dis-tx-ipgap-linecheck-quirk;
465 power-domains = <&power RK3399_PD_USB3>;
466 status = "disabled";
467 };
468 };
470 cdn_dp: dp@fec00000 {
471 compatible = "rockchip,rk3399-cdn-dp";
472 reg = <0x0 0xfec00000 0x0 0x100000>;
473 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
474 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
475 assigned-clock-rates = <100000000>, <200000000>;
476 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
477 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
478 clock-names = "core-clk", "pclk", "spdif", "grf";
479 phys = <&tcphy0_dp>, <&tcphy1_dp>;
480 power-domains = <&power RK3399_PD_HDCP>;
481 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
482 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
483 reset-names = "spdif", "dptx", "apb", "core";
484 rockchip,grf = <&grf>;
485 #sound-dai-cells = <1>;
486 status = "disabled";
488 ports {
489 dp_in: port {
490 #address-cells = <1>;
491 #size-cells = <0>;
493 dp_in_vopb: endpoint@0 {
494 reg = <0>;
495 remote-endpoint = <&vopb_out_dp>;
496 };
498 dp_in_vopl: endpoint@1 {
499 reg = <1>;
500 remote-endpoint = <&vopl_out_dp>;
501 };
502 };
503 };
504 };
506 gic: interrupt-controller@fee00000 {
507 compatible = "arm,gic-v3";
508 #interrupt-cells = <4>;
509 #address-cells = <2>;
510 #size-cells = <2>;
511 ranges;
512 interrupt-controller;
514 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
515 <0x0 0xfef00000 0 0xc0000>, /* GICR */
516 <0x0 0xfff00000 0 0x10000>, /* GICC */
517 <0x0 0xfff10000 0 0x10000>, /* GICH */
518 <0x0 0xfff20000 0 0x10000>; /* GICV */
519 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
520 its: interrupt-controller@fee20000 {
521 compatible = "arm,gic-v3-its";
522 msi-controller;
523 reg = <0x0 0xfee20000 0x0 0x20000>;
524 };
526 ppi-partitions {
527 ppi_cluster0: interrupt-partition-0 {
528 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
529 };
531 ppi_cluster1: interrupt-partition-1 {
532 affinity = <&cpu_b0 &cpu_b1>;
533 };
534 };
535 };
537 saradc: saradc@ff100000 {
538 compatible = "rockchip,rk3399-saradc";
539 reg = <0x0 0xff100000 0x0 0x100>;
540 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
541 #io-channel-cells = <1>;
542 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
543 clock-names = "saradc", "apb_pclk";
544 resets = <&cru SRST_P_SARADC>;
545 reset-names = "saradc-apb";
546 status = "disabled";
547 };
549 i2c1: i2c@ff110000 {
550 compatible = "rockchip,rk3399-i2c";
551 reg = <0x0 0xff110000 0x0 0x1000>;
552 assigned-clocks = <&cru SCLK_I2C1>;
553 assigned-clock-rates = <200000000>;
554 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
555 clock-names = "i2c", "pclk";
556 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c1_xfer>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 status = "disabled";
562 };
564 i2c2: i2c@ff120000 {
565 compatible = "rockchip,rk3399-i2c";
566 reg = <0x0 0xff120000 0x0 0x1000>;
567 assigned-clocks = <&cru SCLK_I2C2>;
568 assigned-clock-rates = <200000000>;
569 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
570 clock-names = "i2c", "pclk";
571 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c2_xfer>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 status = "disabled";
577 };
579 i2c3: i2c@ff130000 {
580 compatible = "rockchip,rk3399-i2c";
581 reg = <0x0 0xff130000 0x0 0x1000>;
582 assigned-clocks = <&cru SCLK_I2C3>;
583 assigned-clock-rates = <200000000>;
584 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
585 clock-names = "i2c", "pclk";
586 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c3_xfer>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591 status = "disabled";
592 };
594 i2c5: i2c@ff140000 {
595 compatible = "rockchip,rk3399-i2c";
596 reg = <0x0 0xff140000 0x0 0x1000>;
597 assigned-clocks = <&cru SCLK_I2C5>;
598 assigned-clock-rates = <200000000>;
599 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
600 clock-names = "i2c", "pclk";
601 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&i2c5_xfer>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 status = "disabled";
607 };
609 i2c6: i2c@ff150000 {
610 compatible = "rockchip,rk3399-i2c";
611 reg = <0x0 0xff150000 0x0 0x1000>;
612 assigned-clocks = <&cru SCLK_I2C6>;
613 assigned-clock-rates = <200000000>;
614 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
615 clock-names = "i2c", "pclk";
616 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c6_xfer>;
619 #address-cells = <1>;
620 #size-cells = <0>;
621 status = "disabled";
622 };
624 i2c7: i2c@ff160000 {
625 compatible = "rockchip,rk3399-i2c";
626 reg = <0x0 0xff160000 0x0 0x1000>;
627 assigned-clocks = <&cru SCLK_I2C7>;
628 assigned-clock-rates = <200000000>;
629 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
630 clock-names = "i2c", "pclk";
631 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c7_xfer>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 status = "disabled";
637 };
639 uart0: serial@ff180000 {
640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641 reg = <0x0 0xff180000 0x0 0x100>;
642 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
643 clock-names = "baudclk", "apb_pclk";
644 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
645 reg-shift = <2>;
646 reg-io-width = <4>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart0_xfer>;
649 status = "disabled";
650 };
652 uart1: serial@ff190000 {
653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff190000 0x0 0x100>;
655 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
656 clock-names = "baudclk", "apb_pclk";
657 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
658 reg-shift = <2>;
659 reg-io-width = <4>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&uart1_xfer>;
662 status = "disabled";
663 };
665 uart2: serial@ff1a0000 {
666 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
667 reg = <0x0 0xff1a0000 0x0 0x100>;
668 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
669 clock-names = "baudclk", "apb_pclk";
670 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
671 reg-shift = <2>;
672 reg-io-width = <4>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&uart2c_xfer>;
675 status = "disabled";
676 };
678 uart3: serial@ff1b0000 {
679 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
680 reg = <0x0 0xff1b0000 0x0 0x100>;
681 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
682 clock-names = "baudclk", "apb_pclk";
683 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
684 reg-shift = <2>;
685 reg-io-width = <4>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&uart3_xfer>;
688 status = "disabled";
689 };
691 spi0: spi@ff1c0000 {
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff1c0000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
697 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
698 dma-names = "tx", "rx";
699 pinctrl-names = "default";
700 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
701 #address-cells = <1>;
702 #size-cells = <0>;
703 status = "disabled";
704 };
706 spi1: spi@ff1d0000 {
707 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
708 reg = <0x0 0xff1d0000 0x0 0x1000>;
709 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
710 clock-names = "spiclk", "apb_pclk";
711 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
712 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
713 dma-names = "tx", "rx";
714 pinctrl-names = "default";
715 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 status = "disabled";
719 };
721 spi2: spi@ff1e0000 {
722 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
723 reg = <0x0 0xff1e0000 0x0 0x1000>;
724 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
725 clock-names = "spiclk", "apb_pclk";
726 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
727 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
728 dma-names = "tx", "rx";
729 pinctrl-names = "default";
730 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
736 spi4: spi@ff1f0000 {
737 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
738 reg = <0x0 0xff1f0000 0x0 0x1000>;
739 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
740 clock-names = "spiclk", "apb_pclk";
741 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
742 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
743 dma-names = "tx", "rx";
744 pinctrl-names = "default";
745 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
746 #address-cells = <1>;
747 #size-cells = <0>;
748 status = "disabled";
749 };
751 spi5: spi@ff200000 {
752 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
753 reg = <0x0 0xff200000 0x0 0x1000>;
754 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
755 clock-names = "spiclk", "apb_pclk";
756 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
757 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
758 dma-names = "tx", "rx";
759 pinctrl-names = "default";
760 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
761 power-domains = <&power RK3399_PD_SDIOAUDIO>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 status = "disabled";
765 };
767 thermal_zones: thermal-zones {
768 cpu_thermal: cpu {
769 polling-delay-passive = <100>;
770 polling-delay = <1000>;
772 thermal-sensors = <&tsadc 0>;
774 trips {
775 cpu_alert0: cpu_alert0 {
776 temperature = <70000>;
777 hysteresis = <2000>;
778 type = "passive";
779 };
780 cpu_alert1: cpu_alert1 {
781 temperature = <75000>;
782 hysteresis = <2000>;
783 type = "passive";
784 };
785 cpu_crit: cpu_crit {
786 temperature = <95000>;
787 hysteresis = <2000>;
788 type = "critical";
789 };
790 };
792 cooling-maps {
793 map0 {
794 trip = <&cpu_alert0>;
795 cooling-device =
796 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
797 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
798 };
799 map1 {
800 trip = <&cpu_alert1>;
801 cooling-device =
802 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
803 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
804 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
805 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
806 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
807 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
808 };
809 };
810 };
812 gpu_thermal: gpu {
813 polling-delay-passive = <100>;
814 polling-delay = <1000>;
816 thermal-sensors = <&tsadc 1>;
818 trips {
819 gpu_alert0: gpu_alert0 {
820 temperature = <75000>;
821 hysteresis = <2000>;
822 type = "passive";
823 };
824 gpu_crit: gpu_crit {
825 temperature = <95000>;
826 hysteresis = <2000>;
827 type = "critical";
828 };
829 };
830 };
831 };
833 tsadc: tsadc@ff260000 {
834 compatible = "rockchip,rk3399-tsadc";
835 reg = <0x0 0xff260000 0x0 0x100>;
836 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
837 assigned-clocks = <&cru SCLK_TSADC>;
838 assigned-clock-rates = <750000>;
839 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
840 clock-names = "tsadc", "apb_pclk";
841 resets = <&cru SRST_TSADC>;
842 reset-names = "tsadc-apb";
843 rockchip,grf = <&grf>;
844 rockchip,hw-tshut-temp = <95000>;
845 pinctrl-names = "init", "default", "sleep";
846 pinctrl-0 = <&otp_gpio>;
847 pinctrl-1 = <&otp_out>;
848 pinctrl-2 = <&otp_gpio>;
849 #thermal-sensor-cells = <1>;
850 status = "disabled";
851 };
853 qos_emmc: qos@ffa58000 {
854 compatible = "syscon";
855 reg = <0x0 0xffa58000 0x0 0x20>;
856 };
858 qos_gmac: qos@ffa5c000 {
859 compatible = "syscon";
860 reg = <0x0 0xffa5c000 0x0 0x20>;
861 };
863 qos_pcie: qos@ffa60080 {
864 compatible = "syscon";
865 reg = <0x0 0xffa60080 0x0 0x20>;
866 };
868 qos_usb_host0: qos@ffa60100 {
869 compatible = "syscon";
870 reg = <0x0 0xffa60100 0x0 0x20>;
871 };
873 qos_usb_host1: qos@ffa60180 {
874 compatible = "syscon";
875 reg = <0x0 0xffa60180 0x0 0x20>;
876 };
878 qos_usb_otg0: qos@ffa70000 {
879 compatible = "syscon";
880 reg = <0x0 0xffa70000 0x0 0x20>;
881 };
883 qos_usb_otg1: qos@ffa70080 {
884 compatible = "syscon";
885 reg = <0x0 0xffa70080 0x0 0x20>;
886 };
888 qos_sd: qos@ffa74000 {
889 compatible = "syscon";
890 reg = <0x0 0xffa74000 0x0 0x20>;
891 };
893 qos_sdioaudio: qos@ffa76000 {
894 compatible = "syscon";
895 reg = <0x0 0xffa76000 0x0 0x20>;
896 };
898 qos_hdcp: qos@ffa90000 {
899 compatible = "syscon";
900 reg = <0x0 0xffa90000 0x0 0x20>;
901 };
903 qos_iep: qos@ffa98000 {
904 compatible = "syscon";
905 reg = <0x0 0xffa98000 0x0 0x20>;
906 };
908 qos_isp0_m0: qos@ffaa0000 {
909 compatible = "syscon";
910 reg = <0x0 0xffaa0000 0x0 0x20>;
911 };
913 qos_isp0_m1: qos@ffaa0080 {
914 compatible = "syscon";
915 reg = <0x0 0xffaa0080 0x0 0x20>;
916 };
918 qos_isp1_m0: qos@ffaa8000 {
919 compatible = "syscon";
920 reg = <0x0 0xffaa8000 0x0 0x20>;
921 };
923 qos_isp1_m1: qos@ffaa8080 {
924 compatible = "syscon";
925 reg = <0x0 0xffaa8080 0x0 0x20>;
926 };
928 qos_rga_r: qos@ffab0000 {
929 compatible = "syscon";
930 reg = <0x0 0xffab0000 0x0 0x20>;
931 };
933 qos_rga_w: qos@ffab0080 {
934 compatible = "syscon";
935 reg = <0x0 0xffab0080 0x0 0x20>;
936 };
938 qos_video_m0: qos@ffab8000 {
939 compatible = "syscon";
940 reg = <0x0 0xffab8000 0x0 0x20>;
941 };
943 qos_video_m1_r: qos@ffac0000 {
944 compatible = "syscon";
945 reg = <0x0 0xffac0000 0x0 0x20>;
946 };
948 qos_video_m1_w: qos@ffac0080 {
949 compatible = "syscon";
950 reg = <0x0 0xffac0080 0x0 0x20>;
951 };
953 qos_vop_big_r: qos@ffac8000 {
954 compatible = "syscon";
955 reg = <0x0 0xffac8000 0x0 0x20>;
956 };
958 qos_vop_big_w: qos@ffac8080 {
959 compatible = "syscon";
960 reg = <0x0 0xffac8080 0x0 0x20>;
961 };
963 qos_vop_little: qos@ffad0000 {
964 compatible = "syscon";
965 reg = <0x0 0xffad0000 0x0 0x20>;
966 };
968 qos_perihp: qos@ffad8080 {
969 compatible = "syscon";
970 reg = <0x0 0xffad8080 0x0 0x20>;
971 };
973 qos_gpu: qos@ffae0000 {
974 compatible = "syscon";
975 reg = <0x0 0xffae0000 0x0 0x20>;
976 };
978 pmu: power-management@ff310000 {
979 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
980 reg = <0x0 0xff310000 0x0 0x1000>;
982 /*
983 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
984 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
985 * Some of the power domains are grouped together for every
986 * voltage domain.
987 * The detail contents as below.
988 */
989 power: power-controller {
990 compatible = "rockchip,rk3399-power-controller";
991 #power-domain-cells = <1>;
992 #address-cells = <1>;
993 #size-cells = <0>;
995 /* These power domains are grouped by VD_CENTER */
996 pd_iep@RK3399_PD_IEP {
997 reg = <RK3399_PD_IEP>;
998 clocks = <&cru ACLK_IEP>,
999 <&cru HCLK_IEP>;
1000 pm_qos = <&qos_iep>;
1001 };
1002 pd_rga@RK3399_PD_RGA {
1003 reg = <RK3399_PD_RGA>;
1004 clocks = <&cru ACLK_RGA>,
1005 <&cru HCLK_RGA>;
1006 pm_qos = <&qos_rga_r>,
1007 <&qos_rga_w>;
1008 };
1009 pd_vcodec@RK3399_PD_VCODEC {
1010 reg = <RK3399_PD_VCODEC>;
1011 clocks = <&cru ACLK_VCODEC>,
1012 <&cru HCLK_VCODEC>;
1013 pm_qos = <&qos_video_m0>;
1014 };
1015 pd_vdu@RK3399_PD_VDU {
1016 reg = <RK3399_PD_VDU>;
1017 clocks = <&cru ACLK_VDU>,
1018 <&cru HCLK_VDU>;
1019 pm_qos = <&qos_video_m1_r>,
1020 <&qos_video_m1_w>;
1021 };
1023 /* These power domains are grouped by VD_GPU */
1024 pd_gpu@RK3399_PD_GPU {
1025 reg = <RK3399_PD_GPU>;
1026 clocks = <&cru ACLK_GPU>;
1027 pm_qos = <&qos_gpu>;
1028 };
1030 /* These power domains are grouped by VD_LOGIC */
1031 pd_edp@RK3399_PD_EDP {
1032 reg = <RK3399_PD_EDP>;
1033 clocks = <&cru PCLK_EDP_CTRL>;
1034 };
1035 pd_emmc@RK3399_PD_EMMC {
1036 reg = <RK3399_PD_EMMC>;
1037 clocks = <&cru ACLK_EMMC>;
1038 pm_qos = <&qos_emmc>;
1039 };
1040 pd_gmac@RK3399_PD_GMAC {
1041 reg = <RK3399_PD_GMAC>;
1042 clocks = <&cru ACLK_GMAC>,
1043 <&cru PCLK_GMAC>;
1044 pm_qos = <&qos_gmac>;
1045 };
1046 pd_sd@RK3399_PD_SD {
1047 reg = <RK3399_PD_SD>;
1048 clocks = <&cru HCLK_SDMMC>,
1049 <&cru SCLK_SDMMC>;
1050 pm_qos = <&qos_sd>;
1051 };
1052 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1053 reg = <RK3399_PD_SDIOAUDIO>;
1054 clocks = <&cru HCLK_SDIO>;
1055 pm_qos = <&qos_sdioaudio>;
1056 };
1057 pd_usb3@RK3399_PD_USB3 {
1058 reg = <RK3399_PD_USB3>;
1059 clocks = <&cru ACLK_USB3>;
1060 pm_qos = <&qos_usb_otg0>,
1061 <&qos_usb_otg1>;
1062 };
1063 pd_vio@RK3399_PD_VIO {
1064 reg = <RK3399_PD_VIO>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1068 pd_hdcp@RK3399_PD_HDCP {
1069 reg = <RK3399_PD_HDCP>;
1070 clocks = <&cru ACLK_HDCP>,
1071 <&cru HCLK_HDCP>,
1072 <&cru PCLK_HDCP>;
1073 pm_qos = <&qos_hdcp>;
1074 };
1075 pd_isp0@RK3399_PD_ISP0 {
1076 reg = <RK3399_PD_ISP0>;
1077 clocks = <&cru ACLK_ISP0>,
1078 <&cru HCLK_ISP0>;
1079 pm_qos = <&qos_isp0_m0>,
1080 <&qos_isp0_m1>;
1081 };
1082 pd_isp1@RK3399_PD_ISP1 {
1083 reg = <RK3399_PD_ISP1>;
1084 clocks = <&cru ACLK_ISP1>,
1085 <&cru HCLK_ISP1>;
1086 pm_qos = <&qos_isp1_m0>,
1087 <&qos_isp1_m1>;
1088 };
1089 pd_tcpc0@RK3399_PD_TCPC0 {
1090 reg = <RK3399_PD_TCPD0>;
1091 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1092 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1093 };
1094 pd_tcpc1@RK3399_PD_TCPC1 {
1095 reg = <RK3399_PD_TCPD1>;
1096 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1097 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1098 };
1099 pd_vo@RK3399_PD_VO {
1100 reg = <RK3399_PD_VO>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1104 pd_vopb@RK3399_PD_VOPB {
1105 reg = <RK3399_PD_VOPB>;
1106 clocks = <&cru ACLK_VOP0>,
1107 <&cru HCLK_VOP0>;
1108 pm_qos = <&qos_vop_big_r>,
1109 <&qos_vop_big_w>;
1110 };
1111 pd_vopl@RK3399_PD_VOPL {
1112 reg = <RK3399_PD_VOPL>;
1113 clocks = <&cru ACLK_VOP1>,
1114 <&cru HCLK_VOP1>;
1115 pm_qos = <&qos_vop_little>;
1116 };
1117 };
1118 };
1119 };
1120 };
1122 pmugrf: syscon@ff320000 {
1123 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1124 reg = <0x0 0xff320000 0x0 0x1000>;
1125 #address-cells = <1>;
1126 #size-cells = <1>;
1128 pmu_io_domains: io-domains {
1129 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1130 status = "disabled";
1131 };
1132 };
1134 spi3: spi@ff350000 {
1135 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1136 reg = <0x0 0xff350000 0x0 0x1000>;
1137 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1138 clock-names = "spiclk", "apb_pclk";
1139 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 status = "disabled";
1145 };
1147 uart4: serial@ff370000 {
1148 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1149 reg = <0x0 0xff370000 0x0 0x100>;
1150 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1151 clock-names = "baudclk", "apb_pclk";
1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1153 reg-shift = <2>;
1154 reg-io-width = <4>;
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&uart4_xfer>;
1157 status = "disabled";
1158 };
1160 i2c0: i2c@ff3c0000 {
1161 compatible = "rockchip,rk3399-i2c";
1162 reg = <0x0 0xff3c0000 0x0 0x1000>;
1163 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1164 assigned-clock-rates = <200000000>;
1165 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1166 clock-names = "i2c", "pclk";
1167 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2c0_xfer>;
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 status = "disabled";
1173 };
1175 i2c4: i2c@ff3d0000 {
1176 compatible = "rockchip,rk3399-i2c";
1177 reg = <0x0 0xff3d0000 0x0 0x1000>;
1178 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1179 assigned-clock-rates = <200000000>;
1180 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1181 clock-names = "i2c", "pclk";
1182 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&i2c4_xfer>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 status = "disabled";
1188 };
1190 i2c8: i2c@ff3e0000 {
1191 compatible = "rockchip,rk3399-i2c";
1192 reg = <0x0 0xff3e0000 0x0 0x1000>;
1193 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1194 assigned-clock-rates = <200000000>;
1195 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1196 clock-names = "i2c", "pclk";
1197 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&i2c8_xfer>;
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1202 status = "disabled";
1203 };
1205 pwm0: pwm@ff420000 {
1206 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1207 reg = <0x0 0xff420000 0x0 0x10>;
1208 #pwm-cells = <3>;
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&pwm0_pin>;
1211 clocks = <&pmucru PCLK_RKPWM_PMU>;
1212 clock-names = "pwm";
1213 status = "disabled";
1214 };
1216 pwm1: pwm@ff420010 {
1217 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1218 reg = <0x0 0xff420010 0x0 0x10>;
1219 #pwm-cells = <3>;
1220 pinctrl-names = "default";
1221 pinctrl-0 = <&pwm1_pin>;
1222 clocks = <&pmucru PCLK_RKPWM_PMU>;
1223 clock-names = "pwm";
1224 status = "disabled";
1225 };
1227 pwm2: pwm@ff420020 {
1228 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1229 reg = <0x0 0xff420020 0x0 0x10>;
1230 #pwm-cells = <3>;
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&pwm2_pin>;
1233 clocks = <&pmucru PCLK_RKPWM_PMU>;
1234 clock-names = "pwm";
1235 status = "disabled";
1236 };
1238 pwm3: pwm@ff420030 {
1239 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1240 reg = <0x0 0xff420030 0x0 0x10>;
1241 #pwm-cells = <3>;
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&pwm3a_pin>;
1244 clocks = <&pmucru PCLK_RKPWM_PMU>;
1245 clock-names = "pwm";
1246 status = "disabled";
1247 };
1249 vpu: video-codec@ff650000 {
1250 compatible = "rockchip,rk3399-vpu";
1251 reg = <0x0 0xff650000 0x0 0x800>;
1252 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1253 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1254 interrupt-names = "vepu", "vdpu";
1255 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1256 clock-names = "aclk", "hclk";
1257 iommus = <&vpu_mmu>;
1258 power-domains = <&power RK3399_PD_VCODEC>;
1259 };
1261 vpu_mmu: iommu@ff650800 {
1262 compatible = "rockchip,iommu";
1263 reg = <0x0 0xff650800 0x0 0x40>;
1264 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1265 interrupt-names = "vpu_mmu";
1266 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1267 clock-names = "aclk", "iface";
1268 #iommu-cells = <0>;
1269 power-domains = <&power RK3399_PD_VCODEC>;
1270 };
1272 vdec_mmu: iommu@ff660480 {
1273 compatible = "rockchip,iommu";
1274 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1276 interrupt-names = "vdec_mmu";
1277 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1278 clock-names = "aclk", "iface";
1279 #iommu-cells = <0>;
1280 status = "disabled";
1281 };
1283 iep_mmu: iommu@ff670800 {
1284 compatible = "rockchip,iommu";
1285 reg = <0x0 0xff670800 0x0 0x40>;
1286 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1287 interrupt-names = "iep_mmu";
1288 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1289 clock-names = "aclk", "iface";
1290 #iommu-cells = <0>;
1291 status = "disabled";
1292 };
1294 rga: rga@ff680000 {
1295 compatible = "rockchip,rk3399-rga";
1296 reg = <0x0 0xff680000 0x0 0x10000>;
1297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1298 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1299 clock-names = "aclk", "hclk", "sclk";
1300 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1301 reset-names = "core", "axi", "ahb";
1302 power-domains = <&power RK3399_PD_RGA>;
1303 };
1305 efuse0: efuse@ff690000 {
1306 compatible = "rockchip,rk3399-efuse";
1307 reg = <0x0 0xff690000 0x0 0x80>;
1308 #address-cells = <1>;
1309 #size-cells = <1>;
1310 clocks = <&cru PCLK_EFUSE1024NS>;
1311 clock-names = "pclk_efuse";
1313 /* Data cells */
1314 cpu_id: cpu-id@7 {
1315 reg = <0x07 0x10>;
1316 };
1317 cpub_leakage: cpu-leakage@17 {
1318 reg = <0x17 0x1>;
1319 };
1320 gpu_leakage: gpu-leakage@18 {
1321 reg = <0x18 0x1>;
1322 };
1323 center_leakage: center-leakage@19 {
1324 reg = <0x19 0x1>;
1325 };
1326 cpul_leakage: cpu-leakage@1a {
1327 reg = <0x1a 0x1>;
1328 };
1329 logic_leakage: logic-leakage@1b {
1330 reg = <0x1b 0x1>;
1331 };
1332 wafer_info: wafer-info@1c {
1333 reg = <0x1c 0x1>;
1334 };
1335 };
1337 pmucru: pmu-clock-controller@ff750000 {
1338 compatible = "rockchip,rk3399-pmucru";
1339 reg = <0x0 0xff750000 0x0 0x1000>;
1340 rockchip,grf = <&pmugrf>;
1341 #clock-cells = <1>;
1342 #reset-cells = <1>;
1343 assigned-clocks = <&pmucru PLL_PPLL>;
1344 assigned-clock-rates = <676000000>;
1345 };
1347 cru: clock-controller@ff760000 {
1348 compatible = "rockchip,rk3399-cru";
1349 reg = <0x0 0xff760000 0x0 0x1000>;
1350 rockchip,grf = <&grf>;
1351 #clock-cells = <1>;
1352 #reset-cells = <1>;
1353 assigned-clocks =
1354 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1355 <&cru PLL_NPLL>,
1356 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1357 <&cru PCLK_PERIHP>,
1358 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1359 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1360 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1361 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1362 <&cru ACLK_GIC_PRE>,
1363 <&cru PCLK_DDR>;
1364 assigned-clock-rates =
1365 <594000000>, <800000000>,
1366 <1000000000>,
1367 <150000000>, <75000000>,
1368 <37500000>,
1369 <100000000>, <100000000>,
1370 <50000000>, <600000000>,
1371 <100000000>, <50000000>,
1372 <400000000>, <400000000>,
1373 <200000000>,
1374 <200000000>;
1375 };
1377 grf: syscon@ff770000 {
1378 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1379 reg = <0x0 0xff770000 0x0 0x10000>;
1380 #address-cells = <1>;
1381 #size-cells = <1>;
1383 io_domains: io-domains {
1384 compatible = "rockchip,rk3399-io-voltage-domain";
1385 status = "disabled";
1386 };
1388 u2phy0: usb2-phy@e450 {
1389 compatible = "rockchip,rk3399-usb2phy";
1390 reg = <0xe450 0x10>;
1391 clocks = <&cru SCLK_USB2PHY0_REF>;
1392 clock-names = "phyclk";
1393 #clock-cells = <0>;
1394 clock-output-names = "clk_usbphy0_480m";
1395 status = "disabled";
1397 u2phy0_host: host-port {
1398 #phy-cells = <0>;
1399 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1400 interrupt-names = "linestate";
1401 status = "disabled";
1402 };
1404 u2phy0_otg: otg-port {
1405 #phy-cells = <0>;
1406 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1407 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1408 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1409 interrupt-names = "otg-bvalid", "otg-id",
1410 "linestate";
1411 status = "disabled";
1412 };
1413 };
1415 u2phy1: usb2-phy@e460 {
1416 compatible = "rockchip,rk3399-usb2phy";
1417 reg = <0xe460 0x10>;
1418 clocks = <&cru SCLK_USB2PHY1_REF>;
1419 clock-names = "phyclk";
1420 #clock-cells = <0>;
1421 clock-output-names = "clk_usbphy1_480m";
1422 status = "disabled";
1424 u2phy1_host: host-port {
1425 #phy-cells = <0>;
1426 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1427 interrupt-names = "linestate";
1428 status = "disabled";
1429 };
1431 u2phy1_otg: otg-port {
1432 #phy-cells = <0>;
1433 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1434 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1435 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1436 interrupt-names = "otg-bvalid", "otg-id",
1437 "linestate";
1438 status = "disabled";
1439 };
1440 };
1442 emmc_phy: phy@f780 {
1443 compatible = "rockchip,rk3399-emmc-phy";
1444 reg = <0xf780 0x24>;
1445 clocks = <&sdhci>;
1446 clock-names = "emmcclk";
1447 #phy-cells = <0>;
1448 status = "disabled";
1449 };
1451 pcie_phy: pcie-phy {
1452 compatible = "rockchip,rk3399-pcie-phy";
1453 clocks = <&cru SCLK_PCIEPHY_REF>;
1454 clock-names = "refclk";
1455 #phy-cells = <1>;
1456 resets = <&cru SRST_PCIEPHY>;
1457 drive-impedance-ohm = <50>;
1458 reset-names = "phy";
1459 status = "disabled";
1460 };
1461 };
1463 tcphy0: phy@ff7c0000 {
1464 compatible = "rockchip,rk3399-typec-phy";
1465 reg = <0x0 0xff7c0000 0x0 0x40000>;
1466 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1467 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1468 clock-names = "tcpdcore", "tcpdphy-ref";
1469 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1470 assigned-clock-rates = <50000000>;
1471 power-domains = <&power RK3399_PD_TCPD0>;
1472 resets = <&cru SRST_UPHY0>,
1473 <&cru SRST_UPHY0_PIPE_L00>,
1474 <&cru SRST_P_UPHY0_TCPHY>;
1475 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1476 rockchip,grf = <&grf>;
1477 status = "disabled";
1479 tcphy0_dp: dp-port {
1480 #phy-cells = <0>;
1481 };
1483 tcphy0_usb3: usb3-port {
1484 #phy-cells = <0>;
1485 };
1486 };
1488 tcphy1: phy@ff800000 {
1489 compatible = "rockchip,rk3399-typec-phy";
1490 reg = <0x0 0xff800000 0x0 0x40000>;
1491 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1492 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1493 clock-names = "tcpdcore", "tcpdphy-ref";
1494 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1495 assigned-clock-rates = <50000000>;
1496 power-domains = <&power RK3399_PD_TCPD1>;
1497 resets = <&cru SRST_UPHY1>,
1498 <&cru SRST_UPHY1_PIPE_L00>,
1499 <&cru SRST_P_UPHY1_TCPHY>;
1500 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1501 rockchip,grf = <&grf>;
1502 status = "disabled";
1504 tcphy1_dp: dp-port {
1505 #phy-cells = <0>;
1506 };
1508 tcphy1_usb3: usb3-port {
1509 #phy-cells = <0>;
1510 };
1511 };
1513 watchdog@ff848000 {
1514 compatible = "snps,dw-wdt";
1515 reg = <0x0 0xff848000 0x0 0x100>;
1516 clocks = <&cru PCLK_WDT>;
1517 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1518 };
1520 rktimer: rktimer@ff850000 {
1521 compatible = "rockchip,rk3399-timer";
1522 reg = <0x0 0xff850000 0x0 0x1000>;
1523 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1524 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1525 clock-names = "pclk", "timer";
1526 };
1528 spdif: spdif@ff870000 {
1529 compatible = "rockchip,rk3399-spdif";
1530 reg = <0x0 0xff870000 0x0 0x1000>;
1531 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1532 dmas = <&dmac_bus 7>;
1533 dma-names = "tx";
1534 clock-names = "mclk", "hclk";
1535 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1536 pinctrl-names = "default";
1537 pinctrl-0 = <&spdif_bus>;
1538 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1539 #sound-dai-cells = <0>;
1540 status = "disabled";
1541 };
1543 i2s0: i2s@ff880000 {
1544 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1545 reg = <0x0 0xff880000 0x0 0x1000>;
1546 rockchip,grf = <&grf>;
1547 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1548 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1549 dma-names = "tx", "rx";
1550 clock-names = "i2s_clk", "i2s_hclk";
1551 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&i2s0_8ch_bus>;
1554 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1555 #sound-dai-cells = <0>;
1556 status = "disabled";
1557 };
1559 i2s1: i2s@ff890000 {
1560 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1561 reg = <0x0 0xff890000 0x0 0x1000>;
1562 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1563 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1564 dma-names = "tx", "rx";
1565 clock-names = "i2s_clk", "i2s_hclk";
1566 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&i2s1_2ch_bus>;
1569 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1570 #sound-dai-cells = <0>;
1571 status = "disabled";
1572 };
1574 i2s2: i2s@ff8a0000 {
1575 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1576 reg = <0x0 0xff8a0000 0x0 0x1000>;
1577 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1578 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1579 dma-names = "tx", "rx";
1580 clock-names = "i2s_clk", "i2s_hclk";
1581 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1582 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1583 #sound-dai-cells = <0>;
1584 status = "disabled";
1585 };
1587 vopl: vop@ff8f0000 {
1588 compatible = "rockchip,rk3399-vop-lit";
1589 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1590 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1591 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1592 assigned-clock-rates = <400000000>, <100000000>;
1593 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1594 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1595 iommus = <&vopl_mmu>;
1596 power-domains = <&power RK3399_PD_VOPL>;
1597 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1598 reset-names = "axi", "ahb", "dclk";
1599 status = "disabled";
1601 vopl_out: port {
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1605 vopl_out_mipi: endpoint@0 {
1606 reg = <0>;
1607 remote-endpoint = <&mipi_in_vopl>;
1608 };
1610 vopl_out_edp: endpoint@1 {
1611 reg = <1>;
1612 remote-endpoint = <&edp_in_vopl>;
1613 };
1615 vopl_out_hdmi: endpoint@2 {
1616 reg = <2>;
1617 remote-endpoint = <&hdmi_in_vopl>;
1618 };
1620 vopl_out_mipi1: endpoint@3 {
1621 reg = <3>;
1622 remote-endpoint = <&mipi1_in_vopl>;
1623 };
1625 vopl_out_dp: endpoint@4 {
1626 reg = <4>;
1627 remote-endpoint = <&dp_in_vopl>;
1628 };
1629 };
1630 };
1632 vopl_mmu: iommu@ff8f3f00 {
1633 compatible = "rockchip,iommu";
1634 reg = <0x0 0xff8f3f00 0x0 0x100>;
1635 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1636 interrupt-names = "vopl_mmu";
1637 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1638 clock-names = "aclk", "iface";
1639 power-domains = <&power RK3399_PD_VOPL>;
1640 #iommu-cells = <0>;
1641 status = "disabled";
1642 };
1644 vopb: vop@ff900000 {
1645 compatible = "rockchip,rk3399-vop-big";
1646 reg = <0x0 0xff900000 0x0 0x3efc>;
1647 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1648 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1649 assigned-clock-rates = <400000000>, <100000000>;
1650 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1651 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1652 iommus = <&vopb_mmu>;
1653 power-domains = <&power RK3399_PD_VOPB>;
1654 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1655 reset-names = "axi", "ahb", "dclk";
1656 status = "disabled";
1658 vopb_out: port {
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1662 vopb_out_edp: endpoint@0 {
1663 reg = <0>;
1664 remote-endpoint = <&edp_in_vopb>;
1665 };
1667 vopb_out_mipi: endpoint@1 {
1668 reg = <1>;
1669 remote-endpoint = <&mipi_in_vopb>;
1670 };
1672 vopb_out_hdmi: endpoint@2 {
1673 reg = <2>;
1674 remote-endpoint = <&hdmi_in_vopb>;
1675 };
1677 vopb_out_mipi1: endpoint@3 {
1678 reg = <3>;
1679 remote-endpoint = <&mipi1_in_vopb>;
1680 };
1682 vopb_out_dp: endpoint@4 {
1683 reg = <4>;
1684 remote-endpoint = <&dp_in_vopb>;
1685 };
1686 };
1687 };
1689 vopb_mmu: iommu@ff903f00 {
1690 compatible = "rockchip,iommu";
1691 reg = <0x0 0xff903f00 0x0 0x100>;
1692 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1693 interrupt-names = "vopb_mmu";
1694 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1695 clock-names = "aclk", "iface";
1696 power-domains = <&power RK3399_PD_VOPB>;
1697 #iommu-cells = <0>;
1698 status = "disabled";
1699 };
1701 isp0_mmu: iommu@ff914000 {
1702 compatible = "rockchip,iommu";
1703 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1704 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1705 interrupt-names = "isp0_mmu";
1706 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1707 clock-names = "aclk", "iface";
1708 #iommu-cells = <0>;
1709 power-domains = <&power RK3399_PD_ISP0>;
1710 rockchip,disable-mmu-reset;
1711 };
1713 isp1_mmu: iommu@ff924000 {
1714 compatible = "rockchip,iommu";
1715 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1716 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1717 interrupt-names = "isp1_mmu";
1718 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1719 clock-names = "aclk", "iface";
1720 #iommu-cells = <0>;
1721 power-domains = <&power RK3399_PD_ISP1>;
1722 rockchip,disable-mmu-reset;
1723 };
1725 hdmi_sound: hdmi-sound {
1726 compatible = "simple-audio-card";
1727 simple-audio-card,format = "i2s";
1728 simple-audio-card,mclk-fs = <256>;
1729 simple-audio-card,name = "hdmi-sound";
1730 status = "disabled";
1732 simple-audio-card,cpu {
1733 sound-dai = <&i2s2>;
1734 };
1735 simple-audio-card,codec {
1736 sound-dai = <&hdmi>;
1737 };
1738 };
1740 hdmi: hdmi@ff940000 {
1741 compatible = "rockchip,rk3399-dw-hdmi";
1742 reg = <0x0 0xff940000 0x0 0x20000>;
1743 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1744 clocks = <&cru PCLK_HDMI_CTRL>,
1745 <&cru SCLK_HDMI_SFR>,
1746 <&cru PLL_VPLL>,
1747 <&cru PCLK_VIO_GRF>,
1748 <&cru SCLK_HDMI_CEC>;
1749 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1750 power-domains = <&power RK3399_PD_HDCP>;
1751 reg-io-width = <4>;
1752 rockchip,grf = <&grf>;
1753 #sound-dai-cells = <0>;
1754 status = "disabled";
1756 ports {
1757 hdmi_in: port {
1758 #address-cells = <1>;
1759 #size-cells = <0>;
1761 hdmi_in_vopb: endpoint@0 {
1762 reg = <0>;
1763 remote-endpoint = <&vopb_out_hdmi>;
1764 };
1765 hdmi_in_vopl: endpoint@1 {
1766 reg = <1>;
1767 remote-endpoint = <&vopl_out_hdmi>;
1768 };
1769 };
1770 };
1771 };
1773 mipi_dsi: mipi@ff960000 {
1774 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1775 reg = <0x0 0xff960000 0x0 0x8000>;
1776 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1777 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1778 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1779 clock-names = "ref", "pclk", "phy_cfg", "grf";
1780 power-domains = <&power RK3399_PD_VIO>;
1781 resets = <&cru SRST_P_MIPI_DSI0>;
1782 reset-names = "apb";
1783 rockchip,grf = <&grf>;
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1786 status = "disabled";
1788 ports {
1789 #address-cells = <1>;
1790 #size-cells = <0>;
1792 mipi_in: port@0 {
1793 reg = <0>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1797 mipi_in_vopb: endpoint@0 {
1798 reg = <0>;
1799 remote-endpoint = <&vopb_out_mipi>;
1800 };
1801 mipi_in_vopl: endpoint@1 {
1802 reg = <1>;
1803 remote-endpoint = <&vopl_out_mipi>;
1804 };
1805 };
1806 };
1807 };
1809 mipi_dsi1: mipi@ff968000 {
1810 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1811 reg = <0x0 0xff968000 0x0 0x8000>;
1812 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1813 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1814 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1815 clock-names = "ref", "pclk", "phy_cfg", "grf";
1816 power-domains = <&power RK3399_PD_VIO>;
1817 resets = <&cru SRST_P_MIPI_DSI1>;
1818 reset-names = "apb";
1819 rockchip,grf = <&grf>;
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1822 status = "disabled";
1824 ports {
1825 #address-cells = <1>;
1826 #size-cells = <0>;
1828 mipi1_in: port@0 {
1829 reg = <0>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1833 mipi1_in_vopb: endpoint@0 {
1834 reg = <0>;
1835 remote-endpoint = <&vopb_out_mipi1>;
1836 };
1838 mipi1_in_vopl: endpoint@1 {
1839 reg = <1>;
1840 remote-endpoint = <&vopl_out_mipi1>;
1841 };
1842 };
1843 };
1844 };
1846 edp: edp@ff970000 {
1847 compatible = "rockchip,rk3399-edp";
1848 reg = <0x0 0xff970000 0x0 0x8000>;
1849 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1850 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1851 clock-names = "dp", "pclk", "grf";
1852 pinctrl-names = "default";
1853 pinctrl-0 = <&edp_hpd>;
1854 power-domains = <&power RK3399_PD_EDP>;
1855 resets = <&cru SRST_P_EDP_CTRL>;
1856 reset-names = "dp";
1857 rockchip,grf = <&grf>;
1858 status = "disabled";
1860 ports {
1861 #address-cells = <1>;
1862 #size-cells = <0>;
1863 edp_in: port@0 {
1864 reg = <0>;
1865 #address-cells = <1>;
1866 #size-cells = <0>;
1868 edp_in_vopb: endpoint@0 {
1869 reg = <0>;
1870 remote-endpoint = <&vopb_out_edp>;
1871 };
1873 edp_in_vopl: endpoint@1 {
1874 reg = <1>;
1875 remote-endpoint = <&vopl_out_edp>;
1876 };
1877 };
1878 };
1879 };
1881 gpu: gpu@ff9a0000 {
1882 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1883 reg = <0x0 0xff9a0000 0x0 0x10000>;
1884 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1885 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1886 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1887 interrupt-names = "gpu", "job", "mmu";
1888 clocks = <&cru ACLK_GPU>;
1889 power-domains = <&power RK3399_PD_GPU>;
1890 status = "disabled";
1891 };
1893 pinctrl: pinctrl {
1894 compatible = "rockchip,rk3399-pinctrl";
1895 rockchip,grf = <&grf>;
1896 rockchip,pmu = <&pmugrf>;
1897 #address-cells = <2>;
1898 #size-cells = <2>;
1899 ranges;
1901 gpio0: gpio0@ff720000 {
1902 compatible = "rockchip,gpio-bank";
1903 reg = <0x0 0xff720000 0x0 0x100>;
1904 clocks = <&pmucru PCLK_GPIO0_PMU>;
1905 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1907 gpio-controller;
1908 #gpio-cells = <0x2>;
1910 interrupt-controller;
1911 #interrupt-cells = <0x2>;
1912 };
1914 gpio1: gpio1@ff730000 {
1915 compatible = "rockchip,gpio-bank";
1916 reg = <0x0 0xff730000 0x0 0x100>;
1917 clocks = <&pmucru PCLK_GPIO1_PMU>;
1918 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1920 gpio-controller;
1921 #gpio-cells = <0x2>;
1923 interrupt-controller;
1924 #interrupt-cells = <0x2>;
1925 };
1927 gpio2: gpio2@ff780000 {
1928 compatible = "rockchip,gpio-bank";
1929 reg = <0x0 0xff780000 0x0 0x100>;
1930 clocks = <&cru PCLK_GPIO2>;
1931 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1933 gpio-controller;
1934 #gpio-cells = <0x2>;
1936 interrupt-controller;
1937 #interrupt-cells = <0x2>;
1938 };
1940 gpio3: gpio3@ff788000 {
1941 compatible = "rockchip,gpio-bank";
1942 reg = <0x0 0xff788000 0x0 0x100>;
1943 clocks = <&cru PCLK_GPIO3>;
1944 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1946 gpio-controller;
1947 #gpio-cells = <0x2>;
1949 interrupt-controller;
1950 #interrupt-cells = <0x2>;
1951 };
1953 gpio4: gpio4@ff790000 {
1954 compatible = "rockchip,gpio-bank";
1955 reg = <0x0 0xff790000 0x0 0x100>;
1956 clocks = <&cru PCLK_GPIO4>;
1957 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1959 gpio-controller;
1960 #gpio-cells = <0x2>;
1962 interrupt-controller;
1963 #interrupt-cells = <0x2>;
1964 };
1966 pcfg_pull_up: pcfg-pull-up {
1967 bias-pull-up;
1968 };
1970 pcfg_pull_down: pcfg-pull-down {
1971 bias-pull-down;
1972 };
1974 pcfg_pull_none: pcfg-pull-none {
1975 bias-disable;
1976 };
1978 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1979 bias-disable;
1980 drive-strength = <12>;
1981 };
1983 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1984 bias-disable;
1985 drive-strength = <13>;
1986 };
1988 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1989 bias-disable;
1990 drive-strength = <18>;
1991 };
1993 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1994 bias-disable;
1995 drive-strength = <20>;
1996 };
1998 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1999 bias-pull-up;
2000 drive-strength = <2>;
2001 };
2003 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2004 bias-pull-up;
2005 drive-strength = <8>;
2006 };
2008 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2009 bias-pull-up;
2010 drive-strength = <18>;
2011 };
2013 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2014 bias-pull-up;
2015 drive-strength = <20>;
2016 };
2018 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2019 bias-pull-down;
2020 drive-strength = <4>;
2021 };
2023 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2024 bias-pull-down;
2025 drive-strength = <8>;
2026 };
2028 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2029 bias-pull-down;
2030 drive-strength = <12>;
2031 };
2033 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2034 bias-pull-down;
2035 drive-strength = <18>;
2036 };
2038 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2039 bias-pull-down;
2040 drive-strength = <20>;
2041 };
2043 pcfg_output_high: pcfg-output-high {
2044 output-high;
2045 };
2047 pcfg_output_low: pcfg-output-low {
2048 output-low;
2049 };
2051 clock {
2052 clk_32k: clk-32k {
2053 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2054 };
2055 };
2057 edp {
2058 edp_hpd: edp-hpd {
2059 rockchip,pins =
2060 <4 RK_PC7 2 &pcfg_pull_none>;
2061 };
2062 };
2064 gmac {
2065 rgmii_pins: rgmii-pins {
2066 rockchip,pins =
2067 /* mac_txclk */
2068 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2069 /* mac_rxclk */
2070 <3 RK_PB6 1 &pcfg_pull_none>,
2071 /* mac_mdio */
2072 <3 RK_PB5 1 &pcfg_pull_none>,
2073 /* mac_txen */
2074 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2075 /* mac_clk */
2076 <3 RK_PB3 1 &pcfg_pull_none>,
2077 /* mac_rxdv */
2078 <3 RK_PB1 1 &pcfg_pull_none>,
2079 /* mac_mdc */
2080 <3 RK_PB0 1 &pcfg_pull_none>,
2081 /* mac_rxd1 */
2082 <3 RK_PA7 1 &pcfg_pull_none>,
2083 /* mac_rxd0 */
2084 <3 RK_PA6 1 &pcfg_pull_none>,
2085 /* mac_txd1 */
2086 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2087 /* mac_txd0 */
2088 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2089 /* mac_rxd3 */
2090 <3 RK_PA3 1 &pcfg_pull_none>,
2091 /* mac_rxd2 */
2092 <3 RK_PA2 1 &pcfg_pull_none>,
2093 /* mac_txd3 */
2094 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2095 /* mac_txd2 */
2096 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2097 };
2099 rmii_pins: rmii-pins {
2100 rockchip,pins =
2101 /* mac_mdio */
2102 <3 RK_PB5 1 &pcfg_pull_none>,
2103 /* mac_txen */
2104 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2105 /* mac_clk */
2106 <3 RK_PB3 1 &pcfg_pull_none>,
2107 /* mac_rxer */
2108 <3 RK_PB2 1 &pcfg_pull_none>,
2109 /* mac_rxdv */
2110 <3 RK_PB1 1 &pcfg_pull_none>,
2111 /* mac_mdc */
2112 <3 RK_PB0 1 &pcfg_pull_none>,
2113 /* mac_rxd1 */
2114 <3 RK_PA7 1 &pcfg_pull_none>,
2115 /* mac_rxd0 */
2116 <3 RK_PA6 1 &pcfg_pull_none>,
2117 /* mac_txd1 */
2118 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2119 /* mac_txd0 */
2120 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2121 };
2122 };
2124 i2c0 {
2125 i2c0_xfer: i2c0-xfer {
2126 rockchip,pins =
2127 <1 RK_PB7 2 &pcfg_pull_none>,
2128 <1 RK_PC0 2 &pcfg_pull_none>;
2129 };
2130 };
2132 i2c1 {
2133 i2c1_xfer: i2c1-xfer {
2134 rockchip,pins =
2135 <4 RK_PA2 1 &pcfg_pull_none>,
2136 <4 RK_PA1 1 &pcfg_pull_none>;
2137 };
2138 };
2140 i2c2 {
2141 i2c2_xfer: i2c2-xfer {
2142 rockchip,pins =
2143 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2144 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2145 };
2146 };
2148 i2c3 {
2149 i2c3_xfer: i2c3-xfer {
2150 rockchip,pins =
2151 <4 RK_PC1 1 &pcfg_pull_none>,
2152 <4 RK_PC0 1 &pcfg_pull_none>;
2153 };
2154 };
2156 i2c4 {
2157 i2c4_xfer: i2c4-xfer {
2158 rockchip,pins =
2159 <1 RK_PB4 1 &pcfg_pull_none>,
2160 <1 RK_PB3 1 &pcfg_pull_none>;
2161 };
2162 };
2164 i2c5 {
2165 i2c5_xfer: i2c5-xfer {
2166 rockchip,pins =
2167 <3 RK_PB3 2 &pcfg_pull_none>,
2168 <3 RK_PB2 2 &pcfg_pull_none>;
2169 };
2170 };
2172 i2c6 {
2173 i2c6_xfer: i2c6-xfer {
2174 rockchip,pins =
2175 <2 RK_PB2 2 &pcfg_pull_none>,
2176 <2 RK_PB1 2 &pcfg_pull_none>;
2177 };
2178 };
2180 i2c7 {
2181 i2c7_xfer: i2c7-xfer {
2182 rockchip,pins =
2183 <2 RK_PB0 2 &pcfg_pull_none>,
2184 <2 RK_PA7 2 &pcfg_pull_none>;
2185 };
2186 };
2188 i2c8 {
2189 i2c8_xfer: i2c8-xfer {
2190 rockchip,pins =
2191 <1 RK_PC5 1 &pcfg_pull_none>,
2192 <1 RK_PC4 1 &pcfg_pull_none>;
2193 };
2194 };
2196 i2s0 {
2197 i2s0_2ch_bus: i2s0-2ch-bus {
2198 rockchip,pins =
2199 <3 RK_PD0 1 &pcfg_pull_none>,
2200 <3 RK_PD1 1 &pcfg_pull_none>,
2201 <3 RK_PD2 1 &pcfg_pull_none>,
2202 <3 RK_PD3 1 &pcfg_pull_none>,
2203 <3 RK_PD7 1 &pcfg_pull_none>,
2204 <4 RK_PA0 1 &pcfg_pull_none>;
2205 };
2207 i2s0_8ch_bus: i2s0-8ch-bus {
2208 rockchip,pins =
2209 <3 RK_PD0 1 &pcfg_pull_none>,
2210 <3 RK_PD1 1 &pcfg_pull_none>,
2211 <3 RK_PD2 1 &pcfg_pull_none>,
2212 <3 RK_PD3 1 &pcfg_pull_none>,
2213 <3 RK_PD4 1 &pcfg_pull_none>,
2214 <3 RK_PD5 1 &pcfg_pull_none>,
2215 <3 RK_PD6 1 &pcfg_pull_none>,
2216 <3 RK_PD7 1 &pcfg_pull_none>,
2217 <4 RK_PA0 1 &pcfg_pull_none>;
2218 };
2219 };
2221 i2s1 {
2222 i2s1_2ch_bus: i2s1-2ch-bus {
2223 rockchip,pins =
2224 <4 RK_PA3 1 &pcfg_pull_none>,
2225 <4 RK_PA4 1 &pcfg_pull_none>,
2226 <4 RK_PA5 1 &pcfg_pull_none>,
2227 <4 RK_PA6 1 &pcfg_pull_none>,
2228 <4 RK_PA7 1 &pcfg_pull_none>;
2229 };
2230 };
2232 sdio0 {
2233 sdio0_bus1: sdio0-bus1 {
2234 rockchip,pins =
2235 <2 RK_PC4 1 &pcfg_pull_up>;
2236 };
2238 sdio0_bus4: sdio0-bus4 {
2239 rockchip,pins =
2240 <2 RK_PC4 1 &pcfg_pull_up>,
2241 <2 RK_PC5 1 &pcfg_pull_up>,
2242 <2 RK_PC6 1 &pcfg_pull_up>,
2243 <2 RK_PC7 1 &pcfg_pull_up>;
2244 };
2246 sdio0_cmd: sdio0-cmd {
2247 rockchip,pins =
2248 <2 RK_PD0 1 &pcfg_pull_up>;
2249 };
2251 sdio0_clk: sdio0-clk {
2252 rockchip,pins =
2253 <2 RK_PD1 1 &pcfg_pull_none>;
2254 };
2256 sdio0_cd: sdio0-cd {
2257 rockchip,pins =
2258 <2 RK_PD2 1 &pcfg_pull_up>;
2259 };
2261 sdio0_pwr: sdio0-pwr {
2262 rockchip,pins =
2263 <2 RK_PD3 1 &pcfg_pull_up>;
2264 };
2266 sdio0_bkpwr: sdio0-bkpwr {
2267 rockchip,pins =
2268 <2 RK_PD4 1 &pcfg_pull_up>;
2269 };
2271 sdio0_wp: sdio0-wp {
2272 rockchip,pins =
2273 <0 RK_PA3 1 &pcfg_pull_up>;
2274 };
2276 sdio0_int: sdio0-int {
2277 rockchip,pins =
2278 <0 RK_PA4 1 &pcfg_pull_up>;
2279 };
2280 };
2282 sdmmc {
2283 sdmmc_bus1: sdmmc-bus1 {
2284 rockchip,pins =
2285 <4 RK_PB0 1 &pcfg_pull_up>;
2286 };
2288 sdmmc_bus4: sdmmc-bus4 {
2289 rockchip,pins =
2290 <4 RK_PB0 1 &pcfg_pull_up>,
2291 <4 RK_PB1 1 &pcfg_pull_up>,
2292 <4 RK_PB2 1 &pcfg_pull_up>,
2293 <4 RK_PB3 1 &pcfg_pull_up>;
2294 };
2296 sdmmc_clk: sdmmc-clk {
2297 rockchip,pins =
2298 <4 RK_PB4 1 &pcfg_pull_none>;
2299 };
2301 sdmmc_cmd: sdmmc-cmd {
2302 rockchip,pins =
2303 <4 RK_PB5 1 &pcfg_pull_up>;
2304 };
2306 sdmmc_cd: sdmmc-cd {
2307 rockchip,pins =
2308 <0 RK_PA7 1 &pcfg_pull_up>;
2309 };
2311 sdmmc_wp: sdmmc-wp {
2312 rockchip,pins =
2313 <0 RK_PB0 1 &pcfg_pull_up>;
2314 };
2315 };
2317 sleep {
2318 ap_pwroff: ap-pwroff {
2319 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2320 };
2322 ddrio_pwroff: ddrio-pwroff {
2323 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2324 };
2325 };
2327 spdif {
2328 spdif_bus: spdif-bus {
2329 rockchip,pins =
2330 <4 RK_PC5 1 &pcfg_pull_none>;
2331 };
2333 spdif_bus_1: spdif-bus-1 {
2334 rockchip,pins =
2335 <3 RK_PC0 3 &pcfg_pull_none>;
2336 };
2337 };
2339 spi0 {
2340 spi0_clk: spi0-clk {
2341 rockchip,pins =
2342 <3 RK_PA6 2 &pcfg_pull_up>;
2343 };
2344 spi0_cs0: spi0-cs0 {
2345 rockchip,pins =
2346 <3 RK_PA7 2 &pcfg_pull_up>;
2347 };
2348 spi0_cs1: spi0-cs1 {
2349 rockchip,pins =
2350 <3 RK_PB0 2 &pcfg_pull_up>;
2351 };
2352 spi0_tx: spi0-tx {
2353 rockchip,pins =
2354 <3 RK_PA5 2 &pcfg_pull_up>;
2355 };
2356 spi0_rx: spi0-rx {
2357 rockchip,pins =
2358 <3 RK_PA4 2 &pcfg_pull_up>;
2359 };
2360 };
2362 spi1 {
2363 spi1_clk: spi1-clk {
2364 rockchip,pins =
2365 <1 RK_PB1 2 &pcfg_pull_up>;
2366 };
2367 spi1_cs0: spi1-cs0 {
2368 rockchip,pins =
2369 <1 RK_PB2 2 &pcfg_pull_up>;
2370 };
2371 spi1_rx: spi1-rx {
2372 rockchip,pins =
2373 <1 RK_PA7 2 &pcfg_pull_up>;
2374 };
2375 spi1_tx: spi1-tx {
2376 rockchip,pins =
2377 <1 RK_PB0 2 &pcfg_pull_up>;
2378 };
2379 };
2381 spi2 {
2382 spi2_clk: spi2-clk {
2383 rockchip,pins =
2384 <2 RK_PB3 1 &pcfg_pull_up>;
2385 };
2386 spi2_cs0: spi2-cs0 {
2387 rockchip,pins =
2388 <2 RK_PB4 1 &pcfg_pull_up>;
2389 };
2390 spi2_rx: spi2-rx {
2391 rockchip,pins =
2392 <2 RK_PB1 1 &pcfg_pull_up>;
2393 };
2394 spi2_tx: spi2-tx {
2395 rockchip,pins =
2396 <2 RK_PB2 1 &pcfg_pull_up>;
2397 };
2398 };
2400 spi3 {
2401 spi3_clk: spi3-clk {
2402 rockchip,pins =
2403 <1 RK_PC1 1 &pcfg_pull_up>;
2404 };
2405 spi3_cs0: spi3-cs0 {
2406 rockchip,pins =
2407 <1 RK_PC2 1 &pcfg_pull_up>;
2408 };
2409 spi3_rx: spi3-rx {
2410 rockchip,pins =
2411 <1 RK_PB7 1 &pcfg_pull_up>;
2412 };
2413 spi3_tx: spi3-tx {
2414 rockchip,pins =
2415 <1 RK_PC0 1 &pcfg_pull_up>;
2416 };
2417 };
2419 spi4 {
2420 spi4_clk: spi4-clk {
2421 rockchip,pins =
2422 <3 RK_PA2 2 &pcfg_pull_up>;
2423 };
2424 spi4_cs0: spi4-cs0 {
2425 rockchip,pins =
2426 <3 RK_PA3 2 &pcfg_pull_up>;
2427 };
2428 spi4_rx: spi4-rx {
2429 rockchip,pins =
2430 <3 RK_PA0 2 &pcfg_pull_up>;
2431 };
2432 spi4_tx: spi4-tx {
2433 rockchip,pins =
2434 <3 RK_PA1 2 &pcfg_pull_up>;
2435 };
2436 };
2438 spi5 {
2439 spi5_clk: spi5-clk {
2440 rockchip,pins =
2441 <2 RK_PC6 2 &pcfg_pull_up>;
2442 };
2443 spi5_cs0: spi5-cs0 {
2444 rockchip,pins =
2445 <2 RK_PC7 2 &pcfg_pull_up>;
2446 };
2447 spi5_rx: spi5-rx {
2448 rockchip,pins =
2449 <2 RK_PC4 2 &pcfg_pull_up>;
2450 };
2451 spi5_tx: spi5-tx {
2452 rockchip,pins =
2453 <2 RK_PC5 2 &pcfg_pull_up>;
2454 };
2455 };
2457 testclk {
2458 test_clkout0: test-clkout0 {
2459 rockchip,pins =
2460 <0 RK_PA0 1 &pcfg_pull_none>;
2461 };
2463 test_clkout1: test-clkout1 {
2464 rockchip,pins =
2465 <2 RK_PD1 2 &pcfg_pull_none>;
2466 };
2468 test_clkout2: test-clkout2 {
2469 rockchip,pins =
2470 <0 RK_PB0 3 &pcfg_pull_none>;
2471 };
2472 };
2474 tsadc {
2475 otp_gpio: otp-gpio {
2476 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2477 };
2479 otp_out: otp-out {
2480 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2481 };
2482 };
2484 uart0 {
2485 uart0_xfer: uart0-xfer {
2486 rockchip,pins =
2487 <2 RK_PC0 1 &pcfg_pull_up>,
2488 <2 RK_PC1 1 &pcfg_pull_none>;
2489 };
2491 uart0_cts: uart0-cts {
2492 rockchip,pins =
2493 <2 RK_PC2 1 &pcfg_pull_none>;
2494 };
2496 uart0_rts: uart0-rts {
2497 rockchip,pins =
2498 <2 RK_PC3 1 &pcfg_pull_none>;
2499 };
2500 };
2502 uart1 {
2503 uart1_xfer: uart1-xfer {
2504 rockchip,pins =
2505 <3 RK_PB4 2 &pcfg_pull_up>,
2506 <3 RK_PB5 2 &pcfg_pull_none>;
2507 };
2508 };
2510 uart2a {
2511 uart2a_xfer: uart2a-xfer {
2512 rockchip,pins =
2513 <4 RK_PB0 2 &pcfg_pull_up>,
2514 <4 RK_PB1 2 &pcfg_pull_none>;
2515 };
2516 };
2518 uart2b {
2519 uart2b_xfer: uart2b-xfer {
2520 rockchip,pins =
2521 <4 RK_PC0 2 &pcfg_pull_up>,
2522 <4 RK_PC1 2 &pcfg_pull_none>;
2523 };
2524 };
2526 uart2c {
2527 uart2c_xfer: uart2c-xfer {
2528 rockchip,pins =
2529 <4 RK_PC3 1 &pcfg_pull_up>,
2530 <4 RK_PC4 1 &pcfg_pull_none>;
2531 };
2532 };
2534 uart3 {
2535 uart3_xfer: uart3-xfer {
2536 rockchip,pins =
2537 <3 RK_PB6 2 &pcfg_pull_up>,
2538 <3 RK_PB7 2 &pcfg_pull_none>;
2539 };
2541 uart3_cts: uart3-cts {
2542 rockchip,pins =
2543 <3 RK_PC0 2 &pcfg_pull_none>;
2544 };
2546 uart3_rts: uart3-rts {
2547 rockchip,pins =
2548 <3 RK_PC1 2 &pcfg_pull_none>;
2549 };
2550 };
2552 uart4 {
2553 uart4_xfer: uart4-xfer {
2554 rockchip,pins =
2555 <1 RK_PA7 1 &pcfg_pull_up>,
2556 <1 RK_PB0 1 &pcfg_pull_none>;
2557 };
2558 };
2560 uarthdcp {
2561 uarthdcp_xfer: uarthdcp-xfer {
2562 rockchip,pins =
2563 <4 RK_PC5 2 &pcfg_pull_up>,
2564 <4 RK_PC6 2 &pcfg_pull_none>;
2565 };
2566 };
2568 pwm0 {
2569 pwm0_pin: pwm0-pin {
2570 rockchip,pins =
2571 <4 RK_PC2 1 &pcfg_pull_none>;
2572 };
2574 pwm0_pin_pull_down: pwm0-pin-pull-down {
2575 rockchip,pins =
2576 <4 RK_PC2 1 &pcfg_pull_down>;
2577 };
2579 vop0_pwm_pin: vop0-pwm-pin {
2580 rockchip,pins =
2581 <4 RK_PC2 2 &pcfg_pull_none>;
2582 };
2584 vop1_pwm_pin: vop1-pwm-pin {
2585 rockchip,pins =
2586 <4 RK_PC2 3 &pcfg_pull_none>;
2587 };
2588 };
2590 pwm1 {
2591 pwm1_pin: pwm1-pin {
2592 rockchip,pins =
2593 <4 RK_PC6 1 &pcfg_pull_none>;
2594 };
2596 pwm1_pin_pull_down: pwm1-pin-pull-down {
2597 rockchip,pins =
2598 <4 RK_PC6 1 &pcfg_pull_down>;
2599 };
2600 };
2602 pwm2 {
2603 pwm2_pin: pwm2-pin {
2604 rockchip,pins =
2605 <1 RK_PC3 1 &pcfg_pull_none>;
2606 };
2608 pwm2_pin_pull_down: pwm2-pin-pull-down {
2609 rockchip,pins =
2610 <1 RK_PC3 1 &pcfg_pull_down>;
2611 };
2612 };
2614 pwm3a {
2615 pwm3a_pin: pwm3a-pin {
2616 rockchip,pins =
2617 <0 RK_PA6 1 &pcfg_pull_none>;
2618 };
2619 };
2621 pwm3b {
2622 pwm3b_pin: pwm3b-pin {
2623 rockchip,pins =
2624 <1 RK_PB6 1 &pcfg_pull_none>;
2625 };
2626 };
2628 hdmi {
2629 hdmi_i2c_xfer: hdmi-i2c-xfer {
2630 rockchip,pins =
2631 <4 RK_PC1 3 &pcfg_pull_none>,
2632 <4 RK_PC0 3 &pcfg_pull_none>;
2633 };
2635 hdmi_cec: hdmi-cec {
2636 rockchip,pins =
2637 <4 RK_PC7 1 &pcfg_pull_none>;
2638 };
2639 };
2641 pcie {
2642 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2643 rockchip,pins =
2644 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2645 };
2647 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2648 rockchip,pins =
2649 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2650 };
2651 };
2653 };
2654 };