arch/arm64/boot/dts/synaptics/berlin4ct.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2015 Marvell Technology Group Ltd.
   4  *
   5  * Author: Jisheng Zhang <jszhang@marvell.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "marvell,berlin4ct", "marvell,berlin";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18         };
  19
  20         psci {
  21                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         compatible = "arm,cortex-a53";
  31                         device_type = "cpu";
  32                         reg = <0x0>;
  33                         enable-method = "psci";
  34                         next-level-cache = <&l2>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <0x1>;
  42                         enable-method = "psci";
  43                         next-level-cache = <&l2>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         compatible = "arm,cortex-a53";
  49                         device_type = "cpu";
  50                         reg = <0x2>;
  51                         enable-method = "psci";
  52                         next-level-cache = <&l2>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         compatible = "arm,cortex-a53";
  58                         device_type = "cpu";
  59                         reg = <0x3>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&l2>;
  62                         cpu-idle-states = <&CPU_SLEEP_0>;
  63                 };
  64
  65                 l2: cache {
  66                         compatible = "cache";
  67                 };
  68
  69                 idle-states {
  70                         entry-method = "psci";
  71                         CPU_SLEEP_0: cpu-sleep-0 {
  72                                 compatible = "arm,idle-state";
  73                                 local-timer-stop;
  74                                 arm,psci-suspend-param = <0x0010000>;
  75                                 entry-latency-us = <75>;
  76                                 exit-latency-us = <155>;
  77                                 min-residency-us = <1000>;
  78                         };
  79                 };
  80         };
  81
  82         osc: osc {
  83                 compatible = "fixed-clock";
  84                 #clock-cells = <0>;
  85                 clock-frequency = <25000000>;
  86         };
  87
  88         pmu {
  89                 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
  90                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  91                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  92                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  93                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  94                 interrupt-affinity = <&cpu0>,
  95                                      <&cpu1>,
  96                                      <&cpu2>,
  97                                      <&cpu3>;
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv8-timer";
 102                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 103                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 104                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 105                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 106         };
 107
 108         soc@f7000000 {
 109                 compatible = "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges = <0 0 0xf7000000 0x1000000>;
 113
 114                 gic: interrupt-controller@901000 {
 115                         compatible = "arm,gic-400";
 116                         #interrupt-cells = <3>;
 117                         interrupt-controller;
 118                         reg = <0x901000 0x1000>,
 119                               <0x902000 0x2000>,
 120                               <0x904000 0x2000>,
 121                               <0x906000 0x2000>;
 122                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 123                 };
 124
 125                 apb@e80000 {
 126                         compatible = "simple-bus";
 127                         #address-cells = <1>;
 128                         #size-cells = <1>;
 129
 130                         ranges = <0 0xe80000 0x10000>;
 131                         interrupt-parent = <&aic>;
 132
 133                         gpio0: gpio@400 {
 134                                 compatible = "snps,dw-apb-gpio";
 135                                 reg = <0x0400 0x400>;
 136                                 #address-cells = <1>;
 137                                 #size-cells = <0>;
 138
 139                                 porta: gpio-port@0 {
 140                                         compatible = "snps,dw-apb-gpio-port";
 141                                         gpio-controller;
 142                                         #gpio-cells = <2>;
 143                                         snps,nr-gpios = <32>;
 144                                         reg = <0>;
 145                                         interrupt-controller;
 146                                         #interrupt-cells = <2>;
 147                                         interrupts = <0>;
 148                                 };
 149                         };
 150
 151                         gpio1: gpio@800 {
 152                                 compatible = "snps,dw-apb-gpio";
 153                                 reg = <0x0800 0x400>;
 154                                 #address-cells = <1>;
 155                                 #size-cells = <0>;
 156
 157                                 portb: gpio-port@1 {
 158                                         compatible = "snps,dw-apb-gpio-port";
 159                                         gpio-controller;
 160                                         #gpio-cells = <2>;
 161                                         snps,nr-gpios = <32>;
 162                                         reg = <0>;
 163                                         interrupt-controller;
 164                                         #interrupt-cells = <2>;
 165                                         interrupts = <1>;
 166                                 };
 167                         };
 168
 169                         gpio2: gpio@c00 {
 170                                 compatible = "snps,dw-apb-gpio";
 171                                 reg = <0x0c00 0x400>;
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174
 175                                 portc: gpio-port@2 {
 176                                         compatible = "snps,dw-apb-gpio-port";
 177                                         gpio-controller;
 178                                         #gpio-cells = <2>;
 179                                         snps,nr-gpios = <32>;
 180                                         reg = <0>;
 181                                         interrupt-controller;
 182                                         #interrupt-cells = <2>;
 183                                         interrupts = <2>;
 184                                 };
 185                         };
 186
 187                         gpio3: gpio@1000 {
 188                                 compatible = "snps,dw-apb-gpio";
 189                                 reg = <0x1000 0x400>;
 190                                 #address-cells = <1>;
 191                                 #size-cells = <0>;
 192
 193                                 portd: gpio-port@3 {
 194                                         compatible = "snps,dw-apb-gpio-port";
 195                                         gpio-controller;
 196                                         #gpio-cells = <2>;
 197                                         snps,nr-gpios = <32>;
 198                                         reg = <0>;
 199                                         interrupt-controller;
 200                                         #interrupt-cells = <2>;
 201                                         interrupts = <3>;
 202                                 };
 203                         };
 204
 205                         aic: interrupt-controller@3800 {
 206                                 compatible = "snps,dw-apb-ictl";
 207                                 reg = <0x3800 0x30>;
 208                                 interrupt-controller;
 209                                 #interrupt-cells = <1>;
 210                                 interrupt-parent = <&gic>;
 211                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 212                         };
 213                 };
 214
 215                 soc_pinctrl: pin-controller@ea8000 {
 216                         compatible = "marvell,berlin4ct-soc-pinctrl";
 217                         reg = <0xea8000 0x14>;
 218                 };
 219
 220                 avio_pinctrl: pin-controller@ea8400 {
 221                         compatible = "marvell,berlin4ct-avio-pinctrl";
 222                         reg = <0xea8400 0x8>;
 223                 };
 224
 225                 apb@fc0000 {
 226                         compatible = "simple-bus";
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229                         ranges = <0 0xfc0000 0x10000>;
 230                         interrupt-parent = <&sic>;
 231
 232                         sic: interrupt-controller@1000 {
 233                                 compatible = "snps,dw-apb-ictl";
 234                                 reg = <0x1000 0x30>;
 235                                 interrupt-controller;
 236                                 #interrupt-cells = <1>;
 237                                 interrupt-parent = <&gic>;
 238                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 239                         };
 240
 241                         wdt0: watchdog@3000 {
 242                                 compatible = "snps,dw-wdt";
 243                                 reg = <0x3000 0x100>;
 244                                 clocks = <&osc>;
 245                                 interrupts = <0>;
 246                         };
 247
 248                         wdt1: watchdog@4000 {
 249                                 compatible = "snps,dw-wdt";
 250                                 reg = <0x4000 0x100>;
 251                                 clocks = <&osc>;
 252                                 interrupts = <1>;
 253                         };
 254
 255                         wdt2: watchdog@5000 {
 256                                 compatible = "snps,dw-wdt";
 257                                 reg = <0x5000 0x100>;
 258                                 clocks = <&osc>;
 259                                 interrupts = <2>;
 260                         };
 261
 262                         sm_gpio0: gpio@8000 {
 263                                 compatible = "snps,dw-apb-gpio";
 264                                 reg = <0x8000 0x400>;
 265                                 #address-cells = <1>;
 266                                 #size-cells = <0>;
 267
 268                                 porte: gpio-port@4 {
 269                                         compatible = "snps,dw-apb-gpio-port";
 270                                         gpio-controller;
 271                                         #gpio-cells = <2>;
 272                                         snps,nr-gpios = <32>;
 273                                         reg = <0>;
 274                                 };
 275                         };
 276
 277                         sm_gpio1: gpio@9000 {
 278                                 compatible = "snps,dw-apb-gpio";
 279                                 reg = <0x9000 0x400>;
 280                                 #address-cells = <1>;
 281                                 #size-cells = <0>;
 282
 283                                 portf: gpio-port@5 {
 284                                         compatible = "snps,dw-apb-gpio-port";
 285                                         gpio-controller;
 286                                         #gpio-cells = <2>;
 287                                         snps,nr-gpios = <32>;
 288                                         reg = <0>;
 289                                 };
 290                         };
 291
 292                         uart0: uart@d000 {
 293                                 compatible = "snps,dw-apb-uart";
 294                                 reg = <0xd000 0x100>;
 295                                 interrupts = <8>;
 296                                 clocks = <&osc>;
 297                                 reg-shift = <2>;
 298                                 status = "disabled";
 299                                 pinctrl-0 = <&uart0_pmux>;
 300                                 pinctrl-names = "default";
 301                         };
 302                 };
 303
 304                 system_pinctrl: pin-controller@fe2200 {
 305                         compatible = "marvell,berlin4ct-system-pinctrl";
 306                         reg = <0xfe2200 0xc>;
 307
 308                         uart0_pmux: uart0-pmux {
 309                                 groups = "SM_URT0_TXD", "SM_URT0_RXD";
 310                                 function = "uart0";
 311                         };
 312                 };
 313         };
 314 };