| blob | 9aa67340a4d8c120187c943422f8b88784bfd31b |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
15 / {
16 compatible = "xlnx,zynqmp";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu0: cpu@0 {
25 compatible = "arm,cortex-a53";
26 device_type = "cpu";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
29 reg = <0x0>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
31 };
33 cpu1: cpu@1 {
34 compatible = "arm,cortex-a53";
35 device_type = "cpu";
36 enable-method = "psci";
37 reg = <0x1>;
38 operating-points-v2 = <&cpu_opp_table>;
39 cpu-idle-states = <&CPU_SLEEP_0>;
40 };
42 cpu2: cpu@2 {
43 compatible = "arm,cortex-a53";
44 device_type = "cpu";
45 enable-method = "psci";
46 reg = <0x2>;
47 operating-points-v2 = <&cpu_opp_table>;
48 cpu-idle-states = <&CPU_SLEEP_0>;
49 };
51 cpu3: cpu@3 {
52 compatible = "arm,cortex-a53";
53 device_type = "cpu";
54 enable-method = "psci";
55 reg = <0x3>;
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
58 };
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP_0: cpu-sleep-0 {
64 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x40000000>;
66 local-timer-stop;
67 entry-latency-us = <300>;
68 exit-latency-us = <600>;
69 min-residency-us = <10000>;
70 };
71 };
72 };
74 cpu_opp_table: cpu-opp-table {
75 compatible = "operating-points-v2";
76 opp-shared;
77 opp00 {
78 opp-hz = /bits/ 64 <1199999988>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <500000>;
81 };
82 opp01 {
83 opp-hz = /bits/ 64 <599999994>;
84 opp-microvolt = <1000000>;
85 clock-latency-ns = <500000>;
86 };
87 opp02 {
88 opp-hz = /bits/ 64 <399999996>;
89 opp-microvolt = <1000000>;
90 clock-latency-ns = <500000>;
91 };
92 opp03 {
93 opp-hz = /bits/ 64 <299999997>;
94 opp-microvolt = <1000000>;
95 clock-latency-ns = <500000>;
96 };
97 };
99 dcc: dcc {
100 compatible = "arm,dcc";
101 status = "disabled";
102 };
104 pmu {
105 compatible = "arm,armv8-pmuv3";
106 interrupt-parent = <&gic>;
107 interrupts = <0 143 4>,
108 <0 144 4>,
109 <0 145 4>,
110 <0 146 4>;
111 };
113 psci {
114 compatible = "arm,psci-0.2";
115 method = "smc";
116 };
118 timer {
119 compatible = "arm,armv8-timer";
120 interrupt-parent = <&gic>;
121 interrupts = <1 13 0xf08>,
122 <1 14 0xf08>,
123 <1 11 0xf08>,
124 <1 10 0xf08>;
125 };
127 amba_apu: amba-apu@0 {
128 compatible = "simple-bus";
129 #address-cells = <2>;
130 #size-cells = <1>;
131 ranges = <0 0 0 0 0xffffffff>;
133 gic: interrupt-controller@f9010000 {
134 compatible = "arm,gic-400", "arm,cortex-a15-gic";
135 #interrupt-cells = <3>;
136 reg = <0x0 0xf9010000 0x10000>,
137 <0x0 0xf9020000 0x20000>,
138 <0x0 0xf9040000 0x20000>,
139 <0x0 0xf9060000 0x20000>;
140 interrupt-controller;
141 interrupt-parent = <&gic>;
142 interrupts = <1 9 0xf04>;
143 };
144 };
146 amba: amba {
147 compatible = "simple-bus";
148 #address-cells = <2>;
149 #size-cells = <2>;
150 ranges;
152 can0: can@ff060000 {
153 compatible = "xlnx,zynq-can-1.0";
154 status = "disabled";
155 clock-names = "can_clk", "pclk";
156 reg = <0x0 0xff060000 0x0 0x1000>;
157 interrupts = <0 23 4>;
158 interrupt-parent = <&gic>;
159 tx-fifo-depth = <0x40>;
160 rx-fifo-depth = <0x40>;
161 };
163 can1: can@ff070000 {
164 compatible = "xlnx,zynq-can-1.0";
165 status = "disabled";
166 clock-names = "can_clk", "pclk";
167 reg = <0x0 0xff070000 0x0 0x1000>;
168 interrupts = <0 24 4>;
169 interrupt-parent = <&gic>;
170 tx-fifo-depth = <0x40>;
171 rx-fifo-depth = <0x40>;
172 };
174 cci: cci@fd6e0000 {
175 compatible = "arm,cci-400";
176 reg = <0x0 0xfd6e0000 0x0 0x9000>;
177 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
178 #address-cells = <1>;
179 #size-cells = <1>;
181 pmu@9000 {
182 compatible = "arm,cci-400-pmu,r1";
183 reg = <0x9000 0x5000>;
184 interrupt-parent = <&gic>;
185 interrupts = <0 123 4>,
186 <0 123 4>,
187 <0 123 4>,
188 <0 123 4>,
189 <0 123 4>;
190 };
191 };
193 /* GDMA */
194 fpd_dma_chan1: dma@fd500000 {
195 status = "disabled";
196 compatible = "xlnx,zynqmp-dma-1.0";
197 reg = <0x0 0xfd500000 0x0 0x1000>;
198 interrupt-parent = <&gic>;
199 interrupts = <0 124 4>;
200 clock-names = "clk_main", "clk_apb";
201 xlnx,bus-width = <128>;
202 };
204 fpd_dma_chan2: dma@fd510000 {
205 status = "disabled";
206 compatible = "xlnx,zynqmp-dma-1.0";
207 reg = <0x0 0xfd510000 0x0 0x1000>;
208 interrupt-parent = <&gic>;
209 interrupts = <0 125 4>;
210 clock-names = "clk_main", "clk_apb";
211 xlnx,bus-width = <128>;
212 };
214 fpd_dma_chan3: dma@fd520000 {
215 status = "disabled";
216 compatible = "xlnx,zynqmp-dma-1.0";
217 reg = <0x0 0xfd520000 0x0 0x1000>;
218 interrupt-parent = <&gic>;
219 interrupts = <0 126 4>;
220 clock-names = "clk_main", "clk_apb";
221 xlnx,bus-width = <128>;
222 };
224 fpd_dma_chan4: dma@fd530000 {
225 status = "disabled";
226 compatible = "xlnx,zynqmp-dma-1.0";
227 reg = <0x0 0xfd530000 0x0 0x1000>;
228 interrupt-parent = <&gic>;
229 interrupts = <0 127 4>;
230 clock-names = "clk_main", "clk_apb";
231 xlnx,bus-width = <128>;
232 };
234 fpd_dma_chan5: dma@fd540000 {
235 status = "disabled";
236 compatible = "xlnx,zynqmp-dma-1.0";
237 reg = <0x0 0xfd540000 0x0 0x1000>;
238 interrupt-parent = <&gic>;
239 interrupts = <0 128 4>;
240 clock-names = "clk_main", "clk_apb";
241 xlnx,bus-width = <128>;
242 };
244 fpd_dma_chan6: dma@fd550000 {
245 status = "disabled";
246 compatible = "xlnx,zynqmp-dma-1.0";
247 reg = <0x0 0xfd550000 0x0 0x1000>;
248 interrupt-parent = <&gic>;
249 interrupts = <0 129 4>;
250 clock-names = "clk_main", "clk_apb";
251 xlnx,bus-width = <128>;
252 };
254 fpd_dma_chan7: dma@fd560000 {
255 status = "disabled";
256 compatible = "xlnx,zynqmp-dma-1.0";
257 reg = <0x0 0xfd560000 0x0 0x1000>;
258 interrupt-parent = <&gic>;
259 interrupts = <0 130 4>;
260 clock-names = "clk_main", "clk_apb";
261 xlnx,bus-width = <128>;
262 };
264 fpd_dma_chan8: dma@fd570000 {
265 status = "disabled";
266 compatible = "xlnx,zynqmp-dma-1.0";
267 reg = <0x0 0xfd570000 0x0 0x1000>;
268 interrupt-parent = <&gic>;
269 interrupts = <0 131 4>;
270 clock-names = "clk_main", "clk_apb";
271 xlnx,bus-width = <128>;
272 };
274 /* LPDDMA default allows only secured access. inorder to enable
275 * These dma channels, Users should ensure that these dma
276 * Channels are allowed for non secure access.
277 */
278 lpd_dma_chan1: dma@ffa80000 {
279 status = "disabled";
280 compatible = "xlnx,zynqmp-dma-1.0";
281 reg = <0x0 0xffa80000 0x0 0x1000>;
282 interrupt-parent = <&gic>;
283 interrupts = <0 77 4>;
284 clock-names = "clk_main", "clk_apb";
285 xlnx,bus-width = <64>;
286 };
288 lpd_dma_chan2: dma@ffa90000 {
289 status = "disabled";
290 compatible = "xlnx,zynqmp-dma-1.0";
291 reg = <0x0 0xffa90000 0x0 0x1000>;
292 interrupt-parent = <&gic>;
293 interrupts = <0 78 4>;
294 clock-names = "clk_main", "clk_apb";
295 xlnx,bus-width = <64>;
296 };
298 lpd_dma_chan3: dma@ffaa0000 {
299 status = "disabled";
300 compatible = "xlnx,zynqmp-dma-1.0";
301 reg = <0x0 0xffaa0000 0x0 0x1000>;
302 interrupt-parent = <&gic>;
303 interrupts = <0 79 4>;
304 clock-names = "clk_main", "clk_apb";
305 xlnx,bus-width = <64>;
306 };
308 lpd_dma_chan4: dma@ffab0000 {
309 status = "disabled";
310 compatible = "xlnx,zynqmp-dma-1.0";
311 reg = <0x0 0xffab0000 0x0 0x1000>;
312 interrupt-parent = <&gic>;
313 interrupts = <0 80 4>;
314 clock-names = "clk_main", "clk_apb";
315 xlnx,bus-width = <64>;
316 };
318 lpd_dma_chan5: dma@ffac0000 {
319 status = "disabled";
320 compatible = "xlnx,zynqmp-dma-1.0";
321 reg = <0x0 0xffac0000 0x0 0x1000>;
322 interrupt-parent = <&gic>;
323 interrupts = <0 81 4>;
324 clock-names = "clk_main", "clk_apb";
325 xlnx,bus-width = <64>;
326 };
328 lpd_dma_chan6: dma@ffad0000 {
329 status = "disabled";
330 compatible = "xlnx,zynqmp-dma-1.0";
331 reg = <0x0 0xffad0000 0x0 0x1000>;
332 interrupt-parent = <&gic>;
333 interrupts = <0 82 4>;
334 clock-names = "clk_main", "clk_apb";
335 xlnx,bus-width = <64>;
336 };
338 lpd_dma_chan7: dma@ffae0000 {
339 status = "disabled";
340 compatible = "xlnx,zynqmp-dma-1.0";
341 reg = <0x0 0xffae0000 0x0 0x1000>;
342 interrupt-parent = <&gic>;
343 interrupts = <0 83 4>;
344 clock-names = "clk_main", "clk_apb";
345 xlnx,bus-width = <64>;
346 };
348 lpd_dma_chan8: dma@ffaf0000 {
349 status = "disabled";
350 compatible = "xlnx,zynqmp-dma-1.0";
351 reg = <0x0 0xffaf0000 0x0 0x1000>;
352 interrupt-parent = <&gic>;
353 interrupts = <0 84 4>;
354 clock-names = "clk_main", "clk_apb";
355 xlnx,bus-width = <64>;
356 };
358 mc: memory-controller@fd070000 {
359 compatible = "xlnx,zynqmp-ddrc-2.40a";
360 reg = <0x0 0xfd070000 0x0 0x30000>;
361 interrupt-parent = <&gic>;
362 interrupts = <0 112 4>;
363 };
365 gem0: ethernet@ff0b0000 {
366 compatible = "cdns,zynqmp-gem", "cdns,gem";
367 status = "disabled";
368 interrupt-parent = <&gic>;
369 interrupts = <0 57 4>, <0 57 4>;
370 reg = <0x0 0xff0b0000 0x0 0x1000>;
371 clock-names = "pclk", "hclk", "tx_clk";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 };
376 gem1: ethernet@ff0c0000 {
377 compatible = "cdns,zynqmp-gem", "cdns,gem";
378 status = "disabled";
379 interrupt-parent = <&gic>;
380 interrupts = <0 59 4>, <0 59 4>;
381 reg = <0x0 0xff0c0000 0x0 0x1000>;
382 clock-names = "pclk", "hclk", "tx_clk";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 };
387 gem2: ethernet@ff0d0000 {
388 compatible = "cdns,zynqmp-gem", "cdns,gem";
389 status = "disabled";
390 interrupt-parent = <&gic>;
391 interrupts = <0 61 4>, <0 61 4>;
392 reg = <0x0 0xff0d0000 0x0 0x1000>;
393 clock-names = "pclk", "hclk", "tx_clk";
394 #address-cells = <1>;
395 #size-cells = <0>;
396 };
398 gem3: ethernet@ff0e0000 {
399 compatible = "cdns,zynqmp-gem", "cdns,gem";
400 status = "disabled";
401 interrupt-parent = <&gic>;
402 interrupts = <0 63 4>, <0 63 4>;
403 reg = <0x0 0xff0e0000 0x0 0x1000>;
404 clock-names = "pclk", "hclk", "tx_clk";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 };
409 gpio: gpio@ff0a0000 {
410 compatible = "xlnx,zynqmp-gpio-1.0";
411 status = "disabled";
412 #gpio-cells = <0x2>;
413 gpio-controller;
414 interrupt-parent = <&gic>;
415 interrupts = <0 16 4>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 reg = <0x0 0xff0a0000 0x0 0x1000>;
419 };
421 i2c0: i2c@ff020000 {
422 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
423 status = "disabled";
424 interrupt-parent = <&gic>;
425 interrupts = <0 17 4>;
426 reg = <0x0 0xff020000 0x0 0x1000>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 };
431 i2c1: i2c@ff030000 {
432 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
433 status = "disabled";
434 interrupt-parent = <&gic>;
435 interrupts = <0 18 4>;
436 reg = <0x0 0xff030000 0x0 0x1000>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 };
441 pcie: pcie@fd0e0000 {
442 compatible = "xlnx,nwl-pcie-2.11";
443 status = "disabled";
444 #address-cells = <3>;
445 #size-cells = <2>;
446 #interrupt-cells = <1>;
447 msi-controller;
448 device_type = "pci";
449 interrupt-parent = <&gic>;
450 interrupts = <0 118 4>,
451 <0 117 4>,
452 <0 116 4>,
453 <0 115 4>, /* MSI_1 [63...32] */
454 <0 114 4>; /* MSI_0 [31...0] */
455 interrupt-names = "misc", "dummy", "intx",
456 "msi1", "msi0";
457 msi-parent = <&pcie>;
458 reg = <0x0 0xfd0e0000 0x0 0x1000>,
459 <0x0 0xfd480000 0x0 0x1000>,
460 <0x80 0x00000000 0x0 0x1000000>;
461 reg-names = "breg", "pcireg", "cfg";
462 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
463 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
464 bus-range = <0x00 0xff>;
465 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
466 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
467 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
468 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
469 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
470 pcie_intc: legacy-interrupt-controller {
471 interrupt-controller;
472 #address-cells = <0>;
473 #interrupt-cells = <1>;
474 };
475 };
477 rtc: rtc@ffa60000 {
478 compatible = "xlnx,zynqmp-rtc";
479 status = "disabled";
480 reg = <0x0 0xffa60000 0x0 0x100>;
481 interrupt-parent = <&gic>;
482 interrupts = <0 26 4>, <0 27 4>;
483 interrupt-names = "alarm", "sec";
484 calibration = <0x8000>;
485 };
487 sata: ahci@fd0c0000 {
488 compatible = "ceva,ahci-1v84";
489 status = "disabled";
490 reg = <0x0 0xfd0c0000 0x0 0x2000>;
491 interrupt-parent = <&gic>;
492 interrupts = <0 133 4>;
493 };
495 sdhci0: mmc@ff160000 {
496 compatible = "arasan,sdhci-8.9a";
497 status = "disabled";
498 interrupt-parent = <&gic>;
499 interrupts = <0 48 4>;
500 reg = <0x0 0xff160000 0x0 0x1000>;
501 clock-names = "clk_xin", "clk_ahb";
502 };
504 sdhci1: mmc@ff170000 {
505 compatible = "arasan,sdhci-8.9a";
506 status = "disabled";
507 interrupt-parent = <&gic>;
508 interrupts = <0 49 4>;
509 reg = <0x0 0xff170000 0x0 0x1000>;
510 clock-names = "clk_xin", "clk_ahb";
511 };
513 smmu: smmu@fd800000 {
514 compatible = "arm,mmu-500";
515 reg = <0x0 0xfd800000 0x0 0x20000>;
516 status = "disabled";
517 #global-interrupts = <1>;
518 interrupt-parent = <&gic>;
519 interrupts = <0 155 4>,
520 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
521 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
522 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
523 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
524 };
526 spi0: spi@ff040000 {
527 compatible = "cdns,spi-r1p6";
528 status = "disabled";
529 interrupt-parent = <&gic>;
530 interrupts = <0 19 4>;
531 reg = <0x0 0xff040000 0x0 0x1000>;
532 clock-names = "ref_clk", "pclk";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 };
537 spi1: spi@ff050000 {
538 compatible = "cdns,spi-r1p6";
539 status = "disabled";
540 interrupt-parent = <&gic>;
541 interrupts = <0 20 4>;
542 reg = <0x0 0xff050000 0x0 0x1000>;
543 clock-names = "ref_clk", "pclk";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 };
548 ttc0: timer@ff110000 {
549 compatible = "cdns,ttc";
550 status = "disabled";
551 interrupt-parent = <&gic>;
552 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
553 reg = <0x0 0xff110000 0x0 0x1000>;
554 timer-width = <32>;
555 };
557 ttc1: timer@ff120000 {
558 compatible = "cdns,ttc";
559 status = "disabled";
560 interrupt-parent = <&gic>;
561 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
562 reg = <0x0 0xff120000 0x0 0x1000>;
563 timer-width = <32>;
564 };
566 ttc2: timer@ff130000 {
567 compatible = "cdns,ttc";
568 status = "disabled";
569 interrupt-parent = <&gic>;
570 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
571 reg = <0x0 0xff130000 0x0 0x1000>;
572 timer-width = <32>;
573 };
575 ttc3: timer@ff140000 {
576 compatible = "cdns,ttc";
577 status = "disabled";
578 interrupt-parent = <&gic>;
579 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
580 reg = <0x0 0xff140000 0x0 0x1000>;
581 timer-width = <32>;
582 };
584 uart0: serial@ff000000 {
585 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
586 status = "disabled";
587 interrupt-parent = <&gic>;
588 interrupts = <0 21 4>;
589 reg = <0x0 0xff000000 0x0 0x1000>;
590 clock-names = "uart_clk", "pclk";
591 };
593 uart1: serial@ff010000 {
594 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
595 status = "disabled";
596 interrupt-parent = <&gic>;
597 interrupts = <0 22 4>;
598 reg = <0x0 0xff010000 0x0 0x1000>;
599 clock-names = "uart_clk", "pclk";
600 };
602 usb0: usb@fe200000 {
603 compatible = "snps,dwc3";
604 status = "disabled";
605 interrupt-parent = <&gic>;
606 interrupts = <0 65 4>;
607 reg = <0x0 0xfe200000 0x0 0x40000>;
608 clock-names = "clk_xin", "clk_ahb";
609 };
611 usb1: usb@fe300000 {
612 compatible = "snps,dwc3";
613 status = "disabled";
614 interrupt-parent = <&gic>;
615 interrupts = <0 70 4>;
616 reg = <0x0 0xfe300000 0x0 0x40000>;
617 clock-names = "clk_xin", "clk_ahb";
618 };
620 watchdog0: watchdog@fd4d0000 {
621 compatible = "cdns,wdt-r1p2";
622 status = "disabled";
623 interrupt-parent = <&gic>;
624 interrupts = <0 113 1>;
625 reg = <0x0 0xfd4d0000 0x0 0x1000>;
626 timeout-sec = <10>;
627 };
628 };
629 };