arch/arm64/include/asm/io.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Based on arch/arm/include/asm/io.h
   4  *
   5  * Copyright (C) 1996-2000 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8 #ifndef __ASM_IO_H
   9 #define __ASM_IO_H
  10
  11 #ifdef __KERNEL__
  12
  13 #include <linux/types.h>
  14
  15 #include <asm/byteorder.h>
  16 #include <asm/barrier.h>
  17 #include <asm/memory.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/early_ioremap.h>
  20 #include <asm/alternative.h>
  21 #include <asm/cpufeature.h>
  22
  23 /*
  24  * Generic IO read/write.  These perform native-endian accesses.
  25  */
  26 #define __raw_writeb __raw_writeb
  27 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  28 {
  29         asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
  30 }
  31
  32 #define __raw_writew __raw_writew
  33 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  34 {
  35         asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
  36 }
  37
  38 #define __raw_writel __raw_writel
  39 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  40 {
  41         asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
  42 }
  43
  44 #define __raw_writeq __raw_writeq
  45 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  46 {
  47         asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
  48 }
  49
  50 #define __raw_readb __raw_readb
  51 static inline u8 __raw_readb(const volatile void __iomem *addr)
  52 {
  53         u8 val;
  54         asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
  55                                  "ldarb %w0, [%1]",
  56                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  57                      : "=r" (val) : "r" (addr));
  58         return val;
  59 }
  60
  61 #define __raw_readw __raw_readw
  62 static inline u16 __raw_readw(const volatile void __iomem *addr)
  63 {
  64         u16 val;
  65
  66         asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
  67                                  "ldarh %w0, [%1]",
  68                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  69                      : "=r" (val) : "r" (addr));
  70         return val;
  71 }
  72
  73 #define __raw_readl __raw_readl
  74 static inline u32 __raw_readl(const volatile void __iomem *addr)
  75 {
  76         u32 val;
  77         asm volatile(ALTERNATIVE("ldr %w0, [%1]",
  78                                  "ldar %w0, [%1]",
  79                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  80                      : "=r" (val) : "r" (addr));
  81         return val;
  82 }
  83
  84 #define __raw_readq __raw_readq
  85 static inline u64 __raw_readq(const volatile void __iomem *addr)
  86 {
  87         u64 val;
  88         asm volatile(ALTERNATIVE("ldr %0, [%1]",
  89                                  "ldar %0, [%1]",
  90                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  91                      : "=r" (val) : "r" (addr));
  92         return val;
  93 }
  94
  95 /* IO barriers */
  96 #define __iormb(v)                                                      \
  97 ({                                                                      \
  98         unsigned long tmp;                                              \
  99                                                                         \
 100         rmb();                                                          \
 101                                                                         \
 102         /*                                                              \
 103          * Create a dummy control dependency from the IO read to any    \
 104          * later instructions. This ensures that a subsequent call to   \
 105          * udelay() will be ordered due to the ISB in get_cycles().     \
 106          */                                                             \
 107         asm volatile("eor       %0, %1, %1\n"                           \
 108                      "cbnz      %0, ."                                  \
 109                      : "=r" (tmp) : "r" ((unsigned long)(v))            \
 110                      : "memory");                                       \
 111 })
 112
 113 #define __io_par(v)             __iormb(v)
 114 #define __iowmb()               wmb()
 115
 116 /*
 117  * Relaxed I/O memory access primitives. These follow the Device memory
 118  * ordering rules but do not guarantee any ordering relative to Normal memory
 119  * accesses.
 120  */
 121 #define readb_relaxed(c)        ({ u8  __r = __raw_readb(c); __r; })
 122 #define readw_relaxed(c)        ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
 123 #define readl_relaxed(c)        ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
 124 #define readq_relaxed(c)        ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
 125
 126 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 127 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 128 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 129 #define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 130
 131 /*
 132  * I/O memory access primitives. Reads are ordered relative to any
 133  * following Normal memory access. Writes are ordered relative to any prior
 134  * Normal memory access.
 135  */
 136 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })
 137 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
 138 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
 139 #define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
 140
 141 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 142 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 143 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
 144 #define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 145
 146 /*
 147  *  I/O port access primitives.
 148  */
 149 #define arch_has_dev_port()     (1)
 150 #define IO_SPACE_LIMIT          (PCI_IO_SIZE - 1)
 151 #define PCI_IOBASE              ((void __iomem *)PCI_IO_START)
 152
 153 /*
 154  * String version of I/O memory access operations.
 155  */
 156 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
 157 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
 158 extern void __memset_io(volatile void __iomem *, int, size_t);
 159
 160 #define memset_io(c,v,l)        __memset_io((c),(v),(l))
 161 #define memcpy_fromio(a,c,l)    __memcpy_fromio((a),(c),(l))
 162 #define memcpy_toio(c,a,l)      __memcpy_toio((c),(a),(l))
 163
 164 /*
 165  * I/O memory mapping functions.
 166  */
 167 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
 168 extern void __iounmap(volatile void __iomem *addr);
 169 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
 170
 171 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 172 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 173 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 174 #define ioremap_wt(addr, size)          __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 175 #define iounmap                         __iounmap
 176
 177 /*
 178  * PCI configuration space mapping function.
 179  *
 180  * The PCI specification disallows posted write configuration transactions.
 181  * Add an arch specific pci_remap_cfgspace() definition that is implemented
 182  * through nGnRnE device memory attribute as recommended by the ARM v8
 183  * Architecture reference manual Issue A.k B2.8.2 "Device memory".
 184  */
 185 #define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))
 186
 187 /*
 188  * io{read,write}{16,32,64}be() macros
 189  */
 190 #define ioread16be(p)           ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
 191 #define ioread32be(p)           ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
 192 #define ioread64be(p)           ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
 193
 194 #define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
 195 #define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 196 #define iowrite64be(v,p)        ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
 197
 198 #include <asm-generic/io.h>
 199
 200 /*
 201  * More restrictive address range checking than the default implementation
 202  * (PHYS_OFFSET and PHYS_MASK taken into account).
 203  */
 204 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 205 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 206 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 207
 208 extern int devmem_is_allowed(unsigned long pfn);
 209
 210 #endif  /* __KERNEL__ */
 211 #endif  /* __ASM_IO_H */