| blob | ddf9d762ac62298a9c16bdff5acf348976280247 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
7 #ifndef __ARM64_KVM_ARM_H__
8 #define __ARM64_KVM_ARM_H__
10 #include <asm/esr.h>
11 #include <asm/memory.h>
12 #include <asm/types.h>
14 /* Hyp Configuration Register (HCR) bits */
15 #define HCR_FWB (UL(1) << 46)
16 #define HCR_API (UL(1) << 41)
17 #define HCR_APK (UL(1) << 40)
18 #define HCR_TEA (UL(1) << 37)
19 #define HCR_TERR (UL(1) << 36)
20 #define HCR_TLOR (UL(1) << 35)
21 #define HCR_E2H (UL(1) << 34)
22 #define HCR_ID (UL(1) << 33)
23 #define HCR_CD (UL(1) << 32)
24 #define HCR_RW_SHIFT 31
25 #define HCR_RW (UL(1) << HCR_RW_SHIFT)
26 #define HCR_TRVM (UL(1) << 30)
27 #define HCR_HCD (UL(1) << 29)
28 #define HCR_TDZ (UL(1) << 28)
29 #define HCR_TGE (UL(1) << 27)
30 #define HCR_TVM (UL(1) << 26)
31 #define HCR_TTLB (UL(1) << 25)
32 #define HCR_TPU (UL(1) << 24)
33 #define HCR_TPC (UL(1) << 23)
34 #define HCR_TSW (UL(1) << 22)
35 #define HCR_TAC (UL(1) << 21)
36 #define HCR_TIDCP (UL(1) << 20)
37 #define HCR_TSC (UL(1) << 19)
38 #define HCR_TID3 (UL(1) << 18)
39 #define HCR_TID2 (UL(1) << 17)
40 #define HCR_TID1 (UL(1) << 16)
41 #define HCR_TID0 (UL(1) << 15)
42 #define HCR_TWE (UL(1) << 14)
43 #define HCR_TWI (UL(1) << 13)
44 #define HCR_DC (UL(1) << 12)
45 #define HCR_BSU (3 << 10)
46 #define HCR_BSU_IS (UL(1) << 10)
47 #define HCR_FB (UL(1) << 9)
48 #define HCR_VSE (UL(1) << 8)
49 #define HCR_VI (UL(1) << 7)
50 #define HCR_VF (UL(1) << 6)
51 #define HCR_AMO (UL(1) << 5)
52 #define HCR_IMO (UL(1) << 4)
53 #define HCR_FMO (UL(1) << 3)
54 #define HCR_PTW (UL(1) << 2)
55 #define HCR_SWIO (UL(1) << 1)
56 #define HCR_VM (UL(1) << 0)
58 /*
59 * The bits we set in HCR:
60 * TLOR: Trap LORegion register accesses
61 * RW: 64bit by default, can be overridden for 32bit VMs
62 * TAC: Trap ACTLR
63 * TSC: Trap SMC
64 * TVM: Trap VM ops (until M+C set in SCTLR_EL1)
65 * TSW: Trap cache operations by set/way
66 * TWE: Trap WFE
67 * TWI: Trap WFI
68 * TIDCP: Trap L2CTLR/L2ECTLR
69 * BSU_IS: Upgrade barriers to the inner shareable domain
70 * FB: Force broadcast of all maintainance operations
71 * AMO: Override CPSR.A and enable signaling with VA
72 * IMO: Override CPSR.I and enable signaling with VI
73 * FMO: Override CPSR.F and enable signaling with VF
74 * SWIO: Turn set/way invalidates into set/way clean+invalidate
75 */
76 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
77 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
78 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
79 HCR_FMO | HCR_IMO)
80 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
81 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)
82 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
84 /* TCR_EL2 Registers bits */
85 #define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
86 #define TCR_EL2_TBI (1 << 20)
87 #define TCR_EL2_PS_SHIFT 16
88 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
89 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
90 #define TCR_EL2_TG0_MASK TCR_TG0_MASK
91 #define TCR_EL2_SH0_MASK TCR_SH0_MASK
92 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
93 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
94 #define TCR_EL2_T0SZ_MASK 0x3f
95 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
96 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
98 /* VTCR_EL2 Registers bits */
99 #define VTCR_EL2_RES1 (1U << 31)
100 #define VTCR_EL2_HD (1 << 22)
101 #define VTCR_EL2_HA (1 << 21)
102 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
103 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
104 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK
105 #define VTCR_EL2_TG0_4K TCR_TG0_4K
106 #define VTCR_EL2_TG0_16K TCR_TG0_16K
107 #define VTCR_EL2_TG0_64K TCR_TG0_64K
108 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK
109 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER
110 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
111 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
112 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
113 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
114 #define VTCR_EL2_SL0_SHIFT 6
115 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
116 #define VTCR_EL2_T0SZ_MASK 0x3f
117 #define VTCR_EL2_VS_SHIFT 19
118 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
119 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
121 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
123 /*
124 * We configure the Stage-2 page tables to always restrict the IPA space to be
125 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
126 * not known to exist and will break with this configuration.
127 *
128 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
129 *
130 * Note that when using 4K pages, we concatenate two first level page tables
131 * together. With 16K pages, we concatenate 16 first level page tables.
132 *
133 */
135 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
136 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
138 /*
139 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
140 * Interestingly, it depends on the page size.
141 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
142 *
143 * -----------------------------------------
144 * | Entry level | 4K | 16K/64K |
145 * ------------------------------------------
146 * | Level: 0 | 2 | - |
147 * ------------------------------------------
148 * | Level: 1 | 1 | 2 |
149 * ------------------------------------------
150 * | Level: 2 | 0 | 1 |
151 * ------------------------------------------
152 * | Level: 3 | - | 0 |
153 * ------------------------------------------
154 *
155 * The table roughly translates to :
156 *
157 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
158 *
159 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
160 * TGRAN_SL0_BASE(4K) = 2
161 * TGRAN_SL0_BASE(16K) = 3
162 * TGRAN_SL0_BASE(64K) = 3
163 * provided we take care of ruling out the unsupported cases and
164 * Entry_Level = 4 - Number_of_levels.
165 *
166 */
167 #ifdef CONFIG_ARM64_64K_PAGES
169 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
170 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
172 #elif defined(CONFIG_ARM64_16K_PAGES)
174 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
175 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
179 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
180 #define VTCR_EL2_TGRAN_SL0_BASE 2UL
182 #endif
184 #define VTCR_EL2_LVLS_TO_SL0(levels) \
185 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
186 #define VTCR_EL2_SL0_TO_LVLS(sl0) \
187 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
188 #define VTCR_EL2_LVLS(vtcr) \
189 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
191 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
192 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
194 /*
195 * ARM VMSAv8-64 defines an algorithm for finding the translation table
196 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
197 *
198 * The algorithm defines the expectations on the translation table
199 * addresses for each level, based on PAGE_SIZE, entry level
200 * and the translation table size (T0SZ). The variable "x" in the
201 * algorithm determines the alignment of a table base address at a given
202 * level and thus determines the alignment of VTTBR:BADDR for stage2
203 * page table entry level.
204 * Since the number of bits resolved at the entry level could vary
205 * depending on the T0SZ, the value of "x" is defined based on a
206 * Magic constant for a given PAGE_SIZE and Entry Level. The
207 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
208 * x = PAGE_SHIFT).
209 *
210 * The value of "x" for entry level is calculated as :
211 * x = Magic_N - T0SZ
212 *
213 * where Magic_N is an integer depending on the page size and the entry
214 * level of the page table as below:
215 *
216 * --------------------------------------------
217 * | Entry level | 4K 16K 64K |
218 * --------------------------------------------
219 * | Level: 0 (4 levels) | 28 | - | - |
220 * --------------------------------------------
221 * | Level: 1 (3 levels) | 37 | 31 | 25 |
222 * --------------------------------------------
223 * | Level: 2 (2 levels) | 46 | 42 | 38 |
224 * --------------------------------------------
225 * | Level: 3 (1 level) | - | 53 | 51 |
226 * --------------------------------------------
227 *
228 * We have a magic formula for the Magic_N below:
229 *
230 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
231 *
232 * where Number_of_levels = (4 - Level). We are only interested in the
233 * value for Entry_Level for the stage2 page table.
234 *
235 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
236 *
237 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
238 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
239 *
240 * Here is one way to explain the Magic Formula:
241 *
242 * x = log2(Size_of_Entry_Level_Table)
243 *
244 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
245 * PAGE_SHIFT bits in the PTE, we have :
246 *
247 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
248 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
249 * where n = number of levels, and since each pointer is 8bytes, we have:
250 *
251 * x = Bits_Entry_Level + 3
252 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
253 *
254 * The only constraint here is that, we have to find the number of page table
255 * levels for a given IPA size (which we do, see stage2_pt_levels())
256 */
257 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
259 #define VTTBR_CNP_BIT (UL(1))
260 #define VTTBR_VMID_SHIFT (UL(48))
261 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
263 /* Hyp System Trap Register */
264 #define HSTR_EL2_T(x) (1 << x)
266 /* Hyp Coprocessor Trap Register Shifts */
267 #define CPTR_EL2_TFP_SHIFT 10
269 /* Hyp Coprocessor Trap Register */
270 #define CPTR_EL2_TCPAC (1 << 31)
271 #define CPTR_EL2_TTA (1 << 20)
272 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
273 #define CPTR_EL2_TZ (1 << 8)
275 #define CPTR_EL2_DEFAULT CPTR_EL2_RES1
277 /* Hyp Debug Configuration Register bits */
278 #define MDCR_EL2_TPMS (1 << 14)
279 #define MDCR_EL2_E2PB_MASK (UL(0x3))
280 #define MDCR_EL2_E2PB_SHIFT (UL(12))
281 #define MDCR_EL2_TDRA (1 << 11)
282 #define MDCR_EL2_TDOSA (1 << 10)
283 #define MDCR_EL2_TDA (1 << 9)
284 #define MDCR_EL2_TDE (1 << 8)
285 #define MDCR_EL2_HPME (1 << 7)
286 #define MDCR_EL2_TPM (1 << 6)
287 #define MDCR_EL2_TPMCR (1 << 5)
288 #define MDCR_EL2_HPMN_MASK (0x1F)
290 /* For compatibility with fault code shared with 32-bit */
291 #define FSC_FAULT ESR_ELx_FSC_FAULT
292 #define FSC_ACCESS ESR_ELx_FSC_ACCESS
293 #define FSC_PERM ESR_ELx_FSC_PERM
294 #define FSC_SEA ESR_ELx_FSC_EXTABT
295 #define FSC_SEA_TTW0 (0x14)
296 #define FSC_SEA_TTW1 (0x15)
297 #define FSC_SEA_TTW2 (0x16)
298 #define FSC_SEA_TTW3 (0x17)
299 #define FSC_SECC (0x18)
300 #define FSC_SECC_TTW0 (0x1c)
301 #define FSC_SECC_TTW1 (0x1d)
302 #define FSC_SECC_TTW2 (0x1e)
303 #define FSC_SECC_TTW3 (0x1f)
305 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
306 #define HPFAR_MASK (~UL(0xf))
307 /*
308 * We have
309 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
310 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
311 */
312 #define PAR_TO_HPFAR(par) \
313 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
315 #define ECN(x) { ESR_ELx_EC_##x, #x }
317 #define kvm_arm_exception_class \
318 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
319 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
320 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
321 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
322 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
323 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
324 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
325 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
326 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
328 #define CPACR_EL1_FPEN (3 << 20)
329 #define CPACR_EL1_TTA (1 << 28)
330 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)