arch/arm64/include/asm/pgtable-prot.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2016 ARM Ltd.
   4  */
   5 #ifndef __ASM_PGTABLE_PROT_H
   6 #define __ASM_PGTABLE_PROT_H
   7
   8 #include <asm/memory.h>
   9 #include <asm/pgtable-hwdef.h>
  10
  11 #include <linux/const.h>
  12
  13 /*
  14  * Software defined PTE bits definition.
  15  */
  16 #define PTE_WRITE               (PTE_DBM)                /* same as DBM (51) */
  17 #define PTE_DIRTY               (_AT(pteval_t, 1) << 55)
  18 #define PTE_SPECIAL             (_AT(pteval_t, 1) << 56)
  19 #define PTE_DEVMAP              (_AT(pteval_t, 1) << 57)
  20 #define PTE_PROT_NONE           (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
  21
  22 #ifndef __ASSEMBLY__
  23
  24 #include <asm/pgtable-types.h>
  25
  26 #define _PROT_DEFAULT           (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
  27 #define _PROT_SECT_DEFAULT      (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
  28
  29 #define PTE_MAYBE_NG            (arm64_kernel_use_ng_mappings() ? PTE_NG : 0)
  30 #define PMD_MAYBE_NG            (arm64_kernel_use_ng_mappings() ? PMD_SECT_NG : 0)
  31
  32 #define PROT_DEFAULT            (_PROT_DEFAULT | PTE_MAYBE_NG)
  33 #define PROT_SECT_DEFAULT       (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
  34
  35 #define PROT_DEVICE_nGnRnE      (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
  36 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
  37 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
  38 #define PROT_NORMAL_WT          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
  39 #define PROT_NORMAL             (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
  40
  41 #define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
  42 #define PROT_SECT_NORMAL        (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  43 #define PROT_SECT_NORMAL_EXEC   (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  44
  45 #define _PAGE_DEFAULT           (_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
  46 #define _HYP_PAGE_DEFAULT       _PAGE_DEFAULT
  47
  48 #define PAGE_KERNEL             __pgprot(PROT_NORMAL)
  49 #define PAGE_KERNEL_RO          __pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
  50 #define PAGE_KERNEL_ROX         __pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
  51 #define PAGE_KERNEL_EXEC        __pgprot(PROT_NORMAL & ~PTE_PXN)
  52 #define PAGE_KERNEL_EXEC_CONT   __pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
  53
  54 #define PAGE_HYP                __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN)
  55 #define PAGE_HYP_EXEC           __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY)
  56 #define PAGE_HYP_RO             __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN)
  57 #define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
  58
  59 #define PAGE_S2_MEMATTR(attr)                                           \
  60         ({                                                              \
  61                 u64 __val;                                              \
  62                 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))          \
  63                         __val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr);     \
  64                 else                                                    \
  65                         __val = PTE_S2_MEMATTR(MT_S2_ ## attr);         \
  66                 __val;                                                  \
  67          })
  68
  69 #define PAGE_S2_XN                                                      \
  70         ({                                                              \
  71                 u64 __val;                                              \
  72                 if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))           \
  73                         __val = 0;                                      \
  74                 else                                                    \
  75                         __val = PTE_S2_XN;                              \
  76                 __val;                                                  \
  77         })
  78
  79 #define PAGE_S2                 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
  80 #define PAGE_S2_DEVICE          __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
  81
  82 #define PAGE_NONE               __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
  83 #define PAGE_SHARED             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
  84 #define PAGE_SHARED_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
  85 #define PAGE_READONLY           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
  86 #define PAGE_READONLY_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
  87 #define PAGE_EXECONLY           __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
  88
  89 #define __P000  PAGE_NONE
  90 #define __P001  PAGE_READONLY
  91 #define __P010  PAGE_READONLY
  92 #define __P011  PAGE_READONLY
  93 #define __P100  PAGE_EXECONLY
  94 #define __P101  PAGE_READONLY_EXEC
  95 #define __P110  PAGE_READONLY_EXEC
  96 #define __P111  PAGE_READONLY_EXEC
  97
  98 #define __S000  PAGE_NONE
  99 #define __S001  PAGE_READONLY
 100 #define __S010  PAGE_SHARED
 101 #define __S011  PAGE_SHARED
 102 #define __S100  PAGE_EXECONLY
 103 #define __S101  PAGE_READONLY_EXEC
 104 #define __S110  PAGE_SHARED_EXEC
 105 #define __S111  PAGE_SHARED_EXEC
 106
 107 #endif /* __ASSEMBLY__ */
 108
 109 #endif /* __ASM_PGTABLE_PROT_H */