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staging: rtl8192u: remove redundant assignment to pointer crypt
[linux/fpc-iii.git] / arch / arm64 / include / asm / sysreg.h
blob06ebcfef73df965dfaa9b2bda97946218b6711d0
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14
15 /*
16 * ARMv8 ARM reserves the following encoding for system registers:
17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
18 * C5.2, version:ARM DDI 0487A.f)
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
24 */
25 #define Op0_shift 19
26 #define Op0_mask 0x3
27 #define Op1_shift 16
28 #define Op1_mask 0x7
29 #define CRn_shift 12
30 #define CRn_mask 0xf
31 #define CRm_shift 8
32 #define CRm_mask 0xf
33 #define Op2_shift 5
34 #define Op2_mask 0x7
35
36 #define sys_reg(op0, op1, crn, crm, op2) \
37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
39 ((op2) << Op2_shift))
40
41 #define sys_insn sys_reg
42
43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
48
49 #ifndef CONFIG_BROKEN_GAS_INST
50
51 #ifdef __ASSEMBLY__
52 #define __emit_inst(x) .inst (x)
53 #else
54 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
55 #endif
56
57 #else /* CONFIG_BROKEN_GAS_INST */
58
59 #ifndef CONFIG_CPU_BIG_ENDIAN
60 #define __INSTR_BSWAP(x) (x)
61 #else /* CONFIG_CPU_BIG_ENDIAN */
62 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
63 (((x) << 8) & 0x00ff0000) | \
64 (((x) >> 8) & 0x0000ff00) | \
65 (((x) >> 24) & 0x000000ff))
66 #endif /* CONFIG_CPU_BIG_ENDIAN */
67
68 #ifdef __ASSEMBLY__
69 #define __emit_inst(x) .long __INSTR_BSWAP(x)
70 #else /* __ASSEMBLY__ */
71 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
72 #endif /* __ASSEMBLY__ */
73
74 #endif /* CONFIG_BROKEN_GAS_INST */
75
76 /*
77 * Instructions for modifying PSTATE fields.
78 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
79 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
80 * for accessing PSTATE fields have the following encoding:
81 * Op0 = 0, CRn = 4
82 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
83 * CRm = Imm4 for the instruction.
84 * Rt = 0x1f
85 */
86 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
87 #define PSTATE_Imm_shift CRm_shift
88
89 #define PSTATE_PAN pstate_field(0, 4)
90 #define PSTATE_UAO pstate_field(0, 3)
91 #define PSTATE_SSBS pstate_field(3, 1)
92
93 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
94 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
95 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
96
97 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
98 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
99
100 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
101
102 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
103 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
104 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
105
106 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
107 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
108 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
109 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
110 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
111 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
112 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
113 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
114 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
115 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
116 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
117 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
118 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
119 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
120 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
121 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
122 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
123 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
124 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
125 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
126 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
127 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
128
129 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
130 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
131 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
132
133 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
134 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
135 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
136 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
137 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
138 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
139 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
140 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
141
142 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
143 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
144 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
145 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
146 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
147 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
148 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
149
150 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
151 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
152 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
153
154 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
155 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
156 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
157
158 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
159 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
160
161 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
162 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
163
164 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
165 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
166
167 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
168 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
169 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
170
171 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
172 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
173 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
174
175 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
176
177 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
178 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
179 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
180
181 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
182 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
183 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
184 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
185
186 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
187 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
188 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
189 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
190
191 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
192 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
193
194 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
195 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
196
197 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
198
199 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
200 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
201 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
202
203 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
204 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
205 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
206 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
207 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
208 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
209 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
210 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
211
212 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
213 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
214
215 /*** Statistical Profiling Extension ***/
216 /* ID registers */
217 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
218 #define SYS_PMSIDR_EL1_FE_SHIFT 0
219 #define SYS_PMSIDR_EL1_FT_SHIFT 1
220 #define SYS_PMSIDR_EL1_FL_SHIFT 2
221 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
222 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
223 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
224 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
225 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
226 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
227 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
228 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
229 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
230
231 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
232 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
233 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
234 #define SYS_PMBIDR_EL1_P_SHIFT 4
235 #define SYS_PMBIDR_EL1_F_SHIFT 5
236
237 /* Sampling controls */
238 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
239 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
240 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
241 #define SYS_PMSCR_EL1_CX_SHIFT 3
242 #define SYS_PMSCR_EL1_PA_SHIFT 4
243 #define SYS_PMSCR_EL1_TS_SHIFT 5
244 #define SYS_PMSCR_EL1_PCT_SHIFT 6
245
246 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
247 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
248 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
249 #define SYS_PMSCR_EL2_CX_SHIFT 3
250 #define SYS_PMSCR_EL2_PA_SHIFT 4
251 #define SYS_PMSCR_EL2_TS_SHIFT 5
252 #define SYS_PMSCR_EL2_PCT_SHIFT 6
253
254 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
255
256 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
257 #define SYS_PMSIRR_EL1_RND_SHIFT 0
258 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
259 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
260
261 /* Filtering controls */
262 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
263 #define SYS_PMSFCR_EL1_FE_SHIFT 0
264 #define SYS_PMSFCR_EL1_FT_SHIFT 1
265 #define SYS_PMSFCR_EL1_FL_SHIFT 2
266 #define SYS_PMSFCR_EL1_B_SHIFT 16
267 #define SYS_PMSFCR_EL1_LD_SHIFT 17
268 #define SYS_PMSFCR_EL1_ST_SHIFT 18
269
270 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
271 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
272
273 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
274 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
275
276 /* Buffer controls */
277 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
278 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
279 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
280 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
281 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
282
283 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
284
285 /* Buffer error reporting */
286 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
287 #define SYS_PMBSR_EL1_COLL_SHIFT 16
288 #define SYS_PMBSR_EL1_S_SHIFT 17
289 #define SYS_PMBSR_EL1_EA_SHIFT 18
290 #define SYS_PMBSR_EL1_DL_SHIFT 19
291 #define SYS_PMBSR_EL1_EC_SHIFT 26
292 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
293
294 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
295 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
296 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
297
298 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
299 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
300
301 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
302 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
303
304 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
305
306 /*** End of Statistical Profiling Extension ***/
307
308 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
309 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
310
311 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
312 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
313
314 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
315 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
316 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
317 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
318 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
319
320 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
321 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
322
323 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
324 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
325 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
326 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
327 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
328 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
329 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
330 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
331 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
332 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
333 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
334 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
335 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
336 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
337 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
338 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
339 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
340 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
341 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
342 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
343 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
344 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
345 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
346 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
347 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
348 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
349 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
350
351 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
352 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
353
354 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
355
356 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
357 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
358 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
359
360 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
361
362 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
363 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
364
365 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
366 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
367 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
368 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
369 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
370 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
371 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
372 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
373 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
374 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
375 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
376 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
377 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
378
379 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
380 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
381
382 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
383
384 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
385 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
386 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
387
388 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
389 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
390
391 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
392 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
393 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
394
395 #define __PMEV_op2(n) ((n) & 0x7)
396 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
397 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
398 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
399 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
400
401 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
402
403 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
404 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
405 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
406 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
407 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
408 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
409 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
410 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
411 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
412
413 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
414 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
415 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
416 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
417 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
418 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
419
420 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
421 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
422 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
423 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
424 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
425
426 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
427 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
428 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
429 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
430 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
431 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
432 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
433 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
434
435 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
436 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
437 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
438 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
439 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
440 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
441 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
442 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
443 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
444
445 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
446 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
447 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
448 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
449 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
450 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
451 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
452 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
453 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
454
455 /* VHE encodings for architectural EL0/1 system registers */
456 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
457 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
458 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
459 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
460 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
461 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
462 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
463 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
464 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
465 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
466 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
467 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
468 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
469 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
470 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
471 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
472 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
473 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
474 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
475 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
476 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
477 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
478 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
479
480 /* Common SCTLR_ELx flags. */
481 #define SCTLR_ELx_DSSBS (BIT(44))
482 #define SCTLR_ELx_ENIA (BIT(31))
483 #define SCTLR_ELx_ENIB (BIT(30))
484 #define SCTLR_ELx_ENDA (BIT(27))
485 #define SCTLR_ELx_EE (BIT(25))
486 #define SCTLR_ELx_IESB (BIT(21))
487 #define SCTLR_ELx_WXN (BIT(19))
488 #define SCTLR_ELx_ENDB (BIT(13))
489 #define SCTLR_ELx_I (BIT(12))
490 #define SCTLR_ELx_SA (BIT(3))
491 #define SCTLR_ELx_C (BIT(2))
492 #define SCTLR_ELx_A (BIT(1))
493 #define SCTLR_ELx_M (BIT(0))
494
495 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
496 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
497
498 /* SCTLR_EL2 specific flags. */
499 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
500 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
501 (BIT(29)))
502 #define SCTLR_EL2_RES0 ((BIT(6)) | (BIT(7)) | (BIT(8)) | (BIT(9)) | \
503 (BIT(10)) | (BIT(13)) | (BIT(14)) | (BIT(15)) | \
504 (BIT(17)) | (BIT(20)) | (BIT(24)) | (BIT(26)) | \
505 (BIT(27)) | (BIT(30)) | (BIT(31)) | \
506 (0xffffefffUL << 32))
507
508 #ifdef CONFIG_CPU_BIG_ENDIAN
509 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
510 #define ENDIAN_CLEAR_EL2 0
511 #else
512 #define ENDIAN_SET_EL2 0
513 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
514 #endif
515
516 /* SCTLR_EL2 value used for the hyp-stub */
517 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
518 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
519 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
520 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
521
522 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL
523 #error "Inconsistent SCTLR_EL2 set/clear bits"
524 #endif
525
526 /* SCTLR_EL1 specific flags. */
527 #define SCTLR_EL1_UCI (BIT(26))
528 #define SCTLR_EL1_E0E (BIT(24))
529 #define SCTLR_EL1_SPAN (BIT(23))
530 #define SCTLR_EL1_NTWE (BIT(18))
531 #define SCTLR_EL1_NTWI (BIT(16))
532 #define SCTLR_EL1_UCT (BIT(15))
533 #define SCTLR_EL1_DZE (BIT(14))
534 #define SCTLR_EL1_UMA (BIT(9))
535 #define SCTLR_EL1_SED (BIT(8))
536 #define SCTLR_EL1_ITD (BIT(7))
537 #define SCTLR_EL1_CP15BEN (BIT(5))
538 #define SCTLR_EL1_SA0 (BIT(4))
539
540 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
541 (BIT(29)))
542 #define SCTLR_EL1_RES0 ((BIT(6)) | (BIT(10)) | (BIT(13)) | (BIT(17)) | \
543 (BIT(27)) | (BIT(30)) | (BIT(31)) | \
544 (0xffffefffUL << 32))
545
546 #ifdef CONFIG_CPU_BIG_ENDIAN
547 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
548 #define ENDIAN_CLEAR_EL1 0
549 #else
550 #define ENDIAN_SET_EL1 0
551 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
552 #endif
553
554 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
555 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
556 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\
557 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
558 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
559 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
560 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
561 SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0)
562
563 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL
564 #error "Inconsistent SCTLR_EL1 set/clear bits"
565 #endif
566
567 /* id_aa64isar0 */
568 #define ID_AA64ISAR0_TS_SHIFT 52
569 #define ID_AA64ISAR0_FHM_SHIFT 48
570 #define ID_AA64ISAR0_DP_SHIFT 44
571 #define ID_AA64ISAR0_SM4_SHIFT 40
572 #define ID_AA64ISAR0_SM3_SHIFT 36
573 #define ID_AA64ISAR0_SHA3_SHIFT 32
574 #define ID_AA64ISAR0_RDM_SHIFT 28
575 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
576 #define ID_AA64ISAR0_CRC32_SHIFT 16
577 #define ID_AA64ISAR0_SHA2_SHIFT 12
578 #define ID_AA64ISAR0_SHA1_SHIFT 8
579 #define ID_AA64ISAR0_AES_SHIFT 4
580
581 /* id_aa64isar1 */
582 #define ID_AA64ISAR1_SB_SHIFT 36
583 #define ID_AA64ISAR1_FRINTTS_SHIFT 32
584 #define ID_AA64ISAR1_GPI_SHIFT 28
585 #define ID_AA64ISAR1_GPA_SHIFT 24
586 #define ID_AA64ISAR1_LRCPC_SHIFT 20
587 #define ID_AA64ISAR1_FCMA_SHIFT 16
588 #define ID_AA64ISAR1_JSCVT_SHIFT 12
589 #define ID_AA64ISAR1_API_SHIFT 8
590 #define ID_AA64ISAR1_APA_SHIFT 4
591 #define ID_AA64ISAR1_DPB_SHIFT 0
592
593 #define ID_AA64ISAR1_APA_NI 0x0
594 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1
595 #define ID_AA64ISAR1_API_NI 0x0
596 #define ID_AA64ISAR1_API_IMP_DEF 0x1
597 #define ID_AA64ISAR1_GPA_NI 0x0
598 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
599 #define ID_AA64ISAR1_GPI_NI 0x0
600 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
601
602 /* id_aa64pfr0 */
603 #define ID_AA64PFR0_CSV3_SHIFT 60
604 #define ID_AA64PFR0_CSV2_SHIFT 56
605 #define ID_AA64PFR0_DIT_SHIFT 48
606 #define ID_AA64PFR0_SVE_SHIFT 32
607 #define ID_AA64PFR0_RAS_SHIFT 28
608 #define ID_AA64PFR0_GIC_SHIFT 24
609 #define ID_AA64PFR0_ASIMD_SHIFT 20
610 #define ID_AA64PFR0_FP_SHIFT 16
611 #define ID_AA64PFR0_EL3_SHIFT 12
612 #define ID_AA64PFR0_EL2_SHIFT 8
613 #define ID_AA64PFR0_EL1_SHIFT 4
614 #define ID_AA64PFR0_EL0_SHIFT 0
615
616 #define ID_AA64PFR0_SVE 0x1
617 #define ID_AA64PFR0_RAS_V1 0x1
618 #define ID_AA64PFR0_FP_NI 0xf
619 #define ID_AA64PFR0_FP_SUPPORTED 0x0
620 #define ID_AA64PFR0_ASIMD_NI 0xf
621 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
622 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
623 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
624 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
625
626 /* id_aa64pfr1 */
627 #define ID_AA64PFR1_SSBS_SHIFT 4
628
629 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
630 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
631 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
632
633 /* id_aa64zfr0 */
634 #define ID_AA64ZFR0_SM4_SHIFT 40
635 #define ID_AA64ZFR0_SHA3_SHIFT 32
636 #define ID_AA64ZFR0_BITPERM_SHIFT 16
637 #define ID_AA64ZFR0_AES_SHIFT 4
638 #define ID_AA64ZFR0_SVEVER_SHIFT 0
639
640 #define ID_AA64ZFR0_SM4 0x1
641 #define ID_AA64ZFR0_SHA3 0x1
642 #define ID_AA64ZFR0_BITPERM 0x1
643 #define ID_AA64ZFR0_AES 0x1
644 #define ID_AA64ZFR0_AES_PMULL 0x2
645 #define ID_AA64ZFR0_SVEVER_SVE2 0x1
646
647 /* id_aa64mmfr0 */
648 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
649 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
650 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
651 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
652 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
653 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
654 #define ID_AA64MMFR0_ASID_SHIFT 4
655 #define ID_AA64MMFR0_PARANGE_SHIFT 0
656
657 #define ID_AA64MMFR0_TGRAN4_NI 0xf
658 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
659 #define ID_AA64MMFR0_TGRAN64_NI 0xf
660 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
661 #define ID_AA64MMFR0_TGRAN16_NI 0x0
662 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
663 #define ID_AA64MMFR0_PARANGE_48 0x5
664 #define ID_AA64MMFR0_PARANGE_52 0x6
665
666 #ifdef CONFIG_ARM64_PA_BITS_52
667 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
668 #else
669 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
670 #endif
671
672 /* id_aa64mmfr1 */
673 #define ID_AA64MMFR1_PAN_SHIFT 20
674 #define ID_AA64MMFR1_LOR_SHIFT 16
675 #define ID_AA64MMFR1_HPD_SHIFT 12
676 #define ID_AA64MMFR1_VHE_SHIFT 8
677 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
678 #define ID_AA64MMFR1_HADBS_SHIFT 0
679
680 #define ID_AA64MMFR1_VMIDBITS_8 0
681 #define ID_AA64MMFR1_VMIDBITS_16 2
682
683 /* id_aa64mmfr2 */
684 #define ID_AA64MMFR2_FWB_SHIFT 40
685 #define ID_AA64MMFR2_AT_SHIFT 32
686 #define ID_AA64MMFR2_LVA_SHIFT 16
687 #define ID_AA64MMFR2_IESB_SHIFT 12
688 #define ID_AA64MMFR2_LSM_SHIFT 8
689 #define ID_AA64MMFR2_UAO_SHIFT 4
690 #define ID_AA64MMFR2_CNP_SHIFT 0
691
692 /* id_aa64dfr0 */
693 #define ID_AA64DFR0_PMSVER_SHIFT 32
694 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
695 #define ID_AA64DFR0_WRPS_SHIFT 20
696 #define ID_AA64DFR0_BRPS_SHIFT 12
697 #define ID_AA64DFR0_PMUVER_SHIFT 8
698 #define ID_AA64DFR0_TRACEVER_SHIFT 4
699 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
700
701 #define ID_ISAR5_RDM_SHIFT 24
702 #define ID_ISAR5_CRC32_SHIFT 16
703 #define ID_ISAR5_SHA2_SHIFT 12
704 #define ID_ISAR5_SHA1_SHIFT 8
705 #define ID_ISAR5_AES_SHIFT 4
706 #define ID_ISAR5_SEVL_SHIFT 0
707
708 #define MVFR0_FPROUND_SHIFT 28
709 #define MVFR0_FPSHVEC_SHIFT 24
710 #define MVFR0_FPSQRT_SHIFT 20
711 #define MVFR0_FPDIVIDE_SHIFT 16
712 #define MVFR0_FPTRAP_SHIFT 12
713 #define MVFR0_FPDP_SHIFT 8
714 #define MVFR0_FPSP_SHIFT 4
715 #define MVFR0_SIMD_SHIFT 0
716
717 #define MVFR1_SIMDFMAC_SHIFT 28
718 #define MVFR1_FPHP_SHIFT 24
719 #define MVFR1_SIMDHP_SHIFT 20
720 #define MVFR1_SIMDSP_SHIFT 16
721 #define MVFR1_SIMDINT_SHIFT 12
722 #define MVFR1_SIMDLS_SHIFT 8
723 #define MVFR1_FPDNAN_SHIFT 4
724 #define MVFR1_FPFTZ_SHIFT 0
725
726
727 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
728 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
729 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
730
731 #define ID_AA64MMFR0_TGRAN4_NI 0xf
732 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
733 #define ID_AA64MMFR0_TGRAN64_NI 0xf
734 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
735 #define ID_AA64MMFR0_TGRAN16_NI 0x0
736 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
737
738 #if defined(CONFIG_ARM64_4K_PAGES)
739 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
740 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
741 #elif defined(CONFIG_ARM64_16K_PAGES)
742 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
743 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
744 #elif defined(CONFIG_ARM64_64K_PAGES)
745 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
746 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
747 #endif
748
749
750 /*
751 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
752 * are reserved by the SVE architecture for future expansion of the LEN
753 * field, with compatible semantics.
754 */
755 #define ZCR_ELx_LEN_SHIFT 0
756 #define ZCR_ELx_LEN_SIZE 9
757 #define ZCR_ELx_LEN_MASK 0x1ff
758
759 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
760 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
761 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
762
763
764 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
765 #define SYS_MPIDR_SAFE_VAL (BIT(31))
766
767 #ifdef __ASSEMBLY__
768
769 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
770 .equ .L__reg_num_x\num, \num
771 .endr
772 .equ .L__reg_num_xzr, 31
773
774 .macro mrs_s, rt, sreg
775 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
776 .endm
777
778 .macro msr_s, sreg, rt
779 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
780 .endm
781
782 #else
783
784 #include <linux/build_bug.h>
785 #include <linux/types.h>
786
787 #define __DEFINE_MRS_MSR_S_REGNUM \
788 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
789 " .equ .L__reg_num_x\\num, \\num\n" \
790 " .endr\n" \
791 " .equ .L__reg_num_xzr, 31\n"
792
793 #define DEFINE_MRS_S \
794 __DEFINE_MRS_MSR_S_REGNUM \
795 " .macro mrs_s, rt, sreg\n" \
796 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \
797 " .endm\n"
798
799 #define DEFINE_MSR_S \
800 __DEFINE_MRS_MSR_S_REGNUM \
801 " .macro msr_s, sreg, rt\n" \
802 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \
803 " .endm\n"
804
805 #define UNDEFINE_MRS_S \
806 " .purgem mrs_s\n"
807
808 #define UNDEFINE_MSR_S \
809 " .purgem msr_s\n"
810
811 #define __mrs_s(v, r) \
812 DEFINE_MRS_S \
813 " mrs_s " v ", " __stringify(r) "\n" \
814 UNDEFINE_MRS_S
815
816 #define __msr_s(r, v) \
817 DEFINE_MSR_S \
818 " msr_s " __stringify(r) ", " v "\n" \
819 UNDEFINE_MSR_S
820
821 /*
822 * Unlike read_cpuid, calls to read_sysreg are never expected to be
823 * optimized away or replaced with synthetic values.
824 */
825 #define read_sysreg(r) ({ \
826 u64 __val; \
827 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
828 __val; \
829 })
830
831 /*
832 * The "Z" constraint normally means a zero immediate, but when combined with
833 * the "%x0" template means XZR.
834 */
835 #define write_sysreg(v, r) do { \
836 u64 __val = (u64)(v); \
837 asm volatile("msr " __stringify(r) ", %x0" \
838 : : "rZ" (__val)); \
839 } while (0)
840
841 /*
842 * For registers without architectural names, or simply unsupported by
843 * GAS.
844 */
845 #define read_sysreg_s(r) ({ \
846 u64 __val; \
847 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
848 __val; \
849 })
850
851 #define write_sysreg_s(v, r) do { \
852 u64 __val = (u64)(v); \
853 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
854 } while (0)
855
856 /*
857 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
858 * set mask are set. Other bits are left as-is.
859 */
860 #define sysreg_clear_set(sysreg, clear, set) do { \
861 u64 __scs_val = read_sysreg(sysreg); \
862 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
863 if (__scs_new != __scs_val) \
864 write_sysreg(__scs_new, sysreg); \
865 } while (0)
866
867 #endif
868
869 #endif /* __ASM_SYSREG_H */
Linux with added FPC-III support