arch/arm64/include/uapi/asm/sigcontext.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #ifndef _UAPI__ASM_SIGCONTEXT_H
  18 #define _UAPI__ASM_SIGCONTEXT_H
  19
  20 #ifndef __ASSEMBLY__
  21
  22 #include <linux/types.h>
  23
  24 /*
  25  * Signal context structure - contains all info to do with the state
  26  * before the signal handler was invoked.
  27  */
  28 struct sigcontext {
  29         __u64 fault_address;
  30         /* AArch64 registers */
  31         __u64 regs[31];
  32         __u64 sp;
  33         __u64 pc;
  34         __u64 pstate;
  35         /* 4K reserved for FP/SIMD state and future expansion */
  36         __u8 __reserved[4096] __attribute__((__aligned__(16)));
  37 };
  38
  39 /*
  40  * Allocation of __reserved[]:
  41  * (Note: records do not necessarily occur in the order shown here.)
  42  *
  43  *      size            description
  44  *
  45  *      0x210           fpsimd_context
  46  *       0x10           esr_context
  47  *      0x8a0           sve_context (vl <= 64) (optional)
  48  *       0x20           extra_context (optional)
  49  *       0x10           terminator (null _aarch64_ctx)
  50  *
  51  *      0x510           (reserved for future allocation)
  52  *
  53  * New records that can exceed this space need to be opt-in for userspace, so
  54  * that an expanded signal frame is not generated unexpectedly.  The mechanism
  55  * for opting in will depend on the extension that generates each new record.
  56  * The above table documents the maximum set and sizes of records than can be
  57  * generated when userspace does not opt in for any such extension.
  58  */
  59
  60 /*
  61  * Header to be used at the beginning of structures extending the user
  62  * context. Such structures must be placed after the rt_sigframe on the stack
  63  * and be 16-byte aligned. The last structure must be a dummy one with the
  64  * magic and size set to 0.
  65  */
  66 struct _aarch64_ctx {
  67         __u32 magic;
  68         __u32 size;
  69 };
  70
  71 #define FPSIMD_MAGIC    0x46508001
  72
  73 struct fpsimd_context {
  74         struct _aarch64_ctx head;
  75         __u32 fpsr;
  76         __u32 fpcr;
  77         __uint128_t vregs[32];
  78 };
  79
  80 /*
  81  * Note: similarly to all other integer fields, each V-register is stored in an
  82  * endianness-dependent format, with the byte at offset i from the start of the
  83  * in-memory representation of the register value containing
  84  *
  85  *    bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
  86  *    bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
  87  */
  88
  89 /* ESR_EL1 context */
  90 #define ESR_MAGIC       0x45535201
  91
  92 struct esr_context {
  93         struct _aarch64_ctx head;
  94         __u64 esr;
  95 };
  96
  97 /*
  98  * extra_context: describes extra space in the signal frame for
  99  * additional structures that don't fit in sigcontext.__reserved[].
 100  *
 101  * Note:
 102  *
 103  * 1) fpsimd_context, esr_context and extra_context must be placed in
 104  * sigcontext.__reserved[] if present.  They cannot be placed in the
 105  * extra space.  Any other record can be placed either in the extra
 106  * space or in sigcontext.__reserved[], unless otherwise specified in
 107  * this file.
 108  *
 109  * 2) There must not be more than one extra_context.
 110  *
 111  * 3) If extra_context is present, it must be followed immediately in
 112  * sigcontext.__reserved[] by the terminating null _aarch64_ctx.
 113  *
 114  * 4) The extra space to which datap points must start at the first
 115  * 16-byte aligned address immediately after the terminating null
 116  * _aarch64_ctx that follows the extra_context structure in
 117  * __reserved[].  The extra space may overrun the end of __reserved[],
 118  * as indicated by a sufficiently large value for the size field.
 119  *
 120  * 5) The extra space must itself be terminated with a null
 121  * _aarch64_ctx.
 122  */
 123 #define EXTRA_MAGIC     0x45585401
 124
 125 struct extra_context {
 126         struct _aarch64_ctx head;
 127         __u64 datap; /* 16-byte aligned pointer to extra space cast to __u64 */
 128         __u32 size; /* size in bytes of the extra space */
 129         __u32 __reserved[3];
 130 };
 131
 132 #define SVE_MAGIC       0x53564501
 133
 134 struct sve_context {
 135         struct _aarch64_ctx head;
 136         __u16 vl;
 137         __u16 __reserved[3];
 138 };
 139
 140 #endif /* !__ASSEMBLY__ */
 141
 142 #include <asm/sve_context.h>
 143
 144 /*
 145  * The SVE architecture leaves space for future expansion of the
 146  * vector length beyond its initial architectural limit of 2048 bits
 147  * (16 quadwords).
 148  *
 149  * See linux/Documentation/arm64/sve.rst for a description of the VL/VQ
 150  * terminology.
 151  */
 152 #define SVE_VQ_BYTES            __SVE_VQ_BYTES  /* bytes per quadword */
 153
 154 #define SVE_VQ_MIN              __SVE_VQ_MIN
 155 #define SVE_VQ_MAX              __SVE_VQ_MAX
 156
 157 #define SVE_VL_MIN              __SVE_VL_MIN
 158 #define SVE_VL_MAX              __SVE_VL_MAX
 159
 160 #define SVE_NUM_ZREGS           __SVE_NUM_ZREGS
 161 #define SVE_NUM_PREGS           __SVE_NUM_PREGS
 162
 163 #define sve_vl_valid(vl)        __sve_vl_valid(vl)
 164 #define sve_vq_from_vl(vl)      __sve_vq_from_vl(vl)
 165 #define sve_vl_from_vq(vq)      __sve_vl_from_vq(vq)
 166
 167 /*
 168  * If the SVE registers are currently live for the thread at signal delivery,
 169  * sve_context.head.size >=
 170  *      SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl))
 171  * and the register data may be accessed using the SVE_SIG_*() macros.
 172  *
 173  * If sve_context.head.size <
 174  *      SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)),
 175  * the SVE registers were not live for the thread and no register data
 176  * is included: in this case, the SVE_SIG_*() macros should not be
 177  * used except for this check.
 178  *
 179  * The same convention applies when returning from a signal: a caller
 180  * will need to remove or resize the sve_context block if it wants to
 181  * make the SVE registers live when they were previously non-live or
 182  * vice-versa.  This may require the the caller to allocate fresh
 183  * memory and/or move other context blocks in the signal frame.
 184  *
 185  * Changing the vector length during signal return is not permitted:
 186  * sve_context.vl must equal the thread's current vector length when
 187  * doing a sigreturn.
 188  *
 189  *
 190  * Note: for all these macros, the "vq" argument denotes the SVE
 191  * vector length in quadwords (i.e., units of 128 bits).
 192  *
 193  * The correct way to obtain vq is to use sve_vq_from_vl(vl).  The
 194  * result is valid if and only if sve_vl_valid(vl) is true.  This is
 195  * guaranteed for a struct sve_context written by the kernel.
 196  *
 197  *
 198  * Additional macros describe the contents and layout of the payload.
 199  * For each, SVE_SIG_x_OFFSET(args) is the start offset relative to
 200  * the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the
 201  * size in bytes:
 202  *
 203  *      x       type                            description
 204  *      -       ----                            -----------
 205  *      REGS                                    the entire SVE context
 206  *
 207  *      ZREGS   __uint128_t[SVE_NUM_ZREGS][vq]  all Z-registers
 208  *      ZREG    __uint128_t[vq]                 individual Z-register Zn
 209  *
 210  *      PREGS   uint16_t[SVE_NUM_PREGS][vq]     all P-registers
 211  *      PREG    uint16_t[vq]                    individual P-register Pn
 212  *
 213  *      FFR     uint16_t[vq]                    first-fault status register
 214  *
 215  * Additional data might be appended in the future.
 216  *
 217  * Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
 218  * is encoded in memory in an endianness-invariant format, with the byte at
 219  * offset i from the start of the in-memory representation containing bits
 220  * [(7 + 8 * i) : (8 * i)] of the register value.
 221  */
 222
 223 #define SVE_SIG_ZREG_SIZE(vq)   __SVE_ZREG_SIZE(vq)
 224 #define SVE_SIG_PREG_SIZE(vq)   __SVE_PREG_SIZE(vq)
 225 #define SVE_SIG_FFR_SIZE(vq)    __SVE_FFR_SIZE(vq)
 226
 227 #define SVE_SIG_REGS_OFFSET                                     \
 228         ((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1))    \
 229                 / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
 230
 231 #define SVE_SIG_ZREGS_OFFSET \
 232                 (SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
 233 #define SVE_SIG_ZREG_OFFSET(vq, n) \
 234                 (SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
 235 #define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
 236
 237 #define SVE_SIG_PREGS_OFFSET(vq) \
 238                 (SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
 239 #define SVE_SIG_PREG_OFFSET(vq, n) \
 240                 (SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
 241 #define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
 242
 243 #define SVE_SIG_FFR_OFFSET(vq) \
 244                 (SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
 245
 246 #define SVE_SIG_REGS_SIZE(vq) \
 247                 (__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
 248
 249 #define SVE_SIG_CONTEXT_SIZE(vq) \
 250                 (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
 251
 252 #endif /* _UAPI__ASM_SIGCONTEXT_H */