| blob | 2cdacd1c141b97295192e9685ffca9ef32765939 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Low-level CPU initialisation
4 * Based on arch/arm/kernel/head.S
5 *
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
8 * Authors: Catalin Marinas <catalin.marinas@arm.com>
9 * Will Deacon <will.deacon@arm.com>
10 */
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/irqchip/arm-gic-v3.h>
16 #include <asm/assembler.h>
17 #include <asm/boot.h>
18 #include <asm/ptrace.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cache.h>
21 #include <asm/cputype.h>
22 #include <asm/elf.h>
23 #include <asm/image.h>
24 #include <asm/kernel-pgtable.h>
25 #include <asm/kvm_arm.h>
26 #include <asm/memory.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/pgtable.h>
29 #include <asm/page.h>
30 #include <asm/smp.h>
31 #include <asm/sysreg.h>
32 #include <asm/thread_info.h>
33 #include <asm/virt.h>
35 #include "efi-header.S"
37 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
39 #if (TEXT_OFFSET & 0xfff) != 0
40 #error TEXT_OFFSET must be at least 4KB aligned
41 #elif (PAGE_OFFSET & 0x1fffff) != 0
42 #error PAGE_OFFSET must be at least 2MB aligned
43 #elif TEXT_OFFSET > 0x1fffff
44 #error TEXT_OFFSET must be less than 2MB
45 #endif
47 /*
48 * Kernel startup entry point.
49 * ---------------------------
50 *
51 * The requirements are:
52 * MMU = off, D-cache = off, I-cache = on or off,
53 * x0 = physical address to the FDT blob.
54 *
55 * This code is mostly position independent so you call this at
56 * __pa(PAGE_OFFSET + TEXT_OFFSET).
57 *
58 * Note that the callee-saved registers are used for storing variables
59 * that are useful before the MMU is enabled. The allocations are described
60 * in the entry routines.
61 */
62 __HEAD
63 _head:
64 /*
65 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
66 */
67 #ifdef CONFIG_EFI
68 /*
69 * This add instruction has no meaningful effect except that
70 * its opcode forms the magic "MZ" signature required by UEFI.
71 */
72 add x13, x18, #0x16
73 b stext
74 #else
75 b stext // branch to kernel start, magic
76 .long 0 // reserved
77 #endif
78 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
79 le64sym _kernel_size_le // Effective size of kernel image, little-endian
80 le64sym _kernel_flags_le // Informative flags, little-endian
81 .quad 0 // reserved
82 .quad 0 // reserved
83 .quad 0 // reserved
84 .ascii ARM64_IMAGE_MAGIC // Magic number
85 #ifdef CONFIG_EFI
86 .long pe_header - _head // Offset to the PE header.
88 pe_header:
89 __EFI_PE_HEADER
90 #else
91 .long 0 // reserved
92 #endif
94 __INIT
96 /*
97 * The following callee saved general purpose registers are used on the
98 * primary lowlevel boot path:
99 *
100 * Register Scope Purpose
101 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
102 * x23 stext() .. start_kernel() physical misalignment/KASLR offset
103 * x28 __create_page_tables() callee preserved temp register
104 * x19/x20 __primary_switch() callee preserved temp registers
105 */
106 ENTRY(stext)
107 bl preserve_boot_args
108 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
109 adrp x23, __PHYS_OFFSET
110 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
111 bl set_cpu_boot_mode_flag
112 bl __create_page_tables
113 /*
114 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
115 * details.
116 * On return, the CPU will be ready for the MMU to be turned on and
117 * the TCR will have been set.
118 */
119 bl __cpu_setup // initialise processor
120 b __primary_switch
121 ENDPROC(stext)
123 /*
124 * Preserve the arguments passed by the bootloader in x0 .. x3
125 */
126 preserve_boot_args:
127 mov x21, x0 // x21=FDT
129 adr_l x0, boot_args // record the contents of
130 stp x21, x1, [x0] // x0 .. x3 at kernel entry
131 stp x2, x3, [x0, #16]
133 dmb sy // needed before dc ivac with
134 // MMU off
136 mov x1, #0x20 // 4 x 8 bytes
137 b __inval_dcache_area // tail call
138 ENDPROC(preserve_boot_args)
140 /*
141 * Macro to create a table entry to the next page.
142 *
143 * tbl: page table address
144 * virt: virtual address
145 * shift: #imm page table shift
146 * ptrs: #imm pointers per table page
147 *
148 * Preserves: virt
149 * Corrupts: ptrs, tmp1, tmp2
150 * Returns: tbl -> next level table page address
151 */
152 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
153 add \tmp1, \tbl, #PAGE_SIZE
154 phys_to_pte \tmp2, \tmp1
155 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
156 lsr \tmp1, \virt, #\shift
157 sub \ptrs, \ptrs, #1
158 and \tmp1, \tmp1, \ptrs // table index
159 str \tmp2, [\tbl, \tmp1, lsl #3]
160 add \tbl, \tbl, #PAGE_SIZE // next level table page
161 .endm
163 /*
164 * Macro to populate page table entries, these entries can be pointers to the next level
165 * or last level entries pointing to physical memory.
166 *
167 * tbl: page table address
168 * rtbl: pointer to page table or physical memory
169 * index: start index to write
170 * eindex: end index to write - [index, eindex] written to
171 * flags: flags for pagetable entry to or in
172 * inc: increment to rtbl between each entry
173 * tmp1: temporary variable
174 *
175 * Preserves: tbl, eindex, flags, inc
176 * Corrupts: index, tmp1
177 * Returns: rtbl
178 */
179 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
180 .Lpe\@: phys_to_pte \tmp1, \rtbl
181 orr \tmp1, \tmp1, \flags // tmp1 = table entry
182 str \tmp1, [\tbl, \index, lsl #3]
183 add \rtbl, \rtbl, \inc // rtbl = pa next level
184 add \index, \index, #1
185 cmp \index, \eindex
186 b.ls .Lpe\@
187 .endm
189 /*
190 * Compute indices of table entries from virtual address range. If multiple entries
191 * were needed in the previous page table level then the next page table level is assumed
192 * to be composed of multiple pages. (This effectively scales the end index).
193 *
194 * vstart: virtual address of start of range
195 * vend: virtual address of end of range
196 * shift: shift used to transform virtual address into index
197 * ptrs: number of entries in page table
198 * istart: index in table corresponding to vstart
199 * iend: index in table corresponding to vend
200 * count: On entry: how many extra entries were required in previous level, scales
201 * our end index.
202 * On exit: returns how many extra entries required for next page table level
203 *
204 * Preserves: vstart, vend, shift, ptrs
205 * Returns: istart, iend, count
206 */
207 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
208 lsr \iend, \vend, \shift
209 mov \istart, \ptrs
210 sub \istart, \istart, #1
211 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
212 mov \istart, \ptrs
213 mul \istart, \istart, \count
214 add \iend, \iend, \istart // iend += (count - 1) * ptrs
215 // our entries span multiple tables
217 lsr \istart, \vstart, \shift
218 mov \count, \ptrs
219 sub \count, \count, #1
220 and \istart, \istart, \count
222 sub \count, \iend, \istart
223 .endm
225 /*
226 * Map memory for specified virtual address range. Each level of page table needed supports
227 * multiple entries. If a level requires n entries the next page table level is assumed to be
228 * formed from n pages.
229 *
230 * tbl: location of page table
231 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
232 * vstart: start address to map
233 * vend: end address to map - we map [vstart, vend]
234 * flags: flags to use to map last level entries
235 * phys: physical address corresponding to vstart - physical memory is contiguous
236 * pgds: the number of pgd entries
237 *
238 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
239 * Preserves: vstart, vend, flags
240 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
241 */
242 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
243 add \rtbl, \tbl, #PAGE_SIZE
244 mov \sv, \rtbl
245 mov \count, #0
246 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
247 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
248 mov \tbl, \sv
249 mov \sv, \rtbl
251 #if SWAPPER_PGTABLE_LEVELS > 3
252 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
253 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
254 mov \tbl, \sv
255 mov \sv, \rtbl
256 #endif
258 #if SWAPPER_PGTABLE_LEVELS > 2
259 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
260 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
261 mov \tbl, \sv
262 #endif
264 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
265 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
266 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
267 .endm
269 /*
270 * Setup the initial page tables. We only setup the barest amount which is
271 * required to get the kernel running. The following sections are required:
272 * - identity mapping to enable the MMU (low address, TTBR0)
273 * - first few MB of the kernel linear mapping to jump to once the MMU has
274 * been enabled
275 */
276 __create_page_tables:
277 mov x28, lr
279 /*
280 * Invalidate the init page tables to avoid potential dirty cache lines
281 * being evicted. Other page tables are allocated in rodata as part of
282 * the kernel image, and thus are clean to the PoC per the boot
283 * protocol.
284 */
285 adrp x0, init_pg_dir
286 adrp x1, init_pg_end
287 sub x1, x1, x0
288 bl __inval_dcache_area
290 /*
291 * Clear the init page tables.
292 */
293 adrp x0, init_pg_dir
294 adrp x1, init_pg_end
295 sub x1, x1, x0
296 1: stp xzr, xzr, [x0], #16
297 stp xzr, xzr, [x0], #16
298 stp xzr, xzr, [x0], #16
299 stp xzr, xzr, [x0], #16
300 subs x1, x1, #64
301 b.ne 1b
303 mov x7, SWAPPER_MM_MMUFLAGS
305 /*
306 * Create the identity mapping.
307 */
308 adrp x0, idmap_pg_dir
309 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
311 #ifdef CONFIG_ARM64_USER_VA_BITS_52
312 mrs_s x6, SYS_ID_AA64MMFR2_EL1
313 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
314 mov x5, #52
315 cbnz x6, 1f
316 #endif
317 mov x5, #VA_BITS
318 1:
319 adr_l x6, vabits_user
320 str x5, [x6]
321 dmb sy
322 dc ivac, x6 // Invalidate potentially stale cache line
324 /*
325 * VA_BITS may be too small to allow for an ID mapping to be created
326 * that covers system RAM if that is located sufficiently high in the
327 * physical address space. So for the ID map, use an extended virtual
328 * range in that case, and configure an additional translation level
329 * if needed.
330 *
331 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
332 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
333 * this number conveniently equals the number of leading zeroes in
334 * the physical address of __idmap_text_end.
335 */
336 adrp x5, __idmap_text_end
337 clz x5, x5
338 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
339 b.ge 1f // .. then skip VA range extension
341 adr_l x6, idmap_t0sz
342 str x5, [x6]
343 dmb sy
344 dc ivac, x6 // Invalidate potentially stale cache line
346 #if (VA_BITS < 48)
347 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
348 #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
350 /*
351 * If VA_BITS < 48, we have to configure an additional table level.
352 * First, we have to verify our assumption that the current value of
353 * VA_BITS was chosen such that all translation levels are fully
354 * utilised, and that lowering T0SZ will always result in an additional
355 * translation level to be configured.
356 */
357 #if VA_BITS != EXTRA_SHIFT
358 #error "Mismatch between VA_BITS and page size/number of translation levels"
359 #endif
361 mov x4, EXTRA_PTRS
362 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
363 #else
364 /*
365 * If VA_BITS == 48, we don't have to configure an additional
366 * translation level, but the top-level table has more entries.
367 */
368 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
369 str_l x4, idmap_ptrs_per_pgd, x5
370 #endif
371 1:
372 ldr_l x4, idmap_ptrs_per_pgd
373 mov x5, x3 // __pa(__idmap_text_start)
374 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
376 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
378 /*
379 * Map the kernel image (starting with PHYS_OFFSET).
380 */
381 adrp x0, init_pg_dir
382 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
383 add x5, x5, x23 // add KASLR displacement
384 mov x4, PTRS_PER_PGD
385 adrp x6, _end // runtime __pa(_end)
386 adrp x3, _text // runtime __pa(_text)
387 sub x6, x6, x3 // _end - _text
388 add x6, x6, x5 // runtime __va(_end)
390 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
392 /*
393 * Since the page tables have been populated with non-cacheable
394 * accesses (MMU disabled), invalidate the idmap and swapper page
395 * tables again to remove any speculatively loaded cache lines.
396 */
397 adrp x0, idmap_pg_dir
398 adrp x1, init_pg_end
399 sub x1, x1, x0
400 dmb sy
401 bl __inval_dcache_area
403 ret x28
404 ENDPROC(__create_page_tables)
405 .ltorg
407 /*
408 * The following fragment of code is executed with the MMU enabled.
409 *
410 * x0 = __PHYS_OFFSET
411 */
412 __primary_switched:
413 adrp x4, init_thread_union
414 add sp, x4, #THREAD_SIZE
415 adr_l x5, init_task
416 msr sp_el0, x5 // Save thread_info
418 adr_l x8, vectors // load VBAR_EL1 with virtual
419 msr vbar_el1, x8 // vector table address
420 isb
422 stp xzr, x30, [sp, #-16]!
423 mov x29, sp
425 str_l x21, __fdt_pointer, x5 // Save FDT pointer
427 ldr_l x4, kimage_vaddr // Save the offset between
428 sub x4, x4, x0 // the kernel virtual and
429 str_l x4, kimage_voffset, x5 // physical mappings
431 // Clear BSS
432 adr_l x0, __bss_start
433 mov x1, xzr
434 adr_l x2, __bss_stop
435 sub x2, x2, x0
436 bl __pi_memset
437 dsb ishst // Make zero page visible to PTW
439 #ifdef CONFIG_KASAN
440 bl kasan_early_init
441 #endif
442 #ifdef CONFIG_RANDOMIZE_BASE
443 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
444 b.ne 0f
445 mov x0, x21 // pass FDT address in x0
446 bl kaslr_early_init // parse FDT for KASLR options
447 cbz x0, 0f // KASLR disabled? just proceed
448 orr x23, x23, x0 // record KASLR offset
449 ldp x29, x30, [sp], #16 // we must enable KASLR, return
450 ret // to __primary_switch()
451 0:
452 #endif
453 add sp, sp, #16
454 mov x29, #0
455 mov x30, #0
456 b start_kernel
457 ENDPROC(__primary_switched)
459 /*
460 * end early head section, begin head code that is also used for
461 * hotplug and needs to have the same protections as the text region
462 */
463 .section ".idmap.text","awx"
465 ENTRY(kimage_vaddr)
466 .quad _text - TEXT_OFFSET
467 EXPORT_SYMBOL(kimage_vaddr)
469 /*
470 * If we're fortunate enough to boot at EL2, ensure that the world is
471 * sane before dropping to EL1.
472 *
473 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
474 * booted in EL1 or EL2 respectively.
475 */
476 ENTRY(el2_setup)
477 msr SPsel, #1 // We want to use SP_EL{1,2}
478 mrs x0, CurrentEL
479 cmp x0, #CurrentEL_EL2
480 b.eq 1f
481 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
482 msr sctlr_el1, x0
483 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
484 isb
485 ret
487 1: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
488 msr sctlr_el2, x0
490 #ifdef CONFIG_ARM64_VHE
491 /*
492 * Check for VHE being present. For the rest of the EL2 setup,
493 * x2 being non-zero indicates that we do have VHE, and that the
494 * kernel is intended to run at EL2.
495 */
496 mrs x2, id_aa64mmfr1_el1
497 ubfx x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
498 #else
499 mov x2, xzr
500 #endif
502 /* Hyp configuration. */
503 mov_q x0, HCR_HOST_NVHE_FLAGS
504 cbz x2, set_hcr
505 mov_q x0, HCR_HOST_VHE_FLAGS
506 set_hcr:
507 msr hcr_el2, x0
508 isb
510 /*
511 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
512 * This is not necessary for VHE, since the host kernel runs in EL2,
513 * and EL0 accesses are configured in the later stage of boot process.
514 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
515 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
516 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
517 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
518 * EL2.
519 */
520 cbnz x2, 1f
521 mrs x0, cnthctl_el2
522 orr x0, x0, #3 // Enable EL1 physical timers
523 msr cnthctl_el2, x0
524 1:
525 msr cntvoff_el2, xzr // Clear virtual offset
527 #ifdef CONFIG_ARM_GIC_V3
528 /* GICv3 system register access */
529 mrs x0, id_aa64pfr0_el1
530 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
531 cbz x0, 3f
533 mrs_s x0, SYS_ICC_SRE_EL2
534 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
535 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
536 msr_s SYS_ICC_SRE_EL2, x0
537 isb // Make sure SRE is now set
538 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
539 tbz x0, #0, 3f // and check that it sticks
540 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
542 3:
543 #endif
545 /* Populate ID registers. */
546 mrs x0, midr_el1
547 mrs x1, mpidr_el1
548 msr vpidr_el2, x0
549 msr vmpidr_el2, x1
551 #ifdef CONFIG_COMPAT
552 msr hstr_el2, xzr // Disable CP15 traps to EL2
553 #endif
555 /* EL2 debug */
556 mrs x1, id_aa64dfr0_el1
557 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
558 cmp x0, #1
559 b.lt 4f // Skip if no PMU present
560 mrs x0, pmcr_el0 // Disable debug access traps
561 ubfx x0, x0, #11, #5 // to EL2 and allow access to
562 4:
563 csel x3, xzr, x0, lt // all PMU counters from EL1
565 /* Statistical profiling */
566 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
567 cbz x0, 7f // Skip if SPE not present
568 cbnz x2, 6f // VHE?
569 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2,
570 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
571 cbnz x4, 5f // then permit sampling of physical
572 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
573 1 << SYS_PMSCR_EL2_PA_SHIFT)
574 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter
575 5:
576 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
577 orr x3, x3, x1 // If we don't have VHE, then
578 b 7f // use EL1&0 translation.
579 6: // For VHE, use EL2 translation
580 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
581 7:
582 msr mdcr_el2, x3 // Configure debug traps
584 /* LORegions */
585 mrs x1, id_aa64mmfr1_el1
586 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
587 cbz x0, 1f
588 msr_s SYS_LORC_EL1, xzr
589 1:
591 /* Stage-2 translation */
592 msr vttbr_el2, xzr
594 cbz x2, install_el2_stub
596 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
597 isb
598 ret
600 install_el2_stub:
601 /*
602 * When VHE is not in use, early init of EL2 and EL1 needs to be
603 * done here.
604 * When VHE _is_ in use, EL1 will not be used in the host and
605 * requires no configuration, and all non-hyp-specific EL2 setup
606 * will be done via the _EL1 system register aliases in __cpu_setup.
607 */
608 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
609 msr sctlr_el1, x0
611 /* Coprocessor traps. */
612 mov x0, #0x33ff
613 msr cptr_el2, x0 // Disable copro. traps to EL2
615 /* SVE register access */
616 mrs x1, id_aa64pfr0_el1
617 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
618 cbz x1, 7f
620 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
621 msr cptr_el2, x0 // Disable copro. traps to EL2
622 isb
623 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
624 msr_s SYS_ZCR_EL2, x1 // length for EL1.
626 /* Hypervisor stub */
627 7: adr_l x0, __hyp_stub_vectors
628 msr vbar_el2, x0
630 /* spsr */
631 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
632 PSR_MODE_EL1h)
633 msr spsr_el2, x0
634 msr elr_el2, lr
635 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
636 eret
637 ENDPROC(el2_setup)
639 /*
640 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
641 * in w0. See arch/arm64/include/asm/virt.h for more info.
642 */
643 set_cpu_boot_mode_flag:
644 adr_l x1, __boot_cpu_mode
645 cmp w0, #BOOT_CPU_MODE_EL2
646 b.ne 1f
647 add x1, x1, #4
648 1: str w0, [x1] // This CPU has booted in EL1
649 dmb sy
650 dc ivac, x1 // Invalidate potentially stale cache line
651 ret
652 ENDPROC(set_cpu_boot_mode_flag)
654 /*
655 * These values are written with the MMU off, but read with the MMU on.
656 * Writers will invalidate the corresponding address, discarding up to a
657 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
658 * sufficient alignment that the CWG doesn't overlap another section.
659 */
660 .pushsection ".mmuoff.data.write", "aw"
661 /*
662 * We need to find out the CPU boot mode long after boot, so we need to
663 * store it in a writable variable.
664 *
665 * This is not in .bss, because we set it sufficiently early that the boot-time
666 * zeroing of .bss would clobber it.
667 */
668 ENTRY(__boot_cpu_mode)
669 .long BOOT_CPU_MODE_EL2
670 .long BOOT_CPU_MODE_EL1
671 /*
672 * The booting CPU updates the failed status @__early_cpu_boot_status,
673 * with MMU turned off.
674 */
675 ENTRY(__early_cpu_boot_status)
676 .quad 0
678 .popsection
680 /*
681 * This provides a "holding pen" for platforms to hold all secondary
682 * cores are held until we're ready for them to initialise.
683 */
684 ENTRY(secondary_holding_pen)
685 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
686 bl set_cpu_boot_mode_flag
687 mrs x0, mpidr_el1
688 mov_q x1, MPIDR_HWID_BITMASK
689 and x0, x0, x1
690 adr_l x3, secondary_holding_pen_release
691 pen: ldr x4, [x3]
692 cmp x4, x0
693 b.eq secondary_startup
694 wfe
695 b pen
696 ENDPROC(secondary_holding_pen)
698 /*
699 * Secondary entry point that jumps straight into the kernel. Only to
700 * be used where CPUs are brought online dynamically by the kernel.
701 */
702 ENTRY(secondary_entry)
703 bl el2_setup // Drop to EL1
704 bl set_cpu_boot_mode_flag
705 b secondary_startup
706 ENDPROC(secondary_entry)
708 secondary_startup:
709 /*
710 * Common entry point for secondary CPUs.
711 */
712 bl __cpu_secondary_check52bitva
713 bl __cpu_setup // initialise processor
714 adrp x1, swapper_pg_dir
715 bl __enable_mmu
716 ldr x8, =__secondary_switched
717 br x8
718 ENDPROC(secondary_startup)
720 __secondary_switched:
721 adr_l x5, vectors
722 msr vbar_el1, x5
723 isb
725 adr_l x0, secondary_data
726 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
727 mov sp, x1
728 ldr x2, [x0, #CPU_BOOT_TASK]
729 msr sp_el0, x2
730 mov x29, #0
731 mov x30, #0
732 b secondary_start_kernel
733 ENDPROC(__secondary_switched)
735 /*
736 * The booting CPU updates the failed status @__early_cpu_boot_status,
737 * with MMU turned off.
738 *
739 * update_early_cpu_boot_status tmp, status
740 * - Corrupts tmp1, tmp2
741 * - Writes 'status' to __early_cpu_boot_status and makes sure
742 * it is committed to memory.
743 */
745 .macro update_early_cpu_boot_status status, tmp1, tmp2
746 mov \tmp2, #\status
747 adr_l \tmp1, __early_cpu_boot_status
748 str \tmp2, [\tmp1]
749 dmb sy
750 dc ivac, \tmp1 // Invalidate potentially stale cache line
751 .endm
753 /*
754 * Enable the MMU.
755 *
756 * x0 = SCTLR_EL1 value for turning on the MMU.
757 * x1 = TTBR1_EL1 value
758 *
759 * Returns to the caller via x30/lr. This requires the caller to be covered
760 * by the .idmap.text section.
761 *
762 * Checks if the selected granule size is supported by the CPU.
763 * If it isn't, park the CPU
764 */
765 ENTRY(__enable_mmu)
766 mrs x2, ID_AA64MMFR0_EL1
767 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
768 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
769 b.ne __no_granule_support
770 update_early_cpu_boot_status 0, x2, x3
771 adrp x2, idmap_pg_dir
772 phys_to_ttbr x1, x1
773 phys_to_ttbr x2, x2
774 msr ttbr0_el1, x2 // load TTBR0
775 offset_ttbr1 x1
776 msr ttbr1_el1, x1 // load TTBR1
777 isb
778 msr sctlr_el1, x0
779 isb
780 /*
781 * Invalidate the local I-cache so that any instructions fetched
782 * speculatively from the PoC are discarded, since they may have
783 * been dynamically patched at the PoU.
784 */
785 ic iallu
786 dsb nsh
787 isb
788 ret
789 ENDPROC(__enable_mmu)
791 ENTRY(__cpu_secondary_check52bitva)
792 #ifdef CONFIG_ARM64_USER_VA_BITS_52
793 ldr_l x0, vabits_user
794 cmp x0, #52
795 b.ne 2f
797 mrs_s x0, SYS_ID_AA64MMFR2_EL1
798 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
799 cbnz x0, 2f
801 update_early_cpu_boot_status \
802 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
803 1: wfe
804 wfi
805 b 1b
807 #endif
808 2: ret
809 ENDPROC(__cpu_secondary_check52bitva)
811 __no_granule_support:
812 /* Indicate that this CPU can't boot and is stuck in the kernel */
813 update_early_cpu_boot_status \
814 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
815 1:
816 wfe
817 wfi
818 b 1b
819 ENDPROC(__no_granule_support)
821 #ifdef CONFIG_RELOCATABLE
822 __relocate_kernel:
823 /*
824 * Iterate over each entry in the relocation table, and apply the
825 * relocations in place.
826 */
827 ldr w9, =__rela_offset // offset to reloc table
828 ldr w10, =__rela_size // size of reloc table
830 mov_q x11, KIMAGE_VADDR // default virtual offset
831 add x11, x11, x23 // actual virtual offset
832 add x9, x9, x11 // __va(.rela)
833 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
835 0: cmp x9, x10
836 b.hs 1f
837 ldp x11, x12, [x9], #24
838 ldr x13, [x9, #-8]
839 cmp w12, #R_AARCH64_RELATIVE
840 b.ne 0b
841 add x13, x13, x23 // relocate
842 str x13, [x11, x23]
843 b 0b
844 1: ret
845 ENDPROC(__relocate_kernel)
846 #endif
848 __primary_switch:
849 #ifdef CONFIG_RANDOMIZE_BASE
850 mov x19, x0 // preserve new SCTLR_EL1 value
851 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
852 #endif
854 adrp x1, init_pg_dir
855 bl __enable_mmu
856 #ifdef CONFIG_RELOCATABLE
857 bl __relocate_kernel
858 #ifdef CONFIG_RANDOMIZE_BASE
859 ldr x8, =__primary_switched
860 adrp x0, __PHYS_OFFSET
861 blr x8
863 /*
864 * If we return here, we have a KASLR displacement in x23 which we need
865 * to take into account by discarding the current kernel mapping and
866 * creating a new one.
867 */
868 pre_disable_mmu_workaround
869 msr sctlr_el1, x20 // disable the MMU
870 isb
871 bl __create_page_tables // recreate kernel mapping
873 tlbi vmalle1 // Remove any stale TLB entries
874 dsb nsh
876 msr sctlr_el1, x19 // re-enable the MMU
877 isb
878 ic iallu // flush instructions fetched
879 dsb nsh // via old mapping
880 isb
882 bl __relocate_kernel
883 #endif
884 #endif
885 ldr x8, =__primary_switched
886 adrp x0, __PHYS_OFFSET
887 br x8
888 ENDPROC(__primary_switch)