1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 ARM Ltd.
4 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 #include <linux/cache.h>
9 #include <linux/dma-noncoherent.h>
10 #include <linux/dma-iommu.h>
12 #include <asm/cacheflush.h>
14 pgprot_t
arch_dma_mmap_pgprot(struct device
*dev
, pgprot_t prot
,
17 return pgprot_writecombine(prot
);
20 void arch_sync_dma_for_device(struct device
*dev
, phys_addr_t paddr
,
21 size_t size
, enum dma_data_direction dir
)
23 __dma_map_area(phys_to_virt(paddr
), size
, dir
);
26 void arch_sync_dma_for_cpu(struct device
*dev
, phys_addr_t paddr
,
27 size_t size
, enum dma_data_direction dir
)
29 __dma_unmap_area(phys_to_virt(paddr
), size
, dir
);
32 void arch_dma_prep_coherent(struct page
*page
, size_t size
)
34 __dma_flush_area(page_address(page
), size
);
37 static int __init
arm64_dma_init(void)
39 return dma_atomic_pool_init(GFP_DMA32
, __pgprot(PROT_NORMAL_NC
));
41 arch_initcall(arm64_dma_init
);
43 #ifdef CONFIG_IOMMU_DMA
44 void arch_teardown_dma_ops(struct device
*dev
)
50 void arch_setup_dma_ops(struct device
*dev
, u64 dma_base
, u64 size
,
51 const struct iommu_ops
*iommu
, bool coherent
)
53 int cls
= cache_line_size_of_cpu();
55 WARN_TAINT(!coherent
&& cls
> ARCH_DMA_MINALIGN
,
56 TAINT_CPU_OUT_OF_SPEC
,
57 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
58 dev_driver_string(dev
), dev_name(dev
),
59 ARCH_DMA_MINALIGN
, cls
);
61 dev
->dma_coherent
= coherent
;
63 iommu_setup_dma_ops(dev
, dma_base
, size
);
66 if (xen_initial_domain())
67 dev
->dma_ops
= xen_dma_ops
;