arch/mips/pci/pci-xtalk-bridge.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
   4  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
   5  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/export.h>
   9 #include <linux/pci.h>
  10 #include <linux/smp.h>
  11 #include <linux/dma-direct.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/platform_data/xtalk-bridge.h>
  14
  15 #include <asm/pci/bridge.h>
  16 #include <asm/paccess.h>
  17 #include <asm/sn/irq_alloc.h>
  18
  19 /*
  20  * Most of the IOC3 PCI config register aren't present
  21  * we emulate what is needed for a normal PCI enumeration
  22  */
  23 static u32 emulate_ioc3_cfg(int where, int size)
  24 {
  25         if (size == 1 && where == 0x3d)
  26                 return 0x01;
  27         else if (size == 2 && where == 0x3c)
  28                 return 0x0100;
  29         else if (size == 4 && where == 0x3c)
  30                 return 0x00000100;
  31
  32         return 0;
  33 }
  34
  35 static void bridge_disable_swapping(struct pci_dev *dev)
  36 {
  37         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
  38         int slot = PCI_SLOT(dev->devfn);
  39
  40         /* Turn off byte swapping */
  41         bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
  42         bridge_read(bc, b_widget.w_tflush);     /* Flush */
  43 }
  44
  45 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
  46         bridge_disable_swapping);
  47
  48
  49 /*
  50  * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
  51  * not really documented, so right now I can't write code which uses it.
  52  * Therefore we use type 0 accesses for now even though they won't work
  53  * correctly for PCI-to-PCI bridges.
  54  *
  55  * The function is complicated by the ultimate brokenness of the IOC3 chip
  56  * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
  57  * accesses and does only decode parts of it's address space.
  58  */
  59 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
  60                                  int where, int size, u32 *value)
  61 {
  62         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
  63         struct bridge_regs *bridge = bc->base;
  64         int slot = PCI_SLOT(devfn);
  65         int fn = PCI_FUNC(devfn);
  66         void *addr;
  67         u32 cf, shift, mask;
  68         int res;
  69
  70         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
  71         if (get_dbe(cf, (u32 *)addr))
  72                 return PCIBIOS_DEVICE_NOT_FOUND;
  73
  74         /*
  75          * IOC3 is broken beyond belief ...  Don't even give the
  76          * generic PCI code a chance to look at it for real ...
  77          */
  78         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
  79                 goto is_ioc3;
  80
  81         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
  82
  83         if (size == 1)
  84                 res = get_dbe(*value, (u8 *)addr);
  85         else if (size == 2)
  86                 res = get_dbe(*value, (u16 *)addr);
  87         else
  88                 res = get_dbe(*value, (u32 *)addr);
  89
  90         return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  91
  92 is_ioc3:
  93
  94         /*
  95          * IOC3 special handling
  96          */
  97         if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
  98                 *value = emulate_ioc3_cfg(where, size);
  99                 return PCIBIOS_SUCCESSFUL;
 100         }
 101
 102         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 103         if (get_dbe(cf, (u32 *)addr))
 104                 return PCIBIOS_DEVICE_NOT_FOUND;
 105
 106         shift = ((where & 3) << 3);
 107         mask = (0xffffffffU >> ((4 - size) << 3));
 108         *value = (cf >> shift) & mask;
 109
 110         return PCIBIOS_SUCCESSFUL;
 111 }
 112
 113 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
 114                                  int where, int size, u32 *value)
 115 {
 116         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 117         struct bridge_regs *bridge = bc->base;
 118         int busno = bus->number;
 119         int slot = PCI_SLOT(devfn);
 120         int fn = PCI_FUNC(devfn);
 121         void *addr;
 122         u32 cf, shift, mask;
 123         int res;
 124
 125         bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
 126         addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
 127         if (get_dbe(cf, (u32 *)addr))
 128                 return PCIBIOS_DEVICE_NOT_FOUND;
 129
 130         /*
 131          * IOC3 is broken beyond belief ...  Don't even give the
 132          * generic PCI code a chance to look at it for real ...
 133          */
 134         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
 135                 goto is_ioc3;
 136
 137         addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
 138
 139         if (size == 1)
 140                 res = get_dbe(*value, (u8 *)addr);
 141         else if (size == 2)
 142                 res = get_dbe(*value, (u16 *)addr);
 143         else
 144                 res = get_dbe(*value, (u32 *)addr);
 145
 146         return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 147
 148 is_ioc3:
 149
 150         /*
 151          * IOC3 special handling
 152          */
 153         if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
 154                 *value = emulate_ioc3_cfg(where, size);
 155                 return PCIBIOS_SUCCESSFUL;
 156         }
 157
 158         addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
 159         if (get_dbe(cf, (u32 *)addr))
 160                 return PCIBIOS_DEVICE_NOT_FOUND;
 161
 162         shift = ((where & 3) << 3);
 163         mask = (0xffffffffU >> ((4 - size) << 3));
 164         *value = (cf >> shift) & mask;
 165
 166         return PCIBIOS_SUCCESSFUL;
 167 }
 168
 169 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
 170                            int where, int size, u32 *value)
 171 {
 172         if (!pci_is_root_bus(bus))
 173                 return pci_conf1_read_config(bus, devfn, where, size, value);
 174
 175         return pci_conf0_read_config(bus, devfn, where, size, value);
 176 }
 177
 178 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
 179                                   int where, int size, u32 value)
 180 {
 181         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 182         struct bridge_regs *bridge = bc->base;
 183         int slot = PCI_SLOT(devfn);
 184         int fn = PCI_FUNC(devfn);
 185         void *addr;
 186         u32 cf, shift, mask, smask;
 187         int res;
 188
 189         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
 190         if (get_dbe(cf, (u32 *)addr))
 191                 return PCIBIOS_DEVICE_NOT_FOUND;
 192
 193         /*
 194          * IOC3 is broken beyond belief ...  Don't even give the
 195          * generic PCI code a chance to look at it for real ...
 196          */
 197         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
 198                 goto is_ioc3;
 199
 200         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
 201
 202         if (size == 1)
 203                 res = put_dbe(value, (u8 *)addr);
 204         else if (size == 2)
 205                 res = put_dbe(value, (u16 *)addr);
 206         else
 207                 res = put_dbe(value, (u32 *)addr);
 208
 209         if (res)
 210                 return PCIBIOS_DEVICE_NOT_FOUND;
 211
 212         return PCIBIOS_SUCCESSFUL;
 213
 214 is_ioc3:
 215
 216         /*
 217          * IOC3 special handling
 218          */
 219         if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
 220                 return PCIBIOS_SUCCESSFUL;
 221
 222         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 223
 224         if (get_dbe(cf, (u32 *)addr))
 225                 return PCIBIOS_DEVICE_NOT_FOUND;
 226
 227         shift = ((where & 3) << 3);
 228         mask = (0xffffffffU >> ((4 - size) << 3));
 229         smask = mask << shift;
 230
 231         cf = (cf & ~smask) | ((value & mask) << shift);
 232         if (put_dbe(cf, (u32 *)addr))
 233                 return PCIBIOS_DEVICE_NOT_FOUND;
 234
 235         return PCIBIOS_SUCCESSFUL;
 236 }
 237
 238 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
 239                                   int where, int size, u32 value)
 240 {
 241         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 242         struct bridge_regs *bridge = bc->base;
 243         int slot = PCI_SLOT(devfn);
 244         int fn = PCI_FUNC(devfn);
 245         int busno = bus->number;
 246         void *addr;
 247         u32 cf, shift, mask, smask;
 248         int res;
 249
 250         bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
 251         addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
 252         if (get_dbe(cf, (u32 *)addr))
 253                 return PCIBIOS_DEVICE_NOT_FOUND;
 254
 255         /*
 256          * IOC3 is broken beyond belief ...  Don't even give the
 257          * generic PCI code a chance to look at it for real ...
 258          */
 259         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
 260                 goto is_ioc3;
 261
 262         addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
 263
 264         if (size == 1)
 265                 res = put_dbe(value, (u8 *)addr);
 266         else if (size == 2)
 267                 res = put_dbe(value, (u16 *)addr);
 268         else
 269                 res = put_dbe(value, (u32 *)addr);
 270
 271         if (res)
 272                 return PCIBIOS_DEVICE_NOT_FOUND;
 273
 274         return PCIBIOS_SUCCESSFUL;
 275
 276 is_ioc3:
 277
 278         /*
 279          * IOC3 special handling
 280          */
 281         if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
 282                 return PCIBIOS_SUCCESSFUL;
 283
 284         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 285         if (get_dbe(cf, (u32 *)addr))
 286                 return PCIBIOS_DEVICE_NOT_FOUND;
 287
 288         shift = ((where & 3) << 3);
 289         mask = (0xffffffffU >> ((4 - size) << 3));
 290         smask = mask << shift;
 291
 292         cf = (cf & ~smask) | ((value & mask) << shift);
 293         if (put_dbe(cf, (u32 *)addr))
 294                 return PCIBIOS_DEVICE_NOT_FOUND;
 295
 296         return PCIBIOS_SUCCESSFUL;
 297 }
 298
 299 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
 300         int where, int size, u32 value)
 301 {
 302         if (!pci_is_root_bus(bus))
 303                 return pci_conf1_write_config(bus, devfn, where, size, value);
 304
 305         return pci_conf0_write_config(bus, devfn, where, size, value);
 306 }
 307
 308 static struct pci_ops bridge_pci_ops = {
 309         .read    = pci_read_config,
 310         .write   = pci_write_config,
 311 };
 312
 313 struct bridge_irq_chip_data {
 314         struct bridge_controller *bc;
 315         nasid_t nasid;
 316 };
 317
 318 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
 319                                bool force)
 320 {
 321 #ifdef CONFIG_NUMA
 322         struct bridge_irq_chip_data *data = d->chip_data;
 323         int bit = d->parent_data->hwirq;
 324         int pin = d->hwirq;
 325         nasid_t nasid;
 326         int ret, cpu;
 327
 328         ret = irq_chip_set_affinity_parent(d, mask, force);
 329         if (ret >= 0) {
 330                 cpu = cpumask_first_and(mask, cpu_online_mask);
 331                 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
 332                 bridge_write(data->bc, b_int_addr[pin].addr,
 333                              (((data->bc->intr_addr >> 30) & 0x30000) |
 334                               bit | (nasid << 8)));
 335                 bridge_read(data->bc, b_wid_tflush);
 336         }
 337         return ret;
 338 #else
 339         return irq_chip_set_affinity_parent(d, mask, force);
 340 #endif
 341 }
 342
 343 struct irq_chip bridge_irq_chip = {
 344         .name             = "BRIDGE",
 345         .irq_mask         = irq_chip_mask_parent,
 346         .irq_unmask       = irq_chip_unmask_parent,
 347         .irq_set_affinity = bridge_set_affinity
 348 };
 349
 350 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
 351                                unsigned int nr_irqs, void *arg)
 352 {
 353         struct bridge_irq_chip_data *data;
 354         struct irq_alloc_info *info = arg;
 355         int ret;
 356
 357         if (nr_irqs > 1 || !info)
 358                 return -EINVAL;
 359
 360         data = kzalloc(sizeof(*data), GFP_KERNEL);
 361         if (!data)
 362                 return -ENOMEM;
 363
 364         ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
 365         if (ret >= 0) {
 366                 data->bc = info->ctrl;
 367                 data->nasid = info->nasid;
 368                 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
 369                                     data, handle_level_irq, NULL, NULL);
 370         } else {
 371                 kfree(data);
 372         }
 373
 374         return ret;
 375 }
 376
 377 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
 378                                unsigned int nr_irqs)
 379 {
 380         struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
 381
 382         if (nr_irqs)
 383                 return;
 384
 385         kfree(irqd->chip_data);
 386         irq_domain_free_irqs_top(domain, virq, nr_irqs);
 387 }
 388
 389 static int bridge_domain_activate(struct irq_domain *domain,
 390                                   struct irq_data *irqd, bool reserve)
 391 {
 392         struct bridge_irq_chip_data *data = irqd->chip_data;
 393         struct bridge_controller *bc = data->bc;
 394         int bit = irqd->parent_data->hwirq;
 395         int pin = irqd->hwirq;
 396         u32 device;
 397
 398         bridge_write(bc, b_int_addr[pin].addr,
 399                      (((bc->intr_addr >> 30) & 0x30000) |
 400                       bit | (data->nasid << 8)));
 401         bridge_set(bc, b_int_enable, (1 << pin));
 402         bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
 403
 404         /*
 405          * Enable sending of an interrupt clear packt to the hub on a high to
 406          * low transition of the interrupt pin.
 407          *
 408          * IRIX sets additional bits in the address which are documented as
 409          * reserved in the bridge docs.
 410          */
 411         bridge_set(bc, b_int_mode, (1UL << pin));
 412
 413         /*
 414          * We assume the bridge to have a 1:1 mapping between devices
 415          * (slots) and intr pins.
 416          */
 417         device = bridge_read(bc, b_int_device);
 418         device &= ~(7 << (pin*3));
 419         device |= (pin << (pin*3));
 420         bridge_write(bc, b_int_device, device);
 421
 422         bridge_read(bc, b_wid_tflush);
 423         return 0;
 424 }
 425
 426 static void bridge_domain_deactivate(struct irq_domain *domain,
 427                                      struct irq_data *irqd)
 428 {
 429         struct bridge_irq_chip_data *data = irqd->chip_data;
 430
 431         bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
 432         bridge_read(data->bc, b_wid_tflush);
 433 }
 434
 435 static const struct irq_domain_ops bridge_domain_ops = {
 436         .alloc      = bridge_domain_alloc,
 437         .free       = bridge_domain_free,
 438         .activate   = bridge_domain_activate,
 439         .deactivate = bridge_domain_deactivate
 440 };
 441
 442 /*
 443  * All observed requests have pin == 1. We could have a global here, that
 444  * gets incremented and returned every time - unfortunately, pci_map_irq
 445  * may be called on the same device over and over, and need to return the
 446  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
 447  *
 448  * A given PCI device, in general, should be able to intr any of the cpus
 449  * on any one of the hubs connected to its xbow.
 450  */
 451 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 452 {
 453         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 454         struct irq_alloc_info info;
 455         int irq;
 456
 457         irq = bc->pci_int[slot];
 458         if (irq == -1) {
 459                 info.ctrl = bc;
 460                 info.nasid = bc->nasid;
 461                 info.pin = slot;
 462
 463                 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
 464                 if (irq < 0)
 465                         return irq;
 466
 467                 bc->pci_int[slot] = irq;
 468         }
 469         return irq;
 470 }
 471
 472 static int bridge_probe(struct platform_device *pdev)
 473 {
 474         struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
 475         struct device *dev = &pdev->dev;
 476         struct bridge_controller *bc;
 477         struct pci_host_bridge *host;
 478         struct irq_domain *domain, *parent;
 479         struct fwnode_handle *fn;
 480         int slot;
 481         int err;
 482
 483         parent = irq_get_default_host();
 484         if (!parent)
 485                 return -ENODEV;
 486         fn = irq_domain_alloc_named_fwnode("BRIDGE");
 487         if (!fn)
 488                 return -ENOMEM;
 489         domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
 490                                              &bridge_domain_ops, NULL);
 491         irq_domain_free_fwnode(fn);
 492         if (!domain)
 493                 return -ENOMEM;
 494
 495         pci_set_flags(PCI_PROBE_ONLY);
 496
 497         host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
 498         if (!host) {
 499                 err = -ENOMEM;
 500                 goto err_remove_domain;
 501         }
 502
 503         bc = pci_host_bridge_priv(host);
 504
 505         bc->busn.name           = "Bridge PCI busn";
 506         bc->busn.start          = 0;
 507         bc->busn.end            = 0xff;
 508         bc->busn.flags          = IORESOURCE_BUS;
 509
 510         bc->domain              = domain;
 511
 512         pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
 513         pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
 514         pci_add_resource(&host->windows, &bc->busn);
 515
 516         err = devm_request_pci_bus_resources(dev, &host->windows);
 517         if (err < 0)
 518                 goto err_free_resource;
 519
 520         bc->nasid = bd->nasid;
 521
 522         bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
 523         bc->base = (struct bridge_regs *)bd->bridge_addr;
 524         bc->intr_addr = bd->intr_addr;
 525
 526         /*
 527          * Clear all pending interrupts.
 528          */
 529         bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
 530
 531         /*
 532          * Until otherwise set up, assume all interrupts are from slot 0
 533          */
 534         bridge_write(bc, b_int_device, 0x0);
 535
 536         /*
 537          * disable swapping for big windows
 538          */
 539         bridge_clr(bc, b_wid_control,
 540                    BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
 541 #ifdef CONFIG_PAGE_SIZE_4KB
 542         bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
 543 #else /* 16kB or larger */
 544         bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
 545 #endif
 546
 547         /*
 548          * Hmm...  IRIX sets additional bits in the address which
 549          * are documented as reserved in the bridge docs.
 550          */
 551         bridge_write(bc, b_wid_int_upper,
 552                      ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
 553         bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
 554         bridge_write(bc, b_dir_map, (bd->masterwid << 20));     /* DMA */
 555         bridge_write(bc, b_int_enable, 0);
 556
 557         for (slot = 0; slot < 8; slot++) {
 558                 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
 559                 bc->pci_int[slot] = -1;
 560         }
 561         bridge_read(bc, b_wid_tflush);    /* wait until Bridge PIO complete */
 562
 563         host->dev.parent = dev;
 564         host->sysdata = bc;
 565         host->busnr = 0;
 566         host->ops = &bridge_pci_ops;
 567         host->map_irq = bridge_map_irq;
 568         host->swizzle_irq = pci_common_swizzle;
 569
 570         err = pci_scan_root_bus_bridge(host);
 571         if (err < 0)
 572                 goto err_free_resource;
 573
 574         pci_bus_claim_resources(host->bus);
 575         pci_bus_add_devices(host->bus);
 576
 577         platform_set_drvdata(pdev, host->bus);
 578
 579         return 0;
 580
 581 err_free_resource:
 582         pci_free_resource_list(&host->windows);
 583 err_remove_domain:
 584         irq_domain_remove(domain);
 585         return err;
 586 }
 587
 588 static int bridge_remove(struct platform_device *pdev)
 589 {
 590         struct pci_bus *bus = platform_get_drvdata(pdev);
 591         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 592
 593         irq_domain_remove(bc->domain);
 594         pci_lock_rescan_remove();
 595         pci_stop_root_bus(bus);
 596         pci_remove_root_bus(bus);
 597         pci_unlock_rescan_remove();
 598
 599         return 0;
 600 }
 601
 602 static struct platform_driver bridge_driver = {
 603         .probe  = bridge_probe,
 604         .remove = bridge_remove,
 605         .driver = {
 606                 .name = "xtalk-bridge",
 607         }
 608 };
 609
 610 builtin_platform_driver(bridge_driver);