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staging: rtl8192u: remove redundant assignment to pointer crypt
[linux/fpc-iii.git] / arch / s390 / net / bpf_jit_comp.c
blobe636728ab452e1818f3566727396945264f3af3b
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BPF Jit compiler for s390.
4 *
5 * Minimum build requirements:
6 *
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
10 * - PACK_STACK
11 * - 64BIT
12 *
13 * Copyright IBM Corp. 2012,2015
14 *
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
17 */
18
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
27 #include <asm/dis.h>
28 #include <asm/facility.h>
29 #include <asm/nospec-branch.h>
30 #include <asm/set_memory.h>
31 #include "bpf_jit.h"
32
33 struct bpf_jit {
34 u32 seen; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg[16]; /* Array to remember which registers are used */
36 u32 *addrs; /* Array with relative instruction addresses */
37 u8 *prg_buf; /* Start of program */
38 int size; /* Size of program and literal pool */
39 int size_prg; /* Size of program */
40 int prg; /* Current position in program */
41 int lit_start; /* Start of literal pool */
42 int lit; /* Current position in literal pool */
43 int base_ip; /* Base address for literal pool */
44 int ret0_ip; /* Address of return 0 */
45 int exit_ip; /* Address of exit */
46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
48 int tail_call_start; /* Tail call start offset */
49 int labels[1]; /* Labels for local jumps */
50 };
51
52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
53
54 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */
55 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */
56 #define SEEN_LITERAL (1 << 2) /* code uses literals */
57 #define SEEN_FUNC (1 << 3) /* calls C functions */
58 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */
59 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */
60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
61
62 /*
63 * s390 registers
64 */
65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
69 #define REG_0 REG_W0 /* Register 0 */
70 #define REG_1 REG_W1 /* Register 1 */
71 #define REG_2 BPF_REG_1 /* Register 2 */
72 #define REG_14 BPF_REG_0 /* Register 14 */
73
74 /*
75 * Mapping of BPF registers to s390 registers
76 */
77 static const int reg2hex[] = {
78 /* Return code */
79 [BPF_REG_0] = 14,
80 /* Function parameters */
81 [BPF_REG_1] = 2,
82 [BPF_REG_2] = 3,
83 [BPF_REG_3] = 4,
84 [BPF_REG_4] = 5,
85 [BPF_REG_5] = 6,
86 /* Call saved registers */
87 [BPF_REG_6] = 7,
88 [BPF_REG_7] = 8,
89 [BPF_REG_8] = 9,
90 [BPF_REG_9] = 10,
91 /* BPF stack pointer */
92 [BPF_REG_FP] = 13,
93 /* Register for blinding */
94 [BPF_REG_AX] = 12,
95 /* Work registers for s390x backend */
96 [REG_W0] = 0,
97 [REG_W1] = 1,
98 [REG_L] = 11,
99 [REG_15] = 15,
100 };
101
102 static inline u32 reg(u32 dst_reg, u32 src_reg)
103 {
104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
105 }
106
107 static inline u32 reg_high(u32 reg)
108 {
109 return reg2hex[reg] << 4;
110 }
111
112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
113 {
114 u32 r1 = reg2hex[b1];
115
116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
117 jit->seen_reg[r1] = 1;
118 }
119
120 #define REG_SET_SEEN(b1) \
121 ({ \
122 reg_set_seen(jit, b1); \
123 })
124
125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
126
127 /*
128 * EMIT macros for code generation
129 */
130
131 #define _EMIT2(op) \
132 ({ \
133 if (jit->prg_buf) \
134 *(u16 *) (jit->prg_buf + jit->prg) = op; \
135 jit->prg += 2; \
136 })
137
138 #define EMIT2(op, b1, b2) \
139 ({ \
140 _EMIT2(op | reg(b1, b2)); \
141 REG_SET_SEEN(b1); \
142 REG_SET_SEEN(b2); \
143 })
144
145 #define _EMIT4(op) \
146 ({ \
147 if (jit->prg_buf) \
148 *(u32 *) (jit->prg_buf + jit->prg) = op; \
149 jit->prg += 4; \
150 })
151
152 #define EMIT4(op, b1, b2) \
153 ({ \
154 _EMIT4(op | reg(b1, b2)); \
155 REG_SET_SEEN(b1); \
156 REG_SET_SEEN(b2); \
157 })
158
159 #define EMIT4_RRF(op, b1, b2, b3) \
160 ({ \
161 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
162 REG_SET_SEEN(b1); \
163 REG_SET_SEEN(b2); \
164 REG_SET_SEEN(b3); \
165 })
166
167 #define _EMIT4_DISP(op, disp) \
168 ({ \
169 unsigned int __disp = (disp) & 0xfff; \
170 _EMIT4(op | __disp); \
171 })
172
173 #define EMIT4_DISP(op, b1, b2, disp) \
174 ({ \
175 _EMIT4_DISP(op | reg_high(b1) << 16 | \
176 reg_high(b2) << 8, disp); \
177 REG_SET_SEEN(b1); \
178 REG_SET_SEEN(b2); \
179 })
180
181 #define EMIT4_IMM(op, b1, imm) \
182 ({ \
183 unsigned int __imm = (imm) & 0xffff; \
184 _EMIT4(op | reg_high(b1) << 16 | __imm); \
185 REG_SET_SEEN(b1); \
186 })
187
188 #define EMIT4_PCREL(op, pcrel) \
189 ({ \
190 long __pcrel = ((pcrel) >> 1) & 0xffff; \
191 _EMIT4(op | __pcrel); \
192 })
193
194 #define _EMIT6(op1, op2) \
195 ({ \
196 if (jit->prg_buf) { \
197 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
198 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
199 } \
200 jit->prg += 6; \
201 })
202
203 #define _EMIT6_DISP(op1, op2, disp) \
204 ({ \
205 unsigned int __disp = (disp) & 0xfff; \
206 _EMIT6(op1 | __disp, op2); \
207 })
208
209 #define _EMIT6_DISP_LH(op1, op2, disp) \
210 ({ \
211 u32 _disp = (u32) disp; \
212 unsigned int __disp_h = _disp & 0xff000; \
213 unsigned int __disp_l = _disp & 0x00fff; \
214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
215 })
216
217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
218 ({ \
219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
220 reg_high(b3) << 8, op2, disp); \
221 REG_SET_SEEN(b1); \
222 REG_SET_SEEN(b2); \
223 REG_SET_SEEN(b3); \
224 })
225
226 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
227 ({ \
228 int rel = (jit->labels[label] - jit->prg) >> 1; \
229 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
230 op2 | mask << 12); \
231 REG_SET_SEEN(b1); \
232 REG_SET_SEEN(b2); \
233 })
234
235 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
236 ({ \
237 int rel = (jit->labels[label] - jit->prg) >> 1; \
238 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
239 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
240 REG_SET_SEEN(b1); \
241 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
242 })
243
244 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
245 ({ \
246 /* Branch instruction needs 6 bytes */ \
247 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
248 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
249 REG_SET_SEEN(b1); \
250 REG_SET_SEEN(b2); \
251 })
252
253 #define EMIT6_PCREL_RILB(op, b, target) \
254 ({ \
255 int rel = (target - jit->prg) / 2; \
256 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
257 REG_SET_SEEN(b); \
258 })
259
260 #define EMIT6_PCREL_RIL(op, target) \
261 ({ \
262 int rel = (target - jit->prg) / 2; \
263 _EMIT6(op | rel >> 16, rel & 0xffff); \
264 })
265
266 #define _EMIT6_IMM(op, imm) \
267 ({ \
268 unsigned int __imm = (imm); \
269 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
270 })
271
272 #define EMIT6_IMM(op, b1, imm) \
273 ({ \
274 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
275 REG_SET_SEEN(b1); \
276 })
277
278 #define EMIT_CONST_U32(val) \
279 ({ \
280 unsigned int ret; \
281 ret = jit->lit - jit->base_ip; \
282 jit->seen |= SEEN_LITERAL; \
283 if (jit->prg_buf) \
284 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
285 jit->lit += 4; \
286 ret; \
287 })
288
289 #define EMIT_CONST_U64(val) \
290 ({ \
291 unsigned int ret; \
292 ret = jit->lit - jit->base_ip; \
293 jit->seen |= SEEN_LITERAL; \
294 if (jit->prg_buf) \
295 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
296 jit->lit += 8; \
297 ret; \
298 })
299
300 #define EMIT_ZERO(b1) \
301 ({ \
302 if (!fp->aux->verifier_zext) { \
303 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
304 EMIT4(0xb9160000, b1, b1); \
305 REG_SET_SEEN(b1); \
306 } \
307 })
308
309 /*
310 * Fill whole space with illegal instructions
311 */
312 static void jit_fill_hole(void *area, unsigned int size)
313 {
314 memset(area, 0, size);
315 }
316
317 /*
318 * Save registers from "rs" (register start) to "re" (register end) on stack
319 */
320 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
321 {
322 u32 off = STK_OFF_R6 + (rs - 6) * 8;
323
324 if (rs == re)
325 /* stg %rs,off(%r15) */
326 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
327 else
328 /* stmg %rs,%re,off(%r15) */
329 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
330 }
331
332 /*
333 * Restore registers from "rs" (register start) to "re" (register end) on stack
334 */
335 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
336 {
337 u32 off = STK_OFF_R6 + (rs - 6) * 8;
338
339 if (jit->seen & SEEN_STACK)
340 off += STK_OFF + stack_depth;
341
342 if (rs == re)
343 /* lg %rs,off(%r15) */
344 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
345 else
346 /* lmg %rs,%re,off(%r15) */
347 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
348 }
349
350 /*
351 * Return first seen register (from start)
352 */
353 static int get_start(struct bpf_jit *jit, int start)
354 {
355 int i;
356
357 for (i = start; i <= 15; i++) {
358 if (jit->seen_reg[i])
359 return i;
360 }
361 return 0;
362 }
363
364 /*
365 * Return last seen register (from start) (gap >= 2)
366 */
367 static int get_end(struct bpf_jit *jit, int start)
368 {
369 int i;
370
371 for (i = start; i < 15; i++) {
372 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
373 return i - 1;
374 }
375 return jit->seen_reg[15] ? 15 : 14;
376 }
377
378 #define REGS_SAVE 1
379 #define REGS_RESTORE 0
380 /*
381 * Save and restore clobbered registers (6-15) on stack.
382 * We save/restore registers in chunks with gap >= 2 registers.
383 */
384 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
385 {
386
387 int re = 6, rs;
388
389 do {
390 rs = get_start(jit, re);
391 if (!rs)
392 break;
393 re = get_end(jit, rs + 1);
394 if (op == REGS_SAVE)
395 save_regs(jit, rs, re);
396 else
397 restore_regs(jit, rs, re, stack_depth);
398 re++;
399 } while (re <= 15);
400 }
401
402 /*
403 * Emit function prologue
404 *
405 * Save registers and create stack frame if necessary.
406 * See stack frame layout desription in "bpf_jit.h"!
407 */
408 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
409 {
410 if (jit->seen & SEEN_TAIL_CALL) {
411 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
412 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
413 } else {
414 /* j tail_call_start: NOP if no tail calls are used */
415 EMIT4_PCREL(0xa7f40000, 6);
416 _EMIT2(0);
417 }
418 /* Tail calls have to skip above initialization */
419 jit->tail_call_start = jit->prg;
420 /* Save registers */
421 save_restore_regs(jit, REGS_SAVE, stack_depth);
422 /* Setup literal pool */
423 if (jit->seen & SEEN_LITERAL) {
424 /* basr %r13,0 */
425 EMIT2(0x0d00, REG_L, REG_0);
426 jit->base_ip = jit->prg;
427 }
428 /* Setup stack and backchain */
429 if (jit->seen & SEEN_STACK) {
430 if (jit->seen & SEEN_FUNC)
431 /* lgr %w1,%r15 (backchain) */
432 EMIT4(0xb9040000, REG_W1, REG_15);
433 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
434 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
435 /* aghi %r15,-STK_OFF */
436 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
437 if (jit->seen & SEEN_FUNC)
438 /* stg %w1,152(%r15) (backchain) */
439 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
440 REG_15, 152);
441 }
442 }
443
444 /*
445 * Function epilogue
446 */
447 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
448 {
449 /* Return 0 */
450 if (jit->seen & SEEN_RET0) {
451 jit->ret0_ip = jit->prg;
452 /* lghi %b0,0 */
453 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
454 }
455 jit->exit_ip = jit->prg;
456 /* Load exit code: lgr %r2,%b0 */
457 EMIT4(0xb9040000, REG_2, BPF_REG_0);
458 /* Restore registers */
459 save_restore_regs(jit, REGS_RESTORE, stack_depth);
460 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
461 jit->r14_thunk_ip = jit->prg;
462 /* Generate __s390_indirect_jump_r14 thunk */
463 if (test_facility(35)) {
464 /* exrl %r0,.+10 */
465 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
466 } else {
467 /* larl %r1,.+14 */
468 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
469 /* ex 0,0(%r1) */
470 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
471 }
472 /* j . */
473 EMIT4_PCREL(0xa7f40000, 0);
474 }
475 /* br %r14 */
476 _EMIT2(0x07fe);
477
478 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
479 (jit->seen & SEEN_FUNC)) {
480 jit->r1_thunk_ip = jit->prg;
481 /* Generate __s390_indirect_jump_r1 thunk */
482 if (test_facility(35)) {
483 /* exrl %r0,.+10 */
484 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
485 /* j . */
486 EMIT4_PCREL(0xa7f40000, 0);
487 /* br %r1 */
488 _EMIT2(0x07f1);
489 } else {
490 /* ex 0,S390_lowcore.br_r1_tampoline */
491 EMIT4_DISP(0x44000000, REG_0, REG_0,
492 offsetof(struct lowcore, br_r1_trampoline));
493 /* j . */
494 EMIT4_PCREL(0xa7f40000, 0);
495 }
496 }
497 }
498
499 /*
500 * Compile one eBPF instruction into s390x code
501 *
502 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
503 * stack space for the large switch statement.
504 */
505 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
506 {
507 struct bpf_insn *insn = &fp->insnsi[i];
508 int jmp_off, last, insn_count = 1;
509 u32 dst_reg = insn->dst_reg;
510 u32 src_reg = insn->src_reg;
511 u32 *addrs = jit->addrs;
512 s32 imm = insn->imm;
513 s16 off = insn->off;
514 unsigned int mask;
515
516 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
517 jit->seen |= SEEN_REG_AX;
518 switch (insn->code) {
519 /*
520 * BPF_MOV
521 */
522 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
523 /* llgfr %dst,%src */
524 EMIT4(0xb9160000, dst_reg, src_reg);
525 if (insn_is_zext(&insn[1]))
526 insn_count = 2;
527 break;
528 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
529 /* lgr %dst,%src */
530 EMIT4(0xb9040000, dst_reg, src_reg);
531 break;
532 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
533 /* llilf %dst,imm */
534 EMIT6_IMM(0xc00f0000, dst_reg, imm);
535 if (insn_is_zext(&insn[1]))
536 insn_count = 2;
537 break;
538 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
539 /* lgfi %dst,imm */
540 EMIT6_IMM(0xc0010000, dst_reg, imm);
541 break;
542 /*
543 * BPF_LD 64
544 */
545 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
546 {
547 /* 16 byte instruction that uses two 'struct bpf_insn' */
548 u64 imm64;
549
550 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
551 /* lg %dst,<d(imm)>(%l) */
552 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
553 EMIT_CONST_U64(imm64));
554 insn_count = 2;
555 break;
556 }
557 /*
558 * BPF_ADD
559 */
560 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
561 /* ar %dst,%src */
562 EMIT2(0x1a00, dst_reg, src_reg);
563 EMIT_ZERO(dst_reg);
564 break;
565 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
566 /* agr %dst,%src */
567 EMIT4(0xb9080000, dst_reg, src_reg);
568 break;
569 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
570 if (!imm)
571 break;
572 /* alfi %dst,imm */
573 EMIT6_IMM(0xc20b0000, dst_reg, imm);
574 EMIT_ZERO(dst_reg);
575 break;
576 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
577 if (!imm)
578 break;
579 /* agfi %dst,imm */
580 EMIT6_IMM(0xc2080000, dst_reg, imm);
581 break;
582 /*
583 * BPF_SUB
584 */
585 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
586 /* sr %dst,%src */
587 EMIT2(0x1b00, dst_reg, src_reg);
588 EMIT_ZERO(dst_reg);
589 break;
590 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
591 /* sgr %dst,%src */
592 EMIT4(0xb9090000, dst_reg, src_reg);
593 break;
594 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
595 if (!imm)
596 break;
597 /* alfi %dst,-imm */
598 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
599 EMIT_ZERO(dst_reg);
600 break;
601 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
602 if (!imm)
603 break;
604 /* agfi %dst,-imm */
605 EMIT6_IMM(0xc2080000, dst_reg, -imm);
606 break;
607 /*
608 * BPF_MUL
609 */
610 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
611 /* msr %dst,%src */
612 EMIT4(0xb2520000, dst_reg, src_reg);
613 EMIT_ZERO(dst_reg);
614 break;
615 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
616 /* msgr %dst,%src */
617 EMIT4(0xb90c0000, dst_reg, src_reg);
618 break;
619 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
620 if (imm == 1)
621 break;
622 /* msfi %r5,imm */
623 EMIT6_IMM(0xc2010000, dst_reg, imm);
624 EMIT_ZERO(dst_reg);
625 break;
626 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
627 if (imm == 1)
628 break;
629 /* msgfi %dst,imm */
630 EMIT6_IMM(0xc2000000, dst_reg, imm);
631 break;
632 /*
633 * BPF_DIV / BPF_MOD
634 */
635 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
636 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
637 {
638 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
639
640 /* lhi %w0,0 */
641 EMIT4_IMM(0xa7080000, REG_W0, 0);
642 /* lr %w1,%dst */
643 EMIT2(0x1800, REG_W1, dst_reg);
644 /* dlr %w0,%src */
645 EMIT4(0xb9970000, REG_W0, src_reg);
646 /* llgfr %dst,%rc */
647 EMIT4(0xb9160000, dst_reg, rc_reg);
648 if (insn_is_zext(&insn[1]))
649 insn_count = 2;
650 break;
651 }
652 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
653 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
654 {
655 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
656
657 /* lghi %w0,0 */
658 EMIT4_IMM(0xa7090000, REG_W0, 0);
659 /* lgr %w1,%dst */
660 EMIT4(0xb9040000, REG_W1, dst_reg);
661 /* dlgr %w0,%dst */
662 EMIT4(0xb9870000, REG_W0, src_reg);
663 /* lgr %dst,%rc */
664 EMIT4(0xb9040000, dst_reg, rc_reg);
665 break;
666 }
667 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
668 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
669 {
670 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
671
672 if (imm == 1) {
673 if (BPF_OP(insn->code) == BPF_MOD)
674 /* lhgi %dst,0 */
675 EMIT4_IMM(0xa7090000, dst_reg, 0);
676 break;
677 }
678 /* lhi %w0,0 */
679 EMIT4_IMM(0xa7080000, REG_W0, 0);
680 /* lr %w1,%dst */
681 EMIT2(0x1800, REG_W1, dst_reg);
682 /* dl %w0,<d(imm)>(%l) */
683 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
684 EMIT_CONST_U32(imm));
685 /* llgfr %dst,%rc */
686 EMIT4(0xb9160000, dst_reg, rc_reg);
687 if (insn_is_zext(&insn[1]))
688 insn_count = 2;
689 break;
690 }
691 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
692 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
693 {
694 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
695
696 if (imm == 1) {
697 if (BPF_OP(insn->code) == BPF_MOD)
698 /* lhgi %dst,0 */
699 EMIT4_IMM(0xa7090000, dst_reg, 0);
700 break;
701 }
702 /* lghi %w0,0 */
703 EMIT4_IMM(0xa7090000, REG_W0, 0);
704 /* lgr %w1,%dst */
705 EMIT4(0xb9040000, REG_W1, dst_reg);
706 /* dlg %w0,<d(imm)>(%l) */
707 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
708 EMIT_CONST_U64(imm));
709 /* lgr %dst,%rc */
710 EMIT4(0xb9040000, dst_reg, rc_reg);
711 break;
712 }
713 /*
714 * BPF_AND
715 */
716 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
717 /* nr %dst,%src */
718 EMIT2(0x1400, dst_reg, src_reg);
719 EMIT_ZERO(dst_reg);
720 break;
721 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
722 /* ngr %dst,%src */
723 EMIT4(0xb9800000, dst_reg, src_reg);
724 break;
725 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
726 /* nilf %dst,imm */
727 EMIT6_IMM(0xc00b0000, dst_reg, imm);
728 EMIT_ZERO(dst_reg);
729 break;
730 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
731 /* ng %dst,<d(imm)>(%l) */
732 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
733 EMIT_CONST_U64(imm));
734 break;
735 /*
736 * BPF_OR
737 */
738 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
739 /* or %dst,%src */
740 EMIT2(0x1600, dst_reg, src_reg);
741 EMIT_ZERO(dst_reg);
742 break;
743 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
744 /* ogr %dst,%src */
745 EMIT4(0xb9810000, dst_reg, src_reg);
746 break;
747 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
748 /* oilf %dst,imm */
749 EMIT6_IMM(0xc00d0000, dst_reg, imm);
750 EMIT_ZERO(dst_reg);
751 break;
752 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
753 /* og %dst,<d(imm)>(%l) */
754 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
755 EMIT_CONST_U64(imm));
756 break;
757 /*
758 * BPF_XOR
759 */
760 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
761 /* xr %dst,%src */
762 EMIT2(0x1700, dst_reg, src_reg);
763 EMIT_ZERO(dst_reg);
764 break;
765 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
766 /* xgr %dst,%src */
767 EMIT4(0xb9820000, dst_reg, src_reg);
768 break;
769 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
770 if (!imm)
771 break;
772 /* xilf %dst,imm */
773 EMIT6_IMM(0xc0070000, dst_reg, imm);
774 EMIT_ZERO(dst_reg);
775 break;
776 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
777 /* xg %dst,<d(imm)>(%l) */
778 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
779 EMIT_CONST_U64(imm));
780 break;
781 /*
782 * BPF_LSH
783 */
784 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
785 /* sll %dst,0(%src) */
786 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
787 EMIT_ZERO(dst_reg);
788 break;
789 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
790 /* sllg %dst,%dst,0(%src) */
791 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
792 break;
793 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
794 if (imm == 0)
795 break;
796 /* sll %dst,imm(%r0) */
797 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
798 EMIT_ZERO(dst_reg);
799 break;
800 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
801 if (imm == 0)
802 break;
803 /* sllg %dst,%dst,imm(%r0) */
804 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
805 break;
806 /*
807 * BPF_RSH
808 */
809 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
810 /* srl %dst,0(%src) */
811 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
812 EMIT_ZERO(dst_reg);
813 break;
814 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
815 /* srlg %dst,%dst,0(%src) */
816 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
817 break;
818 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
819 if (imm == 0)
820 break;
821 /* srl %dst,imm(%r0) */
822 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
823 EMIT_ZERO(dst_reg);
824 break;
825 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
826 if (imm == 0)
827 break;
828 /* srlg %dst,%dst,imm(%r0) */
829 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
830 break;
831 /*
832 * BPF_ARSH
833 */
834 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
835 /* sra %dst,%dst,0(%src) */
836 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
837 EMIT_ZERO(dst_reg);
838 break;
839 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
840 /* srag %dst,%dst,0(%src) */
841 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
842 break;
843 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
844 if (imm == 0)
845 break;
846 /* sra %dst,imm(%r0) */
847 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
848 EMIT_ZERO(dst_reg);
849 break;
850 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
851 if (imm == 0)
852 break;
853 /* srag %dst,%dst,imm(%r0) */
854 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
855 break;
856 /*
857 * BPF_NEG
858 */
859 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
860 /* lcr %dst,%dst */
861 EMIT2(0x1300, dst_reg, dst_reg);
862 EMIT_ZERO(dst_reg);
863 break;
864 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
865 /* lcgr %dst,%dst */
866 EMIT4(0xb9130000, dst_reg, dst_reg);
867 break;
868 /*
869 * BPF_FROM_BE/LE
870 */
871 case BPF_ALU | BPF_END | BPF_FROM_BE:
872 /* s390 is big endian, therefore only clear high order bytes */
873 switch (imm) {
874 case 16: /* dst = (u16) cpu_to_be16(dst) */
875 /* llghr %dst,%dst */
876 EMIT4(0xb9850000, dst_reg, dst_reg);
877 if (insn_is_zext(&insn[1]))
878 insn_count = 2;
879 break;
880 case 32: /* dst = (u32) cpu_to_be32(dst) */
881 if (!fp->aux->verifier_zext)
882 /* llgfr %dst,%dst */
883 EMIT4(0xb9160000, dst_reg, dst_reg);
884 break;
885 case 64: /* dst = (u64) cpu_to_be64(dst) */
886 break;
887 }
888 break;
889 case BPF_ALU | BPF_END | BPF_FROM_LE:
890 switch (imm) {
891 case 16: /* dst = (u16) cpu_to_le16(dst) */
892 /* lrvr %dst,%dst */
893 EMIT4(0xb91f0000, dst_reg, dst_reg);
894 /* srl %dst,16(%r0) */
895 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
896 /* llghr %dst,%dst */
897 EMIT4(0xb9850000, dst_reg, dst_reg);
898 if (insn_is_zext(&insn[1]))
899 insn_count = 2;
900 break;
901 case 32: /* dst = (u32) cpu_to_le32(dst) */
902 /* lrvr %dst,%dst */
903 EMIT4(0xb91f0000, dst_reg, dst_reg);
904 if (!fp->aux->verifier_zext)
905 /* llgfr %dst,%dst */
906 EMIT4(0xb9160000, dst_reg, dst_reg);
907 break;
908 case 64: /* dst = (u64) cpu_to_le64(dst) */
909 /* lrvgr %dst,%dst */
910 EMIT4(0xb90f0000, dst_reg, dst_reg);
911 break;
912 }
913 break;
914 /*
915 * BPF_ST(X)
916 */
917 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
918 /* stcy %src,off(%dst) */
919 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
920 jit->seen |= SEEN_MEM;
921 break;
922 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
923 /* sthy %src,off(%dst) */
924 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
925 jit->seen |= SEEN_MEM;
926 break;
927 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
928 /* sty %src,off(%dst) */
929 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
930 jit->seen |= SEEN_MEM;
931 break;
932 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
933 /* stg %src,off(%dst) */
934 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
935 jit->seen |= SEEN_MEM;
936 break;
937 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
938 /* lhi %w0,imm */
939 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
940 /* stcy %w0,off(dst) */
941 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
942 jit->seen |= SEEN_MEM;
943 break;
944 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
945 /* lhi %w0,imm */
946 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
947 /* sthy %w0,off(dst) */
948 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
949 jit->seen |= SEEN_MEM;
950 break;
951 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
952 /* llilf %w0,imm */
953 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
954 /* sty %w0,off(%dst) */
955 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
956 jit->seen |= SEEN_MEM;
957 break;
958 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
959 /* lgfi %w0,imm */
960 EMIT6_IMM(0xc0010000, REG_W0, imm);
961 /* stg %w0,off(%dst) */
962 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
963 jit->seen |= SEEN_MEM;
964 break;
965 /*
966 * BPF_STX XADD (atomic_add)
967 */
968 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
969 /* laal %w0,%src,off(%dst) */
970 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
971 dst_reg, off);
972 jit->seen |= SEEN_MEM;
973 break;
974 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
975 /* laalg %w0,%src,off(%dst) */
976 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
977 dst_reg, off);
978 jit->seen |= SEEN_MEM;
979 break;
980 /*
981 * BPF_LDX
982 */
983 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
984 /* llgc %dst,0(off,%src) */
985 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
986 jit->seen |= SEEN_MEM;
987 if (insn_is_zext(&insn[1]))
988 insn_count = 2;
989 break;
990 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
991 /* llgh %dst,0(off,%src) */
992 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
993 jit->seen |= SEEN_MEM;
994 if (insn_is_zext(&insn[1]))
995 insn_count = 2;
996 break;
997 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
998 /* llgf %dst,off(%src) */
999 jit->seen |= SEEN_MEM;
1000 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1001 if (insn_is_zext(&insn[1]))
1002 insn_count = 2;
1003 break;
1004 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1005 /* lg %dst,0(off,%src) */
1006 jit->seen |= SEEN_MEM;
1007 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1008 break;
1009 /*
1010 * BPF_JMP / CALL
1011 */
1012 case BPF_JMP | BPF_CALL:
1013 {
1014 /*
1015 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1016 */
1017 const u64 func = (u64)__bpf_call_base + imm;
1018
1019 REG_SET_SEEN(BPF_REG_5);
1020 jit->seen |= SEEN_FUNC;
1021 /* lg %w1,<d(imm)>(%l) */
1022 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1023 EMIT_CONST_U64(func));
1024 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1025 /* brasl %r14,__s390_indirect_jump_r1 */
1026 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1027 } else {
1028 /* basr %r14,%w1 */
1029 EMIT2(0x0d00, REG_14, REG_W1);
1030 }
1031 /* lgr %b0,%r2: load return value into %b0 */
1032 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1033 break;
1034 }
1035 case BPF_JMP | BPF_TAIL_CALL:
1036 /*
1037 * Implicit input:
1038 * B1: pointer to ctx
1039 * B2: pointer to bpf_array
1040 * B3: index in bpf_array
1041 */
1042 jit->seen |= SEEN_TAIL_CALL;
1043
1044 /*
1045 * if (index >= array->map.max_entries)
1046 * goto out;
1047 */
1048
1049 /* llgf %w1,map.max_entries(%b2) */
1050 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1051 offsetof(struct bpf_array, map.max_entries));
1052 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1053 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
1054 REG_W1, 0, 0xa);
1055
1056 /*
1057 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1058 * goto out;
1059 */
1060
1061 if (jit->seen & SEEN_STACK)
1062 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth;
1063 else
1064 off = STK_OFF_TCCNT;
1065 /* lhi %w0,1 */
1066 EMIT4_IMM(0xa7080000, REG_W0, 1);
1067 /* laal %w1,%w0,off(%r15) */
1068 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1069 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1070 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1071 MAX_TAIL_CALL_CNT, 0, 0x2);
1072
1073 /*
1074 * prog = array->ptrs[index];
1075 * if (prog == NULL)
1076 * goto out;
1077 */
1078
1079 /* sllg %r1,%b3,3: %r1 = index * 8 */
1080 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
1081 /* lg %r1,prog(%b2,%r1) */
1082 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1083 REG_1, offsetof(struct bpf_array, ptrs));
1084 /* clgij %r1,0,0x8,label0 */
1085 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1086
1087 /*
1088 * Restore registers before calling function
1089 */
1090 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth);
1091
1092 /*
1093 * goto *(prog->bpf_func + tail_call_start);
1094 */
1095
1096 /* lg %r1,bpf_func(%r1) */
1097 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1098 offsetof(struct bpf_prog, bpf_func));
1099 /* bc 0xf,tail_call_start(%r1) */
1100 _EMIT4(0x47f01000 + jit->tail_call_start);
1101 /* out: */
1102 jit->labels[0] = jit->prg;
1103 break;
1104 case BPF_JMP | BPF_EXIT: /* return b0 */
1105 last = (i == fp->len - 1) ? 1 : 0;
1106 if (last && !(jit->seen & SEEN_RET0))
1107 break;
1108 /* j <exit> */
1109 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1110 break;
1111 /*
1112 * Branch relative (number of skipped instructions) to offset on
1113 * condition.
1114 *
1115 * Condition code to mask mapping:
1116 *
1117 * CC | Description | Mask
1118 * ------------------------------
1119 * 0 | Operands equal | 8
1120 * 1 | First operand low | 4
1121 * 2 | First operand high | 2
1122 * 3 | Unused | 1
1123 *
1124 * For s390x relative branches: ip = ip + off_bytes
1125 * For BPF relative branches: insn = insn + off_insns + 1
1126 *
1127 * For example for s390x with offset 0 we jump to the branch
1128 * instruction itself (loop) and for BPF with offset 0 we
1129 * branch to the instruction behind the branch.
1130 */
1131 case BPF_JMP | BPF_JA: /* if (true) */
1132 mask = 0xf000; /* j */
1133 goto branch_oc;
1134 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1135 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1136 mask = 0x2000; /* jh */
1137 goto branch_ks;
1138 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1139 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1140 mask = 0x4000; /* jl */
1141 goto branch_ks;
1142 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1143 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1144 mask = 0xa000; /* jhe */
1145 goto branch_ks;
1146 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1147 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1148 mask = 0xc000; /* jle */
1149 goto branch_ks;
1150 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1151 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1152 mask = 0x2000; /* jh */
1153 goto branch_ku;
1154 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1155 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1156 mask = 0x4000; /* jl */
1157 goto branch_ku;
1158 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1159 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1160 mask = 0xa000; /* jhe */
1161 goto branch_ku;
1162 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1163 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1164 mask = 0xc000; /* jle */
1165 goto branch_ku;
1166 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1167 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1168 mask = 0x7000; /* jne */
1169 goto branch_ku;
1170 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1171 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1172 mask = 0x8000; /* je */
1173 goto branch_ku;
1174 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1175 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1176 mask = 0x7000; /* jnz */
1177 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1178 /* llilf %w1,imm (load zero extend imm) */
1179 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1180 /* nr %w1,%dst */
1181 EMIT2(0x1400, REG_W1, dst_reg);
1182 } else {
1183 /* lgfi %w1,imm (load sign extend imm) */
1184 EMIT6_IMM(0xc0010000, REG_W1, imm);
1185 /* ngr %w1,%dst */
1186 EMIT4(0xb9800000, REG_W1, dst_reg);
1187 }
1188 goto branch_oc;
1189
1190 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1191 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1192 mask = 0x2000; /* jh */
1193 goto branch_xs;
1194 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1195 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1196 mask = 0x4000; /* jl */
1197 goto branch_xs;
1198 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1199 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1200 mask = 0xa000; /* jhe */
1201 goto branch_xs;
1202 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1203 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1204 mask = 0xc000; /* jle */
1205 goto branch_xs;
1206 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1207 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1208 mask = 0x2000; /* jh */
1209 goto branch_xu;
1210 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1211 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1212 mask = 0x4000; /* jl */
1213 goto branch_xu;
1214 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1215 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1216 mask = 0xa000; /* jhe */
1217 goto branch_xu;
1218 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1219 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1220 mask = 0xc000; /* jle */
1221 goto branch_xu;
1222 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1223 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1224 mask = 0x7000; /* jne */
1225 goto branch_xu;
1226 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1227 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1228 mask = 0x8000; /* je */
1229 goto branch_xu;
1230 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1231 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1232 {
1233 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1234
1235 mask = 0x7000; /* jnz */
1236 /* nrk or ngrk %w1,%dst,%src */
1237 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1238 REG_W1, dst_reg, src_reg);
1239 goto branch_oc;
1240 branch_ks:
1241 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1242 /* lgfi %w1,imm (load sign extend imm) */
1243 EMIT6_IMM(0xc0010000, REG_W1, imm);
1244 /* crj or cgrj %dst,%w1,mask,off */
1245 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1246 dst_reg, REG_W1, i, off, mask);
1247 break;
1248 branch_ku:
1249 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1250 /* lgfi %w1,imm (load sign extend imm) */
1251 EMIT6_IMM(0xc0010000, REG_W1, imm);
1252 /* clrj or clgrj %dst,%w1,mask,off */
1253 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1254 dst_reg, REG_W1, i, off, mask);
1255 break;
1256 branch_xs:
1257 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1258 /* crj or cgrj %dst,%src,mask,off */
1259 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1260 dst_reg, src_reg, i, off, mask);
1261 break;
1262 branch_xu:
1263 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1264 /* clrj or clgrj %dst,%src,mask,off */
1265 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1266 dst_reg, src_reg, i, off, mask);
1267 break;
1268 branch_oc:
1269 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1270 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1271 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1272 break;
1273 }
1274 default: /* too complex, give up */
1275 pr_err("Unknown opcode %02x\n", insn->code);
1276 return -1;
1277 }
1278 return insn_count;
1279 }
1280
1281 /*
1282 * Compile eBPF program into s390x code
1283 */
1284 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1285 {
1286 int i, insn_count;
1287
1288 jit->lit = jit->lit_start;
1289 jit->prg = 0;
1290
1291 bpf_jit_prologue(jit, fp->aux->stack_depth);
1292 for (i = 0; i < fp->len; i += insn_count) {
1293 insn_count = bpf_jit_insn(jit, fp, i);
1294 if (insn_count < 0)
1295 return -1;
1296 /* Next instruction address */
1297 jit->addrs[i + insn_count] = jit->prg;
1298 }
1299 bpf_jit_epilogue(jit, fp->aux->stack_depth);
1300
1301 jit->lit_start = jit->prg;
1302 jit->size = jit->lit;
1303 jit->size_prg = jit->prg;
1304 return 0;
1305 }
1306
1307 bool bpf_jit_needs_zext(void)
1308 {
1309 return true;
1310 }
1311
1312 /*
1313 * Compile eBPF program "fp"
1314 */
1315 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1316 {
1317 struct bpf_prog *tmp, *orig_fp = fp;
1318 struct bpf_binary_header *header;
1319 bool tmp_blinded = false;
1320 struct bpf_jit jit;
1321 int pass;
1322
1323 if (!fp->jit_requested)
1324 return orig_fp;
1325
1326 tmp = bpf_jit_blind_constants(fp);
1327 /*
1328 * If blinding was requested and we failed during blinding,
1329 * we must fall back to the interpreter.
1330 */
1331 if (IS_ERR(tmp))
1332 return orig_fp;
1333 if (tmp != fp) {
1334 tmp_blinded = true;
1335 fp = tmp;
1336 }
1337
1338 memset(&jit, 0, sizeof(jit));
1339 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1340 if (jit.addrs == NULL) {
1341 fp = orig_fp;
1342 goto out;
1343 }
1344 /*
1345 * Three initial passes:
1346 * - 1/2: Determine clobbered registers
1347 * - 3: Calculate program size and addrs arrray
1348 */
1349 for (pass = 1; pass <= 3; pass++) {
1350 if (bpf_jit_prog(&jit, fp)) {
1351 fp = orig_fp;
1352 goto free_addrs;
1353 }
1354 }
1355 /*
1356 * Final pass: Allocate and generate program
1357 */
1358 if (jit.size >= BPF_SIZE_MAX) {
1359 fp = orig_fp;
1360 goto free_addrs;
1361 }
1362 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1363 if (!header) {
1364 fp = orig_fp;
1365 goto free_addrs;
1366 }
1367 if (bpf_jit_prog(&jit, fp)) {
1368 bpf_jit_binary_free(header);
1369 fp = orig_fp;
1370 goto free_addrs;
1371 }
1372 if (bpf_jit_enable > 1) {
1373 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1374 print_fn_code(jit.prg_buf, jit.size_prg);
1375 }
1376 bpf_jit_binary_lock_ro(header);
1377 fp->bpf_func = (void *) jit.prg_buf;
1378 fp->jited = 1;
1379 fp->jited_len = jit.size;
1380 free_addrs:
1381 kfree(jit.addrs);
1382 out:
1383 if (tmp_blinded)
1384 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1385 tmp : orig_fp);
1386 return fp;
1387 }
Linux with added FPC-III support