drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 IBM Corp.
   4  */
   5 #include <linux/bitops.h>
   6 #include <linux/init.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mfd/syscon.h>
  10 #include <linux/mutex.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pinctrl/pinctrl.h>
  14 #include <linux/pinctrl/pinmux.h>
  15 #include <linux/pinctrl/pinconf.h>
  16 #include <linux/pinctrl/pinconf-generic.h>
  17 #include <linux/string.h>
  18 #include <linux/types.h>
  19
  20 #include "../core.h"
  21 #include "../pinctrl-utils.h"
  22 #include "pinctrl-aspeed.h"
  23
  24 /*
  25  * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
  26  * references registers by the device/offset mnemonic. The register macros
  27  * below are named the same way to ease transcription and verification (as
  28  * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
  29  * reference registers beyond those dedicated to pinmux, such as the system
  30  * reset control and MAC clock configuration registers. The AST2500 goes a step
  31  * further and references registers in the graphics IP block.
  32  */
  33 #define SCU2C           0x2C /* Misc. Control Register */
  34 #define SCU3C           0x3C /* System Reset Control/Status Register */
  35 #define SCU48           0x48 /* MAC Interface Clock Delay Setting */
  36 #define HW_STRAP1       0x70 /* AST2400 strapping is 33 bits, is split */
  37 #define HW_REVISION_ID  0x7C /* Silicon revision ID register */
  38 #define SCU80           0x80 /* Multi-function Pin Control #1 */
  39 #define SCU84           0x84 /* Multi-function Pin Control #2 */
  40 #define SCU88           0x88 /* Multi-function Pin Control #3 */
  41 #define SCU8C           0x8C /* Multi-function Pin Control #4 */
  42 #define SCU90           0x90 /* Multi-function Pin Control #5 */
  43 #define SCU94           0x94 /* Multi-function Pin Control #6 */
  44 #define SCUA0           0xA0 /* Multi-function Pin Control #7 */
  45 #define SCUA4           0xA4 /* Multi-function Pin Control #8 */
  46 #define SCUA8           0xA8 /* Multi-function Pin Control #9 */
  47 #define SCUAC           0xAC /* Multi-function Pin Control #10 */
  48 #define HW_STRAP2       0xD0 /* Strapping */
  49
  50 #define ASPEED_G5_NR_PINS 236
  51
  52 #define COND1           { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
  53 #define COND2           { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
  54
  55 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
  56 #define LHCR0           0x20
  57 #define GFX064          0x64
  58
  59 #define B14 0
  60 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
  61
  62 #define D14 1
  63 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
  64
  65 #define D13 2
  66 SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
  67 SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
  68 MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
  69 FUNC_GROUP_DECL(SPI1CS1, D13);
  70 FUNC_GROUP_DECL(TIMER3, D13);
  71
  72 #define E13 3
  73 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
  74
  75 #define I2C9_DESC       SIG_DESC_SET(SCU90, 22)
  76
  77 #define C14 4
  78 SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
  79 SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
  80 MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
  81
  82 FUNC_GROUP_DECL(TIMER5, C14);
  83
  84 #define A13 5
  85 SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
  86 SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
  87 MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
  88
  89 FUNC_GROUP_DECL(TIMER6, A13);
  90
  91 FUNC_GROUP_DECL(I2C9, C14, A13);
  92
  93 #define MDIO2_DESC      SIG_DESC_SET(SCU90, 2)
  94
  95 #define C13 6
  96 SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1);
  97 SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
  98 MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7);
  99
 100 FUNC_GROUP_DECL(TIMER7, C13);
 101
 102 #define B13 7
 103 SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1);
 104 SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
 105 MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8);
 106
 107 FUNC_GROUP_DECL(TIMER8, B13);
 108
 109 FUNC_GROUP_DECL(MDIO2, C13, B13);
 110
 111 #define K19 8
 112 GPIO_PIN_DECL(K19, GPIOB0);
 113
 114 #define L19 9
 115 GPIO_PIN_DECL(L19, GPIOB1);
 116
 117 #define L18 10
 118 GPIO_PIN_DECL(L18, GPIOB2);
 119
 120 #define K18 11
 121 GPIO_PIN_DECL(K18, GPIOB3);
 122
 123 #define J20 12
 124 SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
 125
 126 #define H21 13
 127 #define H21_DESC        SIG_DESC_SET(SCU80, 13)
 128 SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC);
 129 SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC);
 130 MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
 131 FUNC_GROUP_DECL(LPCPD, H21);
 132 FUNC_GROUP_DECL(LPCSMI, H21);
 133
 134 #define H22 14
 135 SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
 136
 137 #define H20 15
 138 GPIO_PIN_DECL(H20, GPIOB7);
 139
 140 #define SD1_DESC        SIG_DESC_SET(SCU90, 0)
 141
 142 #define C12 16
 143 #define I2C10_DESC      SIG_DESC_SET(SCU90, 23)
 144 SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
 145 SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
 146 MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
 147
 148 #define A12 17
 149 SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
 150 SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
 151 MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
 152
 153 FUNC_GROUP_DECL(I2C10, C12, A12);
 154
 155 #define B12 18
 156 #define I2C11_DESC      SIG_DESC_SET(SCU90, 24)
 157 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
 158 SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
 159 MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
 160
 161 #define D9  19
 162 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
 163 SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
 164 MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
 165
 166 FUNC_GROUP_DECL(I2C11, B12, D9);
 167
 168 #define D10 20
 169 #define I2C12_DESC      SIG_DESC_SET(SCU90, 25)
 170 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
 171 SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
 172 MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
 173
 174 #define E12 21
 175 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
 176 SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
 177 MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
 178
 179 FUNC_GROUP_DECL(I2C12, D10, E12);
 180
 181 #define C11 22
 182 #define I2C13_DESC      SIG_DESC_SET(SCU90, 26)
 183 SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
 184 SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
 185 MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
 186
 187 #define B11 23
 188 SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
 189 SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
 190 MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
 191
 192 FUNC_GROUP_DECL(I2C13, C11, B11);
 193 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
 194
 195 #define SD2_DESC        SIG_DESC_SET(SCU90, 1)
 196 #define GPID0_DESC      SIG_DESC_SET(SCU8C, 8)
 197 #define GPID_DESC       SIG_DESC_SET(HW_STRAP1, 21)
 198
 199 #define F19 24
 200 SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
 201 SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
 202 SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
 203 SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
 204 MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
 205
 206 #define E21 25
 207 SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
 208 SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
 209 SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
 210 SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
 211 MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
 212
 213 FUNC_GROUP_DECL(GPID0, F19, E21);
 214
 215 #define GPID2_DESC      SIG_DESC_SET(SCU8C, 9)
 216
 217 #define F20 26
 218 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
 219 SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
 220 SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
 221 SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
 222 MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
 223
 224 #define D20 27
 225 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
 226 SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
 227 SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
 228 SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
 229 MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
 230
 231 FUNC_GROUP_DECL(GPID2, F20, D20);
 232
 233 #define GPID4_DESC      SIG_DESC_SET(SCU8C, 10)
 234
 235 #define D21 28
 236 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
 237 SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
 238 SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
 239 SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
 240 MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
 241
 242 #define E20 29
 243 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
 244 SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
 245 SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
 246 SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
 247 MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
 248
 249 FUNC_GROUP_DECL(GPID4, D21, E20);
 250
 251 #define GPID6_DESC      SIG_DESC_SET(SCU8C, 11)
 252
 253 #define G18 30
 254 SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
 255 SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
 256 SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
 257 SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
 258 MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
 259
 260 #define C21 31
 261 SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
 262 SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
 263 SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
 264 SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
 265 MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
 266
 267 FUNC_GROUP_DECL(GPID6, G18, C21);
 268 FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
 269
 270 #define GPIE_DESC       SIG_DESC_SET(HW_STRAP1, 22)
 271 #define GPIE0_DESC      SIG_DESC_SET(SCU8C, 12)
 272
 273 #define B20 32
 274 SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
 275 SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
 276 SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
 277 SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
 278 MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
 279 FUNC_GROUP_DECL(NCTS3, B20);
 280
 281 #define C20 33
 282 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
 283 SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
 284 SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
 285 SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
 286 MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
 287 FUNC_GROUP_DECL(NDCD3, C20);
 288
 289 FUNC_GROUP_DECL(GPIE0, B20, C20);
 290
 291 #define GPIE2_DESC      SIG_DESC_SET(SCU8C, 13)
 292
 293 #define F18 34
 294 SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
 295 SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
 296 SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
 297 SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
 298 MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
 299 FUNC_GROUP_DECL(NDSR3, F18);
 300
 301
 302 #define F17 35
 303 SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
 304 SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
 305 SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
 306 SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
 307 MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
 308 FUNC_GROUP_DECL(NRI3, F17);
 309
 310 FUNC_GROUP_DECL(GPIE2, F18, F17);
 311
 312 #define GPIE4_DESC      SIG_DESC_SET(SCU8C, 14)
 313
 314 #define E18 36
 315 SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
 316 SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
 317 SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
 318 SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
 319 MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
 320 FUNC_GROUP_DECL(NDTR3, E18);
 321
 322 #define D19 37
 323 SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
 324 SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
 325 SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
 326 SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
 327 MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
 328 FUNC_GROUP_DECL(NRTS3, D19);
 329
 330 FUNC_GROUP_DECL(GPIE4, E18, D19);
 331
 332 #define GPIE6_DESC      SIG_DESC_SET(SCU8C, 15)
 333
 334 #define A20 38
 335 SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
 336 SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
 337 SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
 338 SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
 339 MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
 340 FUNC_GROUP_DECL(TXD3, A20);
 341
 342 #define B19 39
 343 SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
 344 SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
 345 SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
 346 SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
 347 MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
 348 FUNC_GROUP_DECL(RXD3, B19);
 349
 350 FUNC_GROUP_DECL(GPIE6, A20, B19);
 351
 352 #define LPCHC_DESC      SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
 353 #define LPCPLUS_DESC    SIG_DESC_SET(SCU90, 30)
 354
 355 #define J19 40
 356 SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
 357 SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
 358 SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
 359 SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
 360 MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
 361 FUNC_GROUP_DECL(NCTS4, J19);
 362
 363 #define J18 41
 364 SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
 365 SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
 366 SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
 367 SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
 368 MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
 369 FUNC_GROUP_DECL(NDCD4, J18);
 370
 371 #define B22 42
 372 SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
 373 SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
 374 SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
 375 SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
 376 MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
 377 FUNC_GROUP_DECL(NDSR4, B22);
 378
 379 #define B21 43
 380 SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
 381 SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
 382 SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
 383 SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
 384 MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
 385 FUNC_GROUP_DECL(NRI4, B21);
 386
 387 #define A21 44
 388 SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
 389 SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
 390 SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
 391 SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
 392 MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
 393 FUNC_GROUP_DECL(NDTR4, A21);
 394
 395 #define H19 45
 396 SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
 397 SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
 398 SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
 399 SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
 400 MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
 401 FUNC_GROUP_DECL(NRTS4, H19);
 402
 403 #define G17 46
 404 SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
 405 SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
 406 MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
 407 FUNC_GROUP_DECL(TXD4, G17);
 408
 409 #define H18 47
 410 SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
 411 SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
 412 SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
 413 SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
 414 MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
 415 FUNC_GROUP_DECL(RXD4, H18);
 416
 417 FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
 418 FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
 419
 420 #define A19 48
 421 SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
 422 SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
 423
 424 #define E19 49
 425 SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
 426 SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
 427
 428 #define C19 50
 429 SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
 430 SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
 431
 432 #define E16 51
 433 SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
 434 SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
 435
 436 FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
 437
 438 #define SGPS2_DESC      SIG_DESC_SET(SCU94, 12)
 439
 440 #define E17 52
 441 SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
 442 SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
 443 MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
 444 FUNC_GROUP_DECL(SALT1, E17);
 445
 446 #define D16 53
 447 SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
 448 SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
 449 MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
 450 FUNC_GROUP_DECL(SALT2, D16);
 451
 452 #define D15 54
 453 SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
 454 SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
 455 MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
 456 FUNC_GROUP_DECL(SALT3, D15);
 457
 458 #define E14 55
 459 SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
 460 SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
 461 MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
 462 FUNC_GROUP_DECL(SALT4, E14);
 463
 464 FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
 465
 466 #define UART6_DESC      SIG_DESC_SET(SCU90, 7)
 467
 468 #define A18 56
 469 SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
 470 SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
 471 MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
 472
 473 #define B18 57
 474 SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
 475 SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
 476 MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
 477
 478 #define D17 58
 479 SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
 480 SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
 481 MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
 482
 483 #define C17 59
 484 SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
 485 SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
 486 MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
 487
 488 #define A17 60
 489 SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
 490 SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
 491 MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
 492
 493 #define B17 61
 494 SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
 495 SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
 496 MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
 497
 498 #define A16 62
 499 SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
 500 SS_PIN_DECL(A16, GPIOH6, TXD6);
 501
 502 #define D18 63
 503 SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
 504 SS_PIN_DECL(D18, GPIOH7, RXD6);
 505
 506 FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
 507
 508 #define SPI1_DESC \
 509         { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
 510 #define SPI1DEBUG_DESC \
 511         { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
 512 #define SPI1PASSTHRU_DESC \
 513         { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
 514
 515 #define C18 64
 516 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 517 SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 518 SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
 519 SS_PIN_DECL(C18, GPIOI0, SYSCS);
 520
 521 #define E15 65
 522 SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 523 SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 524 SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
 525 SS_PIN_DECL(E15, GPIOI1, SYSCK);
 526
 527 #define B16 66
 528 SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 529 SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 530 SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
 531 SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
 532
 533 #define C16 67
 534 SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 535 SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 536 SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
 537 SS_PIN_DECL(C16, GPIOI3, SYSMISO);
 538
 539 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
 540
 541 #define B15 68
 542 SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
 543 SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 544 SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 545 SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
 546                             SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
 547                             SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
 548 SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
 549 MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
 550
 551 #define C15 69
 552 SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
 553 SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 554 SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 555 SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
 556                             SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
 557                             SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
 558 SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
 559 MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
 560
 561 #define A14 70
 562 SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
 563 SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 564 SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 565 SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
 566                             SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
 567                             SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
 568 SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
 569 MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
 570
 571 #define A15 71
 572 SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
 573 SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
 574 SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
 575 SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
 576                             SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
 577                             SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
 578 SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
 579 MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
 580
 581 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
 582 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
 583 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
 584 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
 585
 586 #define R2 72
 587 SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
 588 SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
 589
 590 #define L2 73
 591 SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
 592 SS_PIN_DECL(L2, GPIOJ1, SGPMLD);
 593
 594 #define N3 74
 595 SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
 596 SS_PIN_DECL(N3, GPIOJ2, SGPMO);
 597
 598 #define N4 75
 599 SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
 600 SS_PIN_DECL(N4, GPIOJ3, SGPMI);
 601
 602 FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
 603
 604 #define N5 76
 605 SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
 606 SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
 607 MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
 608 FUNC_GROUP_DECL(VGAHS, N5);
 609
 610 #define R4 77
 611 SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
 612 SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
 613 MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
 614 FUNC_GROUP_DECL(VGAVS, R4);
 615
 616 #define R3 78
 617 SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
 618 SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
 619 MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
 620 FUNC_GROUP_DECL(DDCCLK, R3);
 621
 622 #define T3 79
 623 SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
 624 SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
 625 MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
 626 FUNC_GROUP_DECL(DDCDAT, T3);
 627
 628 #define I2C5_DESC       SIG_DESC_SET(SCU90, 18)
 629
 630 #define L3 80
 631 SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
 632 SS_PIN_DECL(L3, GPIOK0, SCL5);
 633
 634 #define L4 81
 635 SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
 636 SS_PIN_DECL(L4, GPIOK1, SDA5);
 637
 638 FUNC_GROUP_DECL(I2C5, L3, L4);
 639
 640 #define I2C6_DESC       SIG_DESC_SET(SCU90, 19)
 641
 642 #define L1 82
 643 SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
 644 SS_PIN_DECL(L1, GPIOK2, SCL6);
 645
 646 #define N2 83
 647 SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
 648 SS_PIN_DECL(N2, GPIOK3, SDA6);
 649
 650 FUNC_GROUP_DECL(I2C6, L1, N2);
 651
 652 #define I2C7_DESC       SIG_DESC_SET(SCU90, 20)
 653
 654 #define N1 84
 655 SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
 656 SS_PIN_DECL(N1, GPIOK4, SCL7);
 657
 658 #define P1 85
 659 SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
 660 SS_PIN_DECL(P1, GPIOK5, SDA7);
 661
 662 FUNC_GROUP_DECL(I2C7, N1, P1);
 663
 664 #define I2C8_DESC       SIG_DESC_SET(SCU90, 21)
 665
 666 #define P2 86
 667 SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
 668 SS_PIN_DECL(P2, GPIOK6, SCL8);
 669
 670 #define R1 87
 671 SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
 672 SS_PIN_DECL(R1, GPIOK7, SDA8);
 673
 674 FUNC_GROUP_DECL(I2C8, P2, R1);
 675
 676 #define T2 88
 677 SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
 678
 679 #define VPIOFF0_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
 680 #define VPIOFF1_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
 681 #define VPI24_DESC      { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
 682 #define VPIRSVD_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
 683 #define VPI_24_RSVD_DESC        SIG_DESC_SET(SCU90, 5)
 684
 685 #define T1 89
 686 #define T1_DESC         SIG_DESC_SET(SCU84, 17)
 687 SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
 688 SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
 689 MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
 690 FUNC_GROUP_DECL(NDCD1, T1);
 691
 692 #define U1 90
 693 #define U1_DESC         SIG_DESC_SET(SCU84, 18)
 694 SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
 695 SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
 696 MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
 697 FUNC_GROUP_DECL(NDSR1, U1);
 698
 699 #define U2 91
 700 #define U2_DESC         SIG_DESC_SET(SCU84, 19)
 701 SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
 702 SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
 703 MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
 704 FUNC_GROUP_DECL(NRI1, U2);
 705
 706 #define P4 92
 707 #define P4_DESC         SIG_DESC_SET(SCU84, 20)
 708 SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
 709 SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
 710 MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
 711 FUNC_GROUP_DECL(NDTR1, P4);
 712
 713 #define P3 93
 714 #define P3_DESC         SIG_DESC_SET(SCU84, 21)
 715 SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
 716 SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
 717 MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
 718 FUNC_GROUP_DECL(NRTS1, P3);
 719
 720 #define V1 94
 721 #define V1_DESC         SIG_DESC_SET(SCU84, 22)
 722 SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
 723 SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
 724 MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
 725 FUNC_GROUP_DECL(TXD1, V1);
 726
 727 #define W1 95
 728 #define W1_DESC         SIG_DESC_SET(SCU84, 23)
 729 SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
 730 SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
 731 MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
 732 FUNC_GROUP_DECL(RXD1, W1);
 733
 734 #define Y1 96
 735 #define Y1_DESC         SIG_DESC_SET(SCU84, 24)
 736 SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
 737 SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
 738 MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
 739 FUNC_GROUP_DECL(NCTS2, Y1);
 740
 741 #define AB2 97
 742 #define AB2_DESC        SIG_DESC_SET(SCU84, 25)
 743 SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
 744 SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
 745 MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
 746 FUNC_GROUP_DECL(NDCD2, AB2);
 747
 748 #define AA1 98
 749 #define AA1_DESC        SIG_DESC_SET(SCU84, 26)
 750 SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
 751 SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
 752 MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
 753 FUNC_GROUP_DECL(NDSR2, AA1);
 754
 755 #define Y2 99
 756 #define Y2_DESC         SIG_DESC_SET(SCU84, 27)
 757 SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
 758 SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
 759 MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
 760 FUNC_GROUP_DECL(NRI2, Y2);
 761
 762 #define AA2 100
 763 #define AA2_DESC        SIG_DESC_SET(SCU84, 28)
 764 SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
 765 SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
 766 MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
 767 FUNC_GROUP_DECL(NDTR2, AA2);
 768
 769 #define P5 101
 770 #define P5_DESC SIG_DESC_SET(SCU84, 29)
 771 SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
 772 SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
 773 MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
 774 FUNC_GROUP_DECL(NRTS2, P5);
 775
 776 #define R5 102
 777 #define R5_DESC SIG_DESC_SET(SCU84, 30)
 778 SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
 779 SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
 780 MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
 781 FUNC_GROUP_DECL(TXD2, R5);
 782
 783 #define T5 103
 784 #define T5_DESC SIG_DESC_SET(SCU84, 31)
 785 SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
 786 SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
 787 MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
 788 FUNC_GROUP_DECL(RXD2, T5);
 789
 790 #define V2 104
 791 #define V2_DESC         SIG_DESC_SET(SCU88, 0)
 792 SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
 793 SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
 794 MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
 795 FUNC_GROUP_DECL(PWM0, V2);
 796
 797 #define W2 105
 798 #define W2_DESC         SIG_DESC_SET(SCU88, 1)
 799 SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
 800 SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
 801 MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
 802 FUNC_GROUP_DECL(PWM1, W2);
 803
 804 #define V3 106
 805 #define V3_DESC         SIG_DESC_SET(SCU88, 2)
 806 SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
 807 SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
 808 SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
 809 SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
 810 MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
 811 FUNC_GROUP_DECL(PWM2, V3);
 812
 813 #define U3 107
 814 #define U3_DESC         SIG_DESC_SET(SCU88, 3)
 815 SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
 816 SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
 817 SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
 818 SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
 819 MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
 820 FUNC_GROUP_DECL(PWM3, U3);
 821
 822 #define W3 108
 823 #define W3_DESC         SIG_DESC_SET(SCU88, 4)
 824 SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
 825 SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
 826 SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
 827 SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
 828 MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
 829 FUNC_GROUP_DECL(PWM4, W3);
 830
 831 #define AA3 109
 832 #define AA3_DESC        SIG_DESC_SET(SCU88, 5)
 833 SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
 834 SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
 835 SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
 836 SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
 837 MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
 838 FUNC_GROUP_DECL(PWM5, AA3);
 839
 840 #define Y3 110
 841 #define Y3_DESC         SIG_DESC_SET(SCU88, 6)
 842 SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
 843 SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
 844 MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
 845 FUNC_GROUP_DECL(PWM6, Y3);
 846
 847 #define T4 111
 848 #define T4_DESC         SIG_DESC_SET(SCU88, 7)
 849 SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
 850 SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
 851 MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
 852 FUNC_GROUP_DECL(PWM7, T4);
 853
 854 #define U5 112
 855 SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
 856                           COND2);
 857 SS_PIN_DECL(U5, GPIOO0, VPIG8);
 858
 859 #define U4 113
 860 SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
 861                           COND2);
 862 SS_PIN_DECL(U4, GPIOO1, VPIG9);
 863
 864 #define V5 114
 865 SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
 866                           SIG_DESC_SET(SCU88, 10));
 867 SS_PIN_DECL(V5, GPIOO2, DASHV5);
 868
 869 #define AB4 115
 870 SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
 871                           SIG_DESC_SET(SCU88, 11));
 872 SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
 873
 874 #define AB3 116
 875 SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
 876                           COND2);
 877 SS_PIN_DECL(AB3, GPIOO4, VPIR2);
 878
 879 #define Y4 117
 880 SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
 881                           COND2);
 882 SS_PIN_DECL(Y4, GPIOO5, VPIR3);
 883
 884 #define AA4 118
 885 SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
 886                           COND2);
 887 SS_PIN_DECL(AA4, GPIOO6, VPIR4);
 888
 889 #define W4 119
 890 SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
 891                           COND2);
 892 SS_PIN_DECL(W4, GPIOO7, VPIR5);
 893
 894 #define V4 120
 895 SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
 896                           COND2);
 897 SS_PIN_DECL(V4, GPIOP0, VPIR6);
 898
 899 #define W5 121
 900 SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
 901                           COND2);
 902 SS_PIN_DECL(W5, GPIOP1, VPIR7);
 903
 904 #define AA5 122
 905 SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
 906                           COND2);
 907 SS_PIN_DECL(AA5, GPIOP2, VPIR8);
 908
 909 #define AB5 123
 910 SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
 911                           COND2);
 912 SS_PIN_DECL(AB5, GPIOP3, VPIR9);
 913
 914 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
 915                 U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
 916                 AB5);
 917
 918 #define Y6 124
 919 SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
 920                           SIG_DESC_SET(SCU88, 20));
 921 SS_PIN_DECL(Y6, GPIOP4, DASHY6);
 922
 923 #define Y5 125
 924 SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
 925                           SIG_DESC_SET(SCU88, 21));
 926 SS_PIN_DECL(Y5, GPIOP5, DASHY5);
 927
 928 #define W6 126
 929 SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
 930                           SIG_DESC_SET(SCU88, 22));
 931 SS_PIN_DECL(W6, GPIOP6, DASHW6);
 932
 933 #define V6 127
 934 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
 935                           SIG_DESC_SET(SCU88, 23));
 936 SS_PIN_DECL(V6, GPIOP7, DASHV6);
 937
 938 #define I2C3_DESC       SIG_DESC_SET(SCU90, 16)
 939
 940 #define A11 128
 941 SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
 942 SS_PIN_DECL(A11, GPIOQ0, SCL3);
 943
 944 #define A10 129
 945 SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
 946 SS_PIN_DECL(A10, GPIOQ1, SDA3);
 947
 948 FUNC_GROUP_DECL(I2C3, A11, A10);
 949
 950 #define I2C4_DESC       SIG_DESC_SET(SCU90, 17)
 951
 952 #define A9 130
 953 SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
 954 SS_PIN_DECL(A9, GPIOQ2, SCL4);
 955
 956 #define B9 131
 957 SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
 958 SS_PIN_DECL(B9, GPIOQ3, SDA4);
 959
 960 FUNC_GROUP_DECL(I2C4, A9, B9);
 961
 962 #define I2C14_DESC      SIG_DESC_SET(SCU90, 27)
 963
 964 #define N21 132
 965 SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
 966 SS_PIN_DECL(N21, GPIOQ4, SCL14);
 967
 968 #define N22 133
 969 SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
 970 SS_PIN_DECL(N22, GPIOQ5, SDA14);
 971
 972 FUNC_GROUP_DECL(I2C14, N21, N22);
 973
 974 #define B10 134
 975 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
 976
 977 #define N20 135
 978 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
 979
 980 #define AA19 136
 981 SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
 982
 983 #define T19 137
 984 SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
 985
 986 #define T17 138
 987 SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
 988
 989 #define Y19 139
 990 SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
 991
 992 #define W19 140
 993 SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
 994
 995 #define V19 141
 996 SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
 997
 998 #define D8 142
 999 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
1000 SS_PIN_DECL(D8, GPIOR6, MDC1);
1001
1002 #define E10 143
1003 SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
1004 SS_PIN_DECL(E10, GPIOR7, MDIO1);
1005
1006 FUNC_GROUP_DECL(MDIO1, D8, E10);
1007
1008 #define VPOOFF0_DESC    { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1009 #define VPO_DESC        { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1010 #define VPOOFF1_DESC    { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1011 #define VPOOFF2_DESC    { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1012
1013 #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
1014
1015 #define V20 144
1016 #define V20_DESC        SIG_DESC_SET(SCU8C, 0)
1017 SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1018 SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1019 SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1020 SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
1021                 SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
1022 SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
1023 MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
1024 FUNC_GROUP_DECL(SPI2CS1, V20);
1025
1026 #define U19 145
1027 #define U19_DESC        SIG_DESC_SET(SCU8C, 1)
1028 SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1029 SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1030 SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1031 SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
1032                 SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
1033 SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
1034 MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
1035 FUNC_GROUP_DECL(BMCINT, U19);
1036
1037 #define R18 146
1038 #define R18_DESC        SIG_DESC_SET(SCU8C, 2)
1039 SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1040 SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1041 SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1042 SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
1043                 SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
1044 SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
1045 MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
1046 FUNC_GROUP_DECL(SALT5, R18);
1047
1048 #define P18 147
1049 #define P18_DESC        SIG_DESC_SET(SCU8C, 3)
1050 SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1051 SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1052 SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1053 SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
1054                 SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
1055 SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
1056 MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
1057 FUNC_GROUP_DECL(SALT6, P18);
1058
1059 #define R19 148
1060 #define R19_DESC        SIG_DESC_SET(SCU8C, 4)
1061 SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1062 SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1063 SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1064 SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
1065                 SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
1066 SS_PIN_DECL(R19, GPIOS4, VPOB6);
1067
1068 #define W20 149
1069 #define W20_DESC        SIG_DESC_SET(SCU8C, 5)
1070 SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1071 SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1072 SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1073 SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
1074                 SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
1075 SS_PIN_DECL(W20, GPIOS5, VPOB7);
1076
1077 #define U20 150
1078 #define U20_DESC        SIG_DESC_SET(SCU8C, 6)
1079 SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1080 SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1081 SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1082 SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
1083                 SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
1084 SS_PIN_DECL(U20, GPIOS6, VPOB8);
1085
1086 #define AA20 151
1087 #define AA20_DESC       SIG_DESC_SET(SCU8C, 7)
1088 SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1089 SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1090 SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1091 SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
1092                 SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
1093 SS_PIN_DECL(AA20, GPIOS7, VPOB9);
1094
1095 /* RGMII1/RMII1 */
1096
1097 #define RMII1_DESC      SIG_DESC_BIT(HW_STRAP1, 6, 0)
1098 #define RMII2_DESC      SIG_DESC_BIT(HW_STRAP1, 7, 0)
1099
1100 #define B5 152
1101 SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
1102 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC,
1103                 SIG_DESC_SET(SCU48, 29));
1104 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
1105 MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
1106                 SIG_EXPR_LIST_PTR(RGMII1TXCK));
1107
1108 #define E9 153
1109 SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
1110 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
1111 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
1112 MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
1113                 SIG_EXPR_LIST_PTR(RGMII1TXCTL));
1114
1115 #define F9 154
1116 SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
1117 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
1118 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
1119 MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
1120                 SIG_EXPR_LIST_PTR(RGMII1TXD0));
1121
1122 #define A5 155
1123 SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
1124 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
1125 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
1126 MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
1127                 SIG_EXPR_LIST_PTR(RGMII1TXD1));
1128
1129 #define E7 156
1130 SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
1131 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC);
1132 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
1133 MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
1134                 SIG_EXPR_LIST_PTR(RGMII1TXD2));
1135
1136 #define D7 157
1137 SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
1138 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC);
1139 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
1140 MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
1141                 SIG_EXPR_LIST_PTR(RGMII1TXD3));
1142
1143 #define B2 158
1144 SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
1145 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC,
1146                 SIG_DESC_SET(SCU48, 30));
1147 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
1148 MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO),
1149                 SIG_EXPR_LIST_PTR(RGMII2TXCK));
1150
1151 #define B1 159
1152 SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
1153 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
1154 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
1155 MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN),
1156                 SIG_EXPR_LIST_PTR(RGMII2TXCTL));
1157
1158 #define A2 160
1159 SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
1160 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
1161 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
1162 MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
1163                 SIG_EXPR_LIST_PTR(RGMII2TXD0));
1164
1165 #define B3 161
1166 SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
1167 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
1168 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
1169 MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
1170                 SIG_EXPR_LIST_PTR(RGMII2TXD1));
1171
1172 #define D5 162
1173 SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
1174 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC);
1175 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
1176 MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0),
1177                 SIG_EXPR_LIST_PTR(RGMII2TXD2));
1178
1179 #define D4 163
1180 SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
1181 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC);
1182 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
1183 MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1),
1184                 SIG_EXPR_LIST_PTR(RGMII2TXD3));
1185
1186 #define B4 164
1187 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
1188 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC);
1189 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
1190 MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
1191                 SIG_EXPR_LIST_PTR(RGMII1RXCK));
1192
1193 #define A4 165
1194 SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1195 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC);
1196 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
1197 MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
1198                 SIG_EXPR_LIST_PTR(RGMII1RXCTL));
1199
1200 #define A3 166
1201 SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
1202 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
1203 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
1204 MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
1205                 SIG_EXPR_LIST_PTR(RGMII1RXD0));
1206
1207 #define D6 167
1208 SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
1209 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
1210 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
1211 MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
1212                 SIG_EXPR_LIST_PTR(RGMII1RXD1));
1213
1214 #define C5 168
1215 SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
1216 SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
1217 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
1218 MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
1219                 SIG_EXPR_LIST_PTR(RGMII1RXD2));
1220
1221 #define C4 169
1222 SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
1223 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
1224 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
1225 MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
1226                 SIG_EXPR_LIST_PTR(RGMII1RXD3));
1227
1228 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
1229 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
1230
1231 #define C2 170
1232 SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
1233 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC);
1234 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
1235 MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI),
1236                 SIG_EXPR_LIST_PTR(RGMII2RXCK));
1237
1238 #define C1 171
1239 SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
1240 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC);
1241 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
1242 MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2),
1243                 SIG_EXPR_LIST_PTR(RGMII2RXCTL));
1244
1245 #define C3 172
1246 SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
1247 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
1248 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
1249 MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
1250                 SIG_EXPR_LIST_PTR(RGMII2RXD0));
1251
1252 #define D1 173
1253 SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
1254 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
1255 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
1256 MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
1257                 SIG_EXPR_LIST_PTR(RGMII2RXD1));
1258
1259 #define D2 174
1260 SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
1261 SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
1262 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
1263 MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
1264                 SIG_EXPR_LIST_PTR(RGMII2RXD2));
1265
1266 #define E6 175
1267 SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
1268 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
1269 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
1270 MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
1271                 SIG_EXPR_LIST_PTR(RGMII2RXD3));
1272
1273 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
1274 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
1275
1276 #define F4 176
1277 SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
1278 SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
1279 MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
1280 FUNC_GROUP_DECL(ADC0, F4);
1281
1282 #define F5 177
1283 SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
1284 SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
1285 MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
1286 FUNC_GROUP_DECL(ADC1, F5);
1287
1288 #define E2 178
1289 SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
1290 SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
1291 MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
1292 FUNC_GROUP_DECL(ADC2, E2);
1293
1294 #define E1 179
1295 SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1296 SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
1297 MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
1298 FUNC_GROUP_DECL(ADC3, E1);
1299
1300 #define F3 180
1301 SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1302 SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
1303 MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
1304 FUNC_GROUP_DECL(ADC4, F3);
1305
1306 #define E3 181
1307 SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
1308 SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
1309 MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
1310 FUNC_GROUP_DECL(ADC5, E3);
1311
1312 #define G5 182
1313 SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
1314 SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
1315 MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
1316 FUNC_GROUP_DECL(ADC6, G5);
1317
1318 #define G4 183
1319 SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
1320 SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
1321 MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
1322 FUNC_GROUP_DECL(ADC7, G4);
1323
1324 #define F2 184
1325 SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
1326 SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
1327 MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
1328 FUNC_GROUP_DECL(ADC8, F2);
1329
1330 #define G3 185
1331 SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1332 SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
1333 MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
1334 FUNC_GROUP_DECL(ADC9, G3);
1335
1336 #define G2 186
1337 SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
1338 SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
1339 MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
1340 FUNC_GROUP_DECL(ADC10, G2);
1341
1342 #define F1 187
1343 SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
1344 SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
1345 MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
1346 FUNC_GROUP_DECL(ADC11, F1);
1347
1348 #define H5 188
1349 SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
1350 SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
1351 MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
1352 FUNC_GROUP_DECL(ADC12, H5);
1353
1354 #define G1 189
1355 SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
1356 SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
1357 MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
1358 FUNC_GROUP_DECL(ADC13, G1);
1359
1360 #define H3 190
1361 SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
1362 SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
1363 MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
1364 FUNC_GROUP_DECL(ADC14, H3);
1365
1366 #define H4 191
1367 SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
1368 SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
1369 MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
1370 FUNC_GROUP_DECL(ADC15, H4);
1371
1372 #define ACPI_DESC       SIG_DESC_SET(HW_STRAP1, 19)
1373
1374 #define R22 192
1375 SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
1376 SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
1377 SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
1378 SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
1379 MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
1380 FUNC_GROUP_DECL(SIOS3, R22);
1381
1382 #define R21 193
1383 SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
1384 SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
1385 SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
1386 SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
1387 MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
1388 FUNC_GROUP_DECL(SIOS5, R21);
1389
1390 #define P22 194
1391 SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
1392 SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
1393 SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
1394 SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
1395 MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
1396 FUNC_GROUP_DECL(SIOPWREQ, P22);
1397
1398 #define P21 195
1399 SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
1400 SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
1401 SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
1402 SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
1403 MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
1404 FUNC_GROUP_DECL(SIOONCTRL, P21);
1405
1406 #define M18 196
1407 SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
1408
1409 #define M19 197
1410 SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
1411
1412 #define M20 198
1413 SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
1414
1415 #define P20 199
1416 SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
1417
1418 #define PNOR_DESC       SIG_DESC_SET(SCU90, 31)
1419
1420 #define Y20 200
1421 #define Y20_DESC        SIG_DESC_SET(SCUA4, 16)
1422 SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1423 SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1424 SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1425 SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
1426                 SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
1427 SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
1428 SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
1429 SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
1430 SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
1431 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
1432 MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
1433                 SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
1434 FUNC_GROUP_DECL(SIOPBI, Y20);
1435
1436 #define AB20 201
1437 #define AB20_DESC       SIG_DESC_SET(SCUA4, 17)
1438 SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1439 SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1440 SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1441 SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
1442                 SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
1443 SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
1444 SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
1445 SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
1446 SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
1447 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
1448 MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
1449                 SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
1450 FUNC_GROUP_DECL(SIOPWRGD, AB20);
1451
1452 #define AB21 202
1453 #define AB21_DESC       SIG_DESC_SET(SCUA4, 18)
1454 SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1455 SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1456 SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1457 SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
1458                 SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
1459 SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
1460 SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
1461 SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
1462 SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
1463 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
1464 MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
1465                 SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
1466 FUNC_GROUP_DECL(SIOPBO, AB21);
1467
1468 #define AA21 203
1469 #define AA21_DESC       SIG_DESC_SET(SCUA4, 19)
1470 SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1471 SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1472 SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1473 SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
1474                 SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
1475 SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
1476 SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
1477 SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
1478 SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
1479 SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
1480 MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
1481                 SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
1482 FUNC_GROUP_DECL(SIOSCI, AA21);
1483
1484 FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
1485
1486 /* CRT DVO disabled, configured for single-edge mode */
1487 #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
1488
1489 /* CRT DVO disabled, configured for dual-edge mode */
1490 #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
1491
1492 /* CRT DVO enabled, configured for single-edge mode */
1493 #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
1494
1495 /* CRT DVO enabled, configured for dual-edge mode */
1496 #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
1497
1498 #define U21 204
1499 #define U21_DESC        SIG_DESC_SET(SCUA4, 20)
1500 SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1501 SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1502 SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1503 SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
1504                 SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
1505 SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
1506 MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
1507
1508 #define W22 205
1509 #define W22_DESC        SIG_DESC_SET(SCUA4, 21)
1510 SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1511 SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1512 SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1513 SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
1514                 SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
1515 SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
1516 MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
1517
1518 #define V22 206
1519 #define V22_DESC        SIG_DESC_SET(SCUA4, 22)
1520 SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1521 SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1522 SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1523 SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
1524                 SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
1525 SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
1526 MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
1527
1528 #define W21 207
1529 #define W21_DESC        SIG_DESC_SET(SCUA4, 23)
1530 SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1531 SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1532 SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1533 SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
1534                 SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
1535 SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
1536 MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
1537
1538 #define Y21 208
1539 #define Y21_DESC        SIG_DESC_SET(SCUA4, 24)
1540 SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1541 SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1542 SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1543 SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
1544                 SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
1545 SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
1546 SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
1547 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
1548 MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
1549                 SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
1550 FUNC_GROUP_DECL(SALT7, Y21);
1551
1552 #define V21 209
1553 #define V21_DESC        SIG_DESC_SET(SCUA4, 25)
1554 SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1555 SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1556 SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1557 SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
1558                 SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
1559 SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
1560 SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
1561 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
1562 MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
1563                 SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
1564 FUNC_GROUP_DECL(SALT8, V21);
1565
1566 #define Y22 210
1567 #define Y22_DESC        SIG_DESC_SET(SCUA4, 26)
1568 SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1569 SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1570 SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1571 SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
1572                 SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
1573 SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
1574 SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
1575 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
1576 MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
1577                 SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
1578 FUNC_GROUP_DECL(SALT9, Y22);
1579
1580 #define AA22 211
1581 #define AA22_DESC       SIG_DESC_SET(SCUA4, 27)
1582 SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1583 SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1584 SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1585 SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
1586                 SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
1587 SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
1588 SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
1589 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
1590 MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
1591                 SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
1592 FUNC_GROUP_DECL(SALT10, AA22);
1593
1594 #define U22 212
1595 #define U22_DESC        SIG_DESC_SET(SCUA4, 28)
1596 SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1597 SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1598 SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1599 SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
1600                 SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
1601 SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
1602 SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
1603 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
1604 MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
1605                 SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
1606 FUNC_GROUP_DECL(SALT11, U22);
1607
1608 #define T20 213
1609 #define T20_DESC        SIG_DESC_SET(SCUA4, 29)
1610 SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1611 SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1612 SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1613 SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
1614                 SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
1615 SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
1616 SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
1617 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
1618 MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
1619                 SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
1620 FUNC_GROUP_DECL(SALT12, T20);
1621
1622 #define N18 214
1623 #define N18_DESC        SIG_DESC_SET(SCUA4, 30)
1624 SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1625 SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1626 SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1627 SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
1628                 SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
1629 SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
1630 SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
1631 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
1632 MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
1633                 SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
1634 FUNC_GROUP_DECL(SALT13, N18);
1635
1636 #define P19 215
1637 #define P19_DESC        SIG_DESC_SET(SCUA4, 31)
1638 SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
1639 SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
1640 SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
1641 SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
1642                 SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
1643 SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
1644 SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
1645 SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
1646 MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
1647                 SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
1648 FUNC_GROUP_DECL(SALT14, P19);
1649
1650 #define N19 216
1651 #define N19_DESC        SIG_DESC_SET(SCUA8, 0)
1652 SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1653 SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1654 SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1655 SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
1656                 SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
1657 SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
1658 MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
1659
1660 #define T21 217
1661 #define T21_DESC        SIG_DESC_SET(SCUA8, 1)
1662 SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1663 SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1664 SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1665 SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
1666                 SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
1667 SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
1668 MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
1669
1670 FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
1671                 AA22, U22, T20, N18, P19, N19, T21);
1672
1673 #define T22 218
1674 #define T22_DESC        SIG_DESC_SET(SCUA8, 2)
1675 SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1676 SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1677 SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1678 SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
1679                 SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
1680 SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
1681 MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
1682 FUNC_GROUP_DECL(WDTRST1, T22);
1683
1684 #define R20 219
1685 #define R20_DESC        SIG_DESC_SET(SCUA8, 3)
1686 SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
1687 SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
1688 SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
1689 SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
1690                 SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
1691 SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
1692 MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
1693 FUNC_GROUP_DECL(WDTRST2, R20);
1694
1695 FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
1696                 AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
1697                 N18, P19, N19, T21, T22, R20);
1698
1699 #define ESPI_DESC       SIG_DESC_SET(HW_STRAP1, 25)
1700
1701 #define G21 224
1702 SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
1703 SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
1704 MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
1705 FUNC_GROUP_DECL(LAD0, G21);
1706
1707 #define G20 225
1708 SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
1709 SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
1710 MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
1711 FUNC_GROUP_DECL(LAD1, G20);
1712
1713 #define D22 226
1714 SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
1715 SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
1716 MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
1717 FUNC_GROUP_DECL(LAD2, D22);
1718
1719 #define E22 227
1720 SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
1721 SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
1722 MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
1723 FUNC_GROUP_DECL(LAD3, E22);
1724
1725 #define C22 228
1726 SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
1727 SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
1728 MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
1729 FUNC_GROUP_DECL(LCLK, C22);
1730
1731 #define F21 229
1732 SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
1733 SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
1734 MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
1735 FUNC_GROUP_DECL(LFRAME, F21);
1736
1737 #define F22 230
1738 SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
1739 SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
1740 MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
1741 FUNC_GROUP_DECL(LSIRQ, F22);
1742
1743 #define G22 231
1744 SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
1745 SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
1746 MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
1747 FUNC_GROUP_DECL(LPCRST, G22);
1748
1749 FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
1750
1751 #define A7 232
1752 SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
1753 SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1754 MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
1755
1756 #define A8 233
1757 SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
1758 SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1759 MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
1760
1761 FUNC_GROUP_DECL(USB2AH, A7, A8);
1762 FUNC_GROUP_DECL(USB2AD, A7, A8);
1763
1764 #define USB11BHID_DESC  { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
1765 #define USB2BD_DESC   { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1766 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
1767 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
1768
1769 #define B6 234
1770 SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
1771 SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
1772 SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
1773 SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
1774 SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
1775                 SIG_EXPR_PTR(USB2BHDP2, USB2BH));
1776 MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
1777                 SIG_EXPR_LIST_PTR(USB2BHDP));
1778
1779 #define A6 235
1780 SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
1781 SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
1782 SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
1783 SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
1784 SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
1785                 SIG_EXPR_PTR(USB2BHDN2, USB2BH));
1786 MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
1787                 SIG_EXPR_LIST_PTR(USB2BHDN));
1788
1789 FUNC_GROUP_DECL(USB11BHID, B6, A6);
1790 FUNC_GROUP_DECL(USB2BD, B6, A6);
1791 FUNC_GROUP_DECL(USB2BH, B6, A6);
1792
1793 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1794
1795 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
1796         ASPEED_PINCTRL_PIN(A10),
1797         ASPEED_PINCTRL_PIN(A11),
1798         ASPEED_PINCTRL_PIN(A12),
1799         ASPEED_PINCTRL_PIN(A13),
1800         ASPEED_PINCTRL_PIN(A14),
1801         ASPEED_PINCTRL_PIN(A15),
1802         ASPEED_PINCTRL_PIN(A16),
1803         ASPEED_PINCTRL_PIN(A17),
1804         ASPEED_PINCTRL_PIN(A18),
1805         ASPEED_PINCTRL_PIN(A19),
1806         ASPEED_PINCTRL_PIN(A2),
1807         ASPEED_PINCTRL_PIN(A20),
1808         ASPEED_PINCTRL_PIN(A21),
1809         ASPEED_PINCTRL_PIN(A3),
1810         ASPEED_PINCTRL_PIN(A4),
1811         ASPEED_PINCTRL_PIN(A5),
1812         ASPEED_PINCTRL_PIN(A6),
1813         ASPEED_PINCTRL_PIN(A7),
1814         ASPEED_PINCTRL_PIN(A8),
1815         ASPEED_PINCTRL_PIN(A9),
1816         ASPEED_PINCTRL_PIN(AA1),
1817         ASPEED_PINCTRL_PIN(AA19),
1818         ASPEED_PINCTRL_PIN(AA2),
1819         ASPEED_PINCTRL_PIN(AA20),
1820         ASPEED_PINCTRL_PIN(AA21),
1821         ASPEED_PINCTRL_PIN(AA22),
1822         ASPEED_PINCTRL_PIN(AA3),
1823         ASPEED_PINCTRL_PIN(AA4),
1824         ASPEED_PINCTRL_PIN(AA5),
1825         ASPEED_PINCTRL_PIN(AB2),
1826         ASPEED_PINCTRL_PIN(AB20),
1827         ASPEED_PINCTRL_PIN(AB21),
1828         ASPEED_PINCTRL_PIN(AB3),
1829         ASPEED_PINCTRL_PIN(AB4),
1830         ASPEED_PINCTRL_PIN(AB5),
1831         ASPEED_PINCTRL_PIN(B1),
1832         ASPEED_PINCTRL_PIN(B10),
1833         ASPEED_PINCTRL_PIN(B11),
1834         ASPEED_PINCTRL_PIN(B12),
1835         ASPEED_PINCTRL_PIN(B13),
1836         ASPEED_PINCTRL_PIN(B14),
1837         ASPEED_PINCTRL_PIN(B15),
1838         ASPEED_PINCTRL_PIN(B16),
1839         ASPEED_PINCTRL_PIN(B17),
1840         ASPEED_PINCTRL_PIN(B18),
1841         ASPEED_PINCTRL_PIN(B19),
1842         ASPEED_PINCTRL_PIN(B2),
1843         ASPEED_PINCTRL_PIN(B20),
1844         ASPEED_PINCTRL_PIN(B21),
1845         ASPEED_PINCTRL_PIN(B22),
1846         ASPEED_PINCTRL_PIN(B3),
1847         ASPEED_PINCTRL_PIN(B4),
1848         ASPEED_PINCTRL_PIN(B5),
1849         ASPEED_PINCTRL_PIN(B6),
1850         ASPEED_PINCTRL_PIN(B9),
1851         ASPEED_PINCTRL_PIN(C1),
1852         ASPEED_PINCTRL_PIN(C11),
1853         ASPEED_PINCTRL_PIN(C12),
1854         ASPEED_PINCTRL_PIN(C13),
1855         ASPEED_PINCTRL_PIN(C14),
1856         ASPEED_PINCTRL_PIN(C15),
1857         ASPEED_PINCTRL_PIN(C16),
1858         ASPEED_PINCTRL_PIN(C17),
1859         ASPEED_PINCTRL_PIN(C18),
1860         ASPEED_PINCTRL_PIN(C19),
1861         ASPEED_PINCTRL_PIN(C2),
1862         ASPEED_PINCTRL_PIN(C20),
1863         ASPEED_PINCTRL_PIN(C21),
1864         ASPEED_PINCTRL_PIN(C22),
1865         ASPEED_PINCTRL_PIN(C3),
1866         ASPEED_PINCTRL_PIN(C4),
1867         ASPEED_PINCTRL_PIN(C5),
1868         ASPEED_PINCTRL_PIN(D1),
1869         ASPEED_PINCTRL_PIN(D10),
1870         ASPEED_PINCTRL_PIN(D13),
1871         ASPEED_PINCTRL_PIN(D14),
1872         ASPEED_PINCTRL_PIN(D15),
1873         ASPEED_PINCTRL_PIN(D16),
1874         ASPEED_PINCTRL_PIN(D17),
1875         ASPEED_PINCTRL_PIN(D18),
1876         ASPEED_PINCTRL_PIN(D19),
1877         ASPEED_PINCTRL_PIN(D2),
1878         ASPEED_PINCTRL_PIN(D20),
1879         ASPEED_PINCTRL_PIN(D21),
1880         ASPEED_PINCTRL_PIN(D22),
1881         ASPEED_PINCTRL_PIN(D4),
1882         ASPEED_PINCTRL_PIN(D5),
1883         ASPEED_PINCTRL_PIN(D6),
1884         ASPEED_PINCTRL_PIN(D7),
1885         ASPEED_PINCTRL_PIN(D8),
1886         ASPEED_PINCTRL_PIN(D9),
1887         ASPEED_PINCTRL_PIN(E1),
1888         ASPEED_PINCTRL_PIN(E10),
1889         ASPEED_PINCTRL_PIN(E12),
1890         ASPEED_PINCTRL_PIN(E13),
1891         ASPEED_PINCTRL_PIN(E14),
1892         ASPEED_PINCTRL_PIN(E15),
1893         ASPEED_PINCTRL_PIN(E16),
1894         ASPEED_PINCTRL_PIN(E17),
1895         ASPEED_PINCTRL_PIN(E18),
1896         ASPEED_PINCTRL_PIN(E19),
1897         ASPEED_PINCTRL_PIN(E2),
1898         ASPEED_PINCTRL_PIN(E20),
1899         ASPEED_PINCTRL_PIN(E21),
1900         ASPEED_PINCTRL_PIN(E22),
1901         ASPEED_PINCTRL_PIN(E3),
1902         ASPEED_PINCTRL_PIN(E6),
1903         ASPEED_PINCTRL_PIN(E7),
1904         ASPEED_PINCTRL_PIN(E9),
1905         ASPEED_PINCTRL_PIN(F1),
1906         ASPEED_PINCTRL_PIN(F17),
1907         ASPEED_PINCTRL_PIN(F18),
1908         ASPEED_PINCTRL_PIN(F19),
1909         ASPEED_PINCTRL_PIN(F2),
1910         ASPEED_PINCTRL_PIN(F20),
1911         ASPEED_PINCTRL_PIN(F21),
1912         ASPEED_PINCTRL_PIN(F22),
1913         ASPEED_PINCTRL_PIN(F3),
1914         ASPEED_PINCTRL_PIN(F4),
1915         ASPEED_PINCTRL_PIN(F5),
1916         ASPEED_PINCTRL_PIN(F9),
1917         ASPEED_PINCTRL_PIN(G1),
1918         ASPEED_PINCTRL_PIN(G17),
1919         ASPEED_PINCTRL_PIN(G18),
1920         ASPEED_PINCTRL_PIN(G2),
1921         ASPEED_PINCTRL_PIN(G20),
1922         ASPEED_PINCTRL_PIN(G21),
1923         ASPEED_PINCTRL_PIN(G22),
1924         ASPEED_PINCTRL_PIN(G3),
1925         ASPEED_PINCTRL_PIN(G4),
1926         ASPEED_PINCTRL_PIN(G5),
1927         ASPEED_PINCTRL_PIN(H18),
1928         ASPEED_PINCTRL_PIN(H19),
1929         ASPEED_PINCTRL_PIN(H20),
1930         ASPEED_PINCTRL_PIN(H21),
1931         ASPEED_PINCTRL_PIN(H22),
1932         ASPEED_PINCTRL_PIN(H3),
1933         ASPEED_PINCTRL_PIN(H4),
1934         ASPEED_PINCTRL_PIN(H5),
1935         ASPEED_PINCTRL_PIN(J18),
1936         ASPEED_PINCTRL_PIN(J19),
1937         ASPEED_PINCTRL_PIN(J20),
1938         ASPEED_PINCTRL_PIN(K18),
1939         ASPEED_PINCTRL_PIN(K19),
1940         ASPEED_PINCTRL_PIN(L1),
1941         ASPEED_PINCTRL_PIN(L18),
1942         ASPEED_PINCTRL_PIN(L19),
1943         ASPEED_PINCTRL_PIN(L2),
1944         ASPEED_PINCTRL_PIN(L3),
1945         ASPEED_PINCTRL_PIN(L4),
1946         ASPEED_PINCTRL_PIN(M18),
1947         ASPEED_PINCTRL_PIN(M19),
1948         ASPEED_PINCTRL_PIN(M20),
1949         ASPEED_PINCTRL_PIN(N1),
1950         ASPEED_PINCTRL_PIN(N18),
1951         ASPEED_PINCTRL_PIN(N19),
1952         ASPEED_PINCTRL_PIN(N2),
1953         ASPEED_PINCTRL_PIN(N20),
1954         ASPEED_PINCTRL_PIN(N21),
1955         ASPEED_PINCTRL_PIN(N22),
1956         ASPEED_PINCTRL_PIN(N3),
1957         ASPEED_PINCTRL_PIN(N4),
1958         ASPEED_PINCTRL_PIN(N5),
1959         ASPEED_PINCTRL_PIN(P1),
1960         ASPEED_PINCTRL_PIN(P18),
1961         ASPEED_PINCTRL_PIN(P19),
1962         ASPEED_PINCTRL_PIN(P2),
1963         ASPEED_PINCTRL_PIN(P20),
1964         ASPEED_PINCTRL_PIN(P21),
1965         ASPEED_PINCTRL_PIN(P22),
1966         ASPEED_PINCTRL_PIN(P3),
1967         ASPEED_PINCTRL_PIN(P4),
1968         ASPEED_PINCTRL_PIN(P5),
1969         ASPEED_PINCTRL_PIN(R1),
1970         ASPEED_PINCTRL_PIN(R18),
1971         ASPEED_PINCTRL_PIN(R19),
1972         ASPEED_PINCTRL_PIN(R2),
1973         ASPEED_PINCTRL_PIN(R20),
1974         ASPEED_PINCTRL_PIN(R21),
1975         ASPEED_PINCTRL_PIN(R22),
1976         ASPEED_PINCTRL_PIN(R3),
1977         ASPEED_PINCTRL_PIN(R4),
1978         ASPEED_PINCTRL_PIN(R5),
1979         ASPEED_PINCTRL_PIN(T1),
1980         ASPEED_PINCTRL_PIN(T17),
1981         ASPEED_PINCTRL_PIN(T19),
1982         ASPEED_PINCTRL_PIN(T2),
1983         ASPEED_PINCTRL_PIN(T20),
1984         ASPEED_PINCTRL_PIN(T21),
1985         ASPEED_PINCTRL_PIN(T22),
1986         ASPEED_PINCTRL_PIN(T3),
1987         ASPEED_PINCTRL_PIN(T4),
1988         ASPEED_PINCTRL_PIN(T5),
1989         ASPEED_PINCTRL_PIN(U1),
1990         ASPEED_PINCTRL_PIN(U19),
1991         ASPEED_PINCTRL_PIN(U2),
1992         ASPEED_PINCTRL_PIN(U20),
1993         ASPEED_PINCTRL_PIN(U21),
1994         ASPEED_PINCTRL_PIN(U22),
1995         ASPEED_PINCTRL_PIN(U3),
1996         ASPEED_PINCTRL_PIN(U4),
1997         ASPEED_PINCTRL_PIN(U5),
1998         ASPEED_PINCTRL_PIN(V1),
1999         ASPEED_PINCTRL_PIN(V19),
2000         ASPEED_PINCTRL_PIN(V2),
2001         ASPEED_PINCTRL_PIN(V20),
2002         ASPEED_PINCTRL_PIN(V21),
2003         ASPEED_PINCTRL_PIN(V22),
2004         ASPEED_PINCTRL_PIN(V3),
2005         ASPEED_PINCTRL_PIN(V4),
2006         ASPEED_PINCTRL_PIN(V5),
2007         ASPEED_PINCTRL_PIN(V6),
2008         ASPEED_PINCTRL_PIN(W1),
2009         ASPEED_PINCTRL_PIN(W19),
2010         ASPEED_PINCTRL_PIN(W2),
2011         ASPEED_PINCTRL_PIN(W20),
2012         ASPEED_PINCTRL_PIN(W21),
2013         ASPEED_PINCTRL_PIN(W22),
2014         ASPEED_PINCTRL_PIN(W3),
2015         ASPEED_PINCTRL_PIN(W4),
2016         ASPEED_PINCTRL_PIN(W5),
2017         ASPEED_PINCTRL_PIN(W6),
2018         ASPEED_PINCTRL_PIN(Y1),
2019         ASPEED_PINCTRL_PIN(Y19),
2020         ASPEED_PINCTRL_PIN(Y2),
2021         ASPEED_PINCTRL_PIN(Y20),
2022         ASPEED_PINCTRL_PIN(Y21),
2023         ASPEED_PINCTRL_PIN(Y22),
2024         ASPEED_PINCTRL_PIN(Y3),
2025         ASPEED_PINCTRL_PIN(Y4),
2026         ASPEED_PINCTRL_PIN(Y5),
2027         ASPEED_PINCTRL_PIN(Y6),
2028 };
2029
2030 static const struct aspeed_pin_group aspeed_g5_groups[] = {
2031         ASPEED_PINCTRL_GROUP(ACPI),
2032         ASPEED_PINCTRL_GROUP(ADC0),
2033         ASPEED_PINCTRL_GROUP(ADC1),
2034         ASPEED_PINCTRL_GROUP(ADC10),
2035         ASPEED_PINCTRL_GROUP(ADC11),
2036         ASPEED_PINCTRL_GROUP(ADC12),
2037         ASPEED_PINCTRL_GROUP(ADC13),
2038         ASPEED_PINCTRL_GROUP(ADC14),
2039         ASPEED_PINCTRL_GROUP(ADC15),
2040         ASPEED_PINCTRL_GROUP(ADC2),
2041         ASPEED_PINCTRL_GROUP(ADC3),
2042         ASPEED_PINCTRL_GROUP(ADC4),
2043         ASPEED_PINCTRL_GROUP(ADC5),
2044         ASPEED_PINCTRL_GROUP(ADC6),
2045         ASPEED_PINCTRL_GROUP(ADC7),
2046         ASPEED_PINCTRL_GROUP(ADC8),
2047         ASPEED_PINCTRL_GROUP(ADC9),
2048         ASPEED_PINCTRL_GROUP(BMCINT),
2049         ASPEED_PINCTRL_GROUP(DDCCLK),
2050         ASPEED_PINCTRL_GROUP(DDCDAT),
2051         ASPEED_PINCTRL_GROUP(ESPI),
2052         ASPEED_PINCTRL_GROUP(FWSPICS1),
2053         ASPEED_PINCTRL_GROUP(FWSPICS2),
2054         ASPEED_PINCTRL_GROUP(GPID0),
2055         ASPEED_PINCTRL_GROUP(GPID2),
2056         ASPEED_PINCTRL_GROUP(GPID4),
2057         ASPEED_PINCTRL_GROUP(GPID6),
2058         ASPEED_PINCTRL_GROUP(GPIE0),
2059         ASPEED_PINCTRL_GROUP(GPIE2),
2060         ASPEED_PINCTRL_GROUP(GPIE4),
2061         ASPEED_PINCTRL_GROUP(GPIE6),
2062         ASPEED_PINCTRL_GROUP(I2C10),
2063         ASPEED_PINCTRL_GROUP(I2C11),
2064         ASPEED_PINCTRL_GROUP(I2C12),
2065         ASPEED_PINCTRL_GROUP(I2C13),
2066         ASPEED_PINCTRL_GROUP(I2C14),
2067         ASPEED_PINCTRL_GROUP(I2C3),
2068         ASPEED_PINCTRL_GROUP(I2C4),
2069         ASPEED_PINCTRL_GROUP(I2C5),
2070         ASPEED_PINCTRL_GROUP(I2C6),
2071         ASPEED_PINCTRL_GROUP(I2C7),
2072         ASPEED_PINCTRL_GROUP(I2C8),
2073         ASPEED_PINCTRL_GROUP(I2C9),
2074         ASPEED_PINCTRL_GROUP(LAD0),
2075         ASPEED_PINCTRL_GROUP(LAD1),
2076         ASPEED_PINCTRL_GROUP(LAD2),
2077         ASPEED_PINCTRL_GROUP(LAD3),
2078         ASPEED_PINCTRL_GROUP(LCLK),
2079         ASPEED_PINCTRL_GROUP(LFRAME),
2080         ASPEED_PINCTRL_GROUP(LPCHC),
2081         ASPEED_PINCTRL_GROUP(LPCPD),
2082         ASPEED_PINCTRL_GROUP(LPCPLUS),
2083         ASPEED_PINCTRL_GROUP(LPCPME),
2084         ASPEED_PINCTRL_GROUP(LPCRST),
2085         ASPEED_PINCTRL_GROUP(LPCSMI),
2086         ASPEED_PINCTRL_GROUP(LSIRQ),
2087         ASPEED_PINCTRL_GROUP(MAC1LINK),
2088         ASPEED_PINCTRL_GROUP(MAC2LINK),
2089         ASPEED_PINCTRL_GROUP(MDIO1),
2090         ASPEED_PINCTRL_GROUP(MDIO2),
2091         ASPEED_PINCTRL_GROUP(NCTS1),
2092         ASPEED_PINCTRL_GROUP(NCTS2),
2093         ASPEED_PINCTRL_GROUP(NCTS3),
2094         ASPEED_PINCTRL_GROUP(NCTS4),
2095         ASPEED_PINCTRL_GROUP(NDCD1),
2096         ASPEED_PINCTRL_GROUP(NDCD2),
2097         ASPEED_PINCTRL_GROUP(NDCD3),
2098         ASPEED_PINCTRL_GROUP(NDCD4),
2099         ASPEED_PINCTRL_GROUP(NDSR1),
2100         ASPEED_PINCTRL_GROUP(NDSR2),
2101         ASPEED_PINCTRL_GROUP(NDSR3),
2102         ASPEED_PINCTRL_GROUP(NDSR4),
2103         ASPEED_PINCTRL_GROUP(NDTR1),
2104         ASPEED_PINCTRL_GROUP(NDTR2),
2105         ASPEED_PINCTRL_GROUP(NDTR3),
2106         ASPEED_PINCTRL_GROUP(NDTR4),
2107         ASPEED_PINCTRL_GROUP(NRI1),
2108         ASPEED_PINCTRL_GROUP(NRI2),
2109         ASPEED_PINCTRL_GROUP(NRI3),
2110         ASPEED_PINCTRL_GROUP(NRI4),
2111         ASPEED_PINCTRL_GROUP(NRTS1),
2112         ASPEED_PINCTRL_GROUP(NRTS2),
2113         ASPEED_PINCTRL_GROUP(NRTS3),
2114         ASPEED_PINCTRL_GROUP(NRTS4),
2115         ASPEED_PINCTRL_GROUP(OSCCLK),
2116         ASPEED_PINCTRL_GROUP(PEWAKE),
2117         ASPEED_PINCTRL_GROUP(PNOR),
2118         ASPEED_PINCTRL_GROUP(PWM0),
2119         ASPEED_PINCTRL_GROUP(PWM1),
2120         ASPEED_PINCTRL_GROUP(PWM2),
2121         ASPEED_PINCTRL_GROUP(PWM3),
2122         ASPEED_PINCTRL_GROUP(PWM4),
2123         ASPEED_PINCTRL_GROUP(PWM5),
2124         ASPEED_PINCTRL_GROUP(PWM6),
2125         ASPEED_PINCTRL_GROUP(PWM7),
2126         ASPEED_PINCTRL_GROUP(RGMII1),
2127         ASPEED_PINCTRL_GROUP(RGMII2),
2128         ASPEED_PINCTRL_GROUP(RMII1),
2129         ASPEED_PINCTRL_GROUP(RMII2),
2130         ASPEED_PINCTRL_GROUP(RXD1),
2131         ASPEED_PINCTRL_GROUP(RXD2),
2132         ASPEED_PINCTRL_GROUP(RXD3),
2133         ASPEED_PINCTRL_GROUP(RXD4),
2134         ASPEED_PINCTRL_GROUP(SALT1),
2135         ASPEED_PINCTRL_GROUP(SALT10),
2136         ASPEED_PINCTRL_GROUP(SALT11),
2137         ASPEED_PINCTRL_GROUP(SALT12),
2138         ASPEED_PINCTRL_GROUP(SALT13),
2139         ASPEED_PINCTRL_GROUP(SALT14),
2140         ASPEED_PINCTRL_GROUP(SALT2),
2141         ASPEED_PINCTRL_GROUP(SALT3),
2142         ASPEED_PINCTRL_GROUP(SALT4),
2143         ASPEED_PINCTRL_GROUP(SALT5),
2144         ASPEED_PINCTRL_GROUP(SALT6),
2145         ASPEED_PINCTRL_GROUP(SALT7),
2146         ASPEED_PINCTRL_GROUP(SALT8),
2147         ASPEED_PINCTRL_GROUP(SALT9),
2148         ASPEED_PINCTRL_GROUP(SCL1),
2149         ASPEED_PINCTRL_GROUP(SCL2),
2150         ASPEED_PINCTRL_GROUP(SD1),
2151         ASPEED_PINCTRL_GROUP(SD2),
2152         ASPEED_PINCTRL_GROUP(SDA1),
2153         ASPEED_PINCTRL_GROUP(SDA2),
2154         ASPEED_PINCTRL_GROUP(SGPM),
2155         ASPEED_PINCTRL_GROUP(SGPS1),
2156         ASPEED_PINCTRL_GROUP(SGPS2),
2157         ASPEED_PINCTRL_GROUP(SIOONCTRL),
2158         ASPEED_PINCTRL_GROUP(SIOPBI),
2159         ASPEED_PINCTRL_GROUP(SIOPBO),
2160         ASPEED_PINCTRL_GROUP(SIOPWREQ),
2161         ASPEED_PINCTRL_GROUP(SIOPWRGD),
2162         ASPEED_PINCTRL_GROUP(SIOS3),
2163         ASPEED_PINCTRL_GROUP(SIOS5),
2164         ASPEED_PINCTRL_GROUP(SIOSCI),
2165         ASPEED_PINCTRL_GROUP(SPI1),
2166         ASPEED_PINCTRL_GROUP(SPI1CS1),
2167         ASPEED_PINCTRL_GROUP(SPI1DEBUG),
2168         ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
2169         ASPEED_PINCTRL_GROUP(SPI2CK),
2170         ASPEED_PINCTRL_GROUP(SPI2CS0),
2171         ASPEED_PINCTRL_GROUP(SPI2CS1),
2172         ASPEED_PINCTRL_GROUP(SPI2MISO),
2173         ASPEED_PINCTRL_GROUP(SPI2MOSI),
2174         ASPEED_PINCTRL_GROUP(TIMER3),
2175         ASPEED_PINCTRL_GROUP(TIMER4),
2176         ASPEED_PINCTRL_GROUP(TIMER5),
2177         ASPEED_PINCTRL_GROUP(TIMER6),
2178         ASPEED_PINCTRL_GROUP(TIMER7),
2179         ASPEED_PINCTRL_GROUP(TIMER8),
2180         ASPEED_PINCTRL_GROUP(TXD1),
2181         ASPEED_PINCTRL_GROUP(TXD2),
2182         ASPEED_PINCTRL_GROUP(TXD3),
2183         ASPEED_PINCTRL_GROUP(TXD4),
2184         ASPEED_PINCTRL_GROUP(UART6),
2185         ASPEED_PINCTRL_GROUP(USB11BHID),
2186         ASPEED_PINCTRL_GROUP(USB2AD),
2187         ASPEED_PINCTRL_GROUP(USB2AH),
2188         ASPEED_PINCTRL_GROUP(USB2BD),
2189         ASPEED_PINCTRL_GROUP(USB2BH),
2190         ASPEED_PINCTRL_GROUP(USBCKI),
2191         ASPEED_PINCTRL_GROUP(VGABIOSROM),
2192         ASPEED_PINCTRL_GROUP(VGAHS),
2193         ASPEED_PINCTRL_GROUP(VGAVS),
2194         ASPEED_PINCTRL_GROUP(VPI24),
2195         ASPEED_PINCTRL_GROUP(VPO),
2196         ASPEED_PINCTRL_GROUP(WDTRST1),
2197         ASPEED_PINCTRL_GROUP(WDTRST2),
2198 };
2199
2200 static const struct aspeed_pin_function aspeed_g5_functions[] = {
2201         ASPEED_PINCTRL_FUNC(ACPI),
2202         ASPEED_PINCTRL_FUNC(ADC0),
2203         ASPEED_PINCTRL_FUNC(ADC1),
2204         ASPEED_PINCTRL_FUNC(ADC10),
2205         ASPEED_PINCTRL_FUNC(ADC11),
2206         ASPEED_PINCTRL_FUNC(ADC12),
2207         ASPEED_PINCTRL_FUNC(ADC13),
2208         ASPEED_PINCTRL_FUNC(ADC14),
2209         ASPEED_PINCTRL_FUNC(ADC15),
2210         ASPEED_PINCTRL_FUNC(ADC2),
2211         ASPEED_PINCTRL_FUNC(ADC3),
2212         ASPEED_PINCTRL_FUNC(ADC4),
2213         ASPEED_PINCTRL_FUNC(ADC5),
2214         ASPEED_PINCTRL_FUNC(ADC6),
2215         ASPEED_PINCTRL_FUNC(ADC7),
2216         ASPEED_PINCTRL_FUNC(ADC8),
2217         ASPEED_PINCTRL_FUNC(ADC9),
2218         ASPEED_PINCTRL_FUNC(BMCINT),
2219         ASPEED_PINCTRL_FUNC(DDCCLK),
2220         ASPEED_PINCTRL_FUNC(DDCDAT),
2221         ASPEED_PINCTRL_FUNC(ESPI),
2222         ASPEED_PINCTRL_FUNC(FWSPICS1),
2223         ASPEED_PINCTRL_FUNC(FWSPICS2),
2224         ASPEED_PINCTRL_FUNC(GPID0),
2225         ASPEED_PINCTRL_FUNC(GPID2),
2226         ASPEED_PINCTRL_FUNC(GPID4),
2227         ASPEED_PINCTRL_FUNC(GPID6),
2228         ASPEED_PINCTRL_FUNC(GPIE0),
2229         ASPEED_PINCTRL_FUNC(GPIE2),
2230         ASPEED_PINCTRL_FUNC(GPIE4),
2231         ASPEED_PINCTRL_FUNC(GPIE6),
2232         ASPEED_PINCTRL_FUNC(I2C10),
2233         ASPEED_PINCTRL_FUNC(I2C11),
2234         ASPEED_PINCTRL_FUNC(I2C12),
2235         ASPEED_PINCTRL_FUNC(I2C13),
2236         ASPEED_PINCTRL_FUNC(I2C14),
2237         ASPEED_PINCTRL_FUNC(I2C3),
2238         ASPEED_PINCTRL_FUNC(I2C4),
2239         ASPEED_PINCTRL_FUNC(I2C5),
2240         ASPEED_PINCTRL_FUNC(I2C6),
2241         ASPEED_PINCTRL_FUNC(I2C7),
2242         ASPEED_PINCTRL_FUNC(I2C8),
2243         ASPEED_PINCTRL_FUNC(I2C9),
2244         ASPEED_PINCTRL_FUNC(LAD0),
2245         ASPEED_PINCTRL_FUNC(LAD1),
2246         ASPEED_PINCTRL_FUNC(LAD2),
2247         ASPEED_PINCTRL_FUNC(LAD3),
2248         ASPEED_PINCTRL_FUNC(LCLK),
2249         ASPEED_PINCTRL_FUNC(LFRAME),
2250         ASPEED_PINCTRL_FUNC(LPCHC),
2251         ASPEED_PINCTRL_FUNC(LPCPD),
2252         ASPEED_PINCTRL_FUNC(LPCPLUS),
2253         ASPEED_PINCTRL_FUNC(LPCPME),
2254         ASPEED_PINCTRL_FUNC(LPCRST),
2255         ASPEED_PINCTRL_FUNC(LPCSMI),
2256         ASPEED_PINCTRL_FUNC(LSIRQ),
2257         ASPEED_PINCTRL_FUNC(MAC1LINK),
2258         ASPEED_PINCTRL_FUNC(MAC2LINK),
2259         ASPEED_PINCTRL_FUNC(MDIO1),
2260         ASPEED_PINCTRL_FUNC(MDIO2),
2261         ASPEED_PINCTRL_FUNC(NCTS1),
2262         ASPEED_PINCTRL_FUNC(NCTS2),
2263         ASPEED_PINCTRL_FUNC(NCTS3),
2264         ASPEED_PINCTRL_FUNC(NCTS4),
2265         ASPEED_PINCTRL_FUNC(NDCD1),
2266         ASPEED_PINCTRL_FUNC(NDCD2),
2267         ASPEED_PINCTRL_FUNC(NDCD3),
2268         ASPEED_PINCTRL_FUNC(NDCD4),
2269         ASPEED_PINCTRL_FUNC(NDSR1),
2270         ASPEED_PINCTRL_FUNC(NDSR2),
2271         ASPEED_PINCTRL_FUNC(NDSR3),
2272         ASPEED_PINCTRL_FUNC(NDSR4),
2273         ASPEED_PINCTRL_FUNC(NDTR1),
2274         ASPEED_PINCTRL_FUNC(NDTR2),
2275         ASPEED_PINCTRL_FUNC(NDTR3),
2276         ASPEED_PINCTRL_FUNC(NDTR4),
2277         ASPEED_PINCTRL_FUNC(NRI1),
2278         ASPEED_PINCTRL_FUNC(NRI2),
2279         ASPEED_PINCTRL_FUNC(NRI3),
2280         ASPEED_PINCTRL_FUNC(NRI4),
2281         ASPEED_PINCTRL_FUNC(NRTS1),
2282         ASPEED_PINCTRL_FUNC(NRTS2),
2283         ASPEED_PINCTRL_FUNC(NRTS3),
2284         ASPEED_PINCTRL_FUNC(NRTS4),
2285         ASPEED_PINCTRL_FUNC(OSCCLK),
2286         ASPEED_PINCTRL_FUNC(PEWAKE),
2287         ASPEED_PINCTRL_FUNC(PNOR),
2288         ASPEED_PINCTRL_FUNC(PWM0),
2289         ASPEED_PINCTRL_FUNC(PWM1),
2290         ASPEED_PINCTRL_FUNC(PWM2),
2291         ASPEED_PINCTRL_FUNC(PWM3),
2292         ASPEED_PINCTRL_FUNC(PWM4),
2293         ASPEED_PINCTRL_FUNC(PWM5),
2294         ASPEED_PINCTRL_FUNC(PWM6),
2295         ASPEED_PINCTRL_FUNC(PWM7),
2296         ASPEED_PINCTRL_FUNC(RGMII1),
2297         ASPEED_PINCTRL_FUNC(RGMII2),
2298         ASPEED_PINCTRL_FUNC(RMII1),
2299         ASPEED_PINCTRL_FUNC(RMII2),
2300         ASPEED_PINCTRL_FUNC(RXD1),
2301         ASPEED_PINCTRL_FUNC(RXD2),
2302         ASPEED_PINCTRL_FUNC(RXD3),
2303         ASPEED_PINCTRL_FUNC(RXD4),
2304         ASPEED_PINCTRL_FUNC(SALT1),
2305         ASPEED_PINCTRL_FUNC(SALT10),
2306         ASPEED_PINCTRL_FUNC(SALT11),
2307         ASPEED_PINCTRL_FUNC(SALT12),
2308         ASPEED_PINCTRL_FUNC(SALT13),
2309         ASPEED_PINCTRL_FUNC(SALT14),
2310         ASPEED_PINCTRL_FUNC(SALT2),
2311         ASPEED_PINCTRL_FUNC(SALT3),
2312         ASPEED_PINCTRL_FUNC(SALT4),
2313         ASPEED_PINCTRL_FUNC(SALT5),
2314         ASPEED_PINCTRL_FUNC(SALT6),
2315         ASPEED_PINCTRL_FUNC(SALT7),
2316         ASPEED_PINCTRL_FUNC(SALT8),
2317         ASPEED_PINCTRL_FUNC(SALT9),
2318         ASPEED_PINCTRL_FUNC(SCL1),
2319         ASPEED_PINCTRL_FUNC(SCL2),
2320         ASPEED_PINCTRL_FUNC(SD1),
2321         ASPEED_PINCTRL_FUNC(SD2),
2322         ASPEED_PINCTRL_FUNC(SDA1),
2323         ASPEED_PINCTRL_FUNC(SDA2),
2324         ASPEED_PINCTRL_FUNC(SGPM),
2325         ASPEED_PINCTRL_FUNC(SGPS1),
2326         ASPEED_PINCTRL_FUNC(SGPS2),
2327         ASPEED_PINCTRL_FUNC(SIOONCTRL),
2328         ASPEED_PINCTRL_FUNC(SIOPBI),
2329         ASPEED_PINCTRL_FUNC(SIOPBO),
2330         ASPEED_PINCTRL_FUNC(SIOPWREQ),
2331         ASPEED_PINCTRL_FUNC(SIOPWRGD),
2332         ASPEED_PINCTRL_FUNC(SIOS3),
2333         ASPEED_PINCTRL_FUNC(SIOS5),
2334         ASPEED_PINCTRL_FUNC(SIOSCI),
2335         ASPEED_PINCTRL_FUNC(SPI1),
2336         ASPEED_PINCTRL_FUNC(SPI1CS1),
2337         ASPEED_PINCTRL_FUNC(SPI1DEBUG),
2338         ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
2339         ASPEED_PINCTRL_FUNC(SPI2CK),
2340         ASPEED_PINCTRL_FUNC(SPI2CS0),
2341         ASPEED_PINCTRL_FUNC(SPI2CS1),
2342         ASPEED_PINCTRL_FUNC(SPI2MISO),
2343         ASPEED_PINCTRL_FUNC(SPI2MOSI),
2344         ASPEED_PINCTRL_FUNC(TIMER3),
2345         ASPEED_PINCTRL_FUNC(TIMER4),
2346         ASPEED_PINCTRL_FUNC(TIMER5),
2347         ASPEED_PINCTRL_FUNC(TIMER6),
2348         ASPEED_PINCTRL_FUNC(TIMER7),
2349         ASPEED_PINCTRL_FUNC(TIMER8),
2350         ASPEED_PINCTRL_FUNC(TXD1),
2351         ASPEED_PINCTRL_FUNC(TXD2),
2352         ASPEED_PINCTRL_FUNC(TXD3),
2353         ASPEED_PINCTRL_FUNC(TXD4),
2354         ASPEED_PINCTRL_FUNC(UART6),
2355         ASPEED_PINCTRL_FUNC(USB11BHID),
2356         ASPEED_PINCTRL_FUNC(USB2AD),
2357         ASPEED_PINCTRL_FUNC(USB2AH),
2358         ASPEED_PINCTRL_FUNC(USB2BD),
2359         ASPEED_PINCTRL_FUNC(USB2BH),
2360         ASPEED_PINCTRL_FUNC(USBCKI),
2361         ASPEED_PINCTRL_FUNC(VGABIOSROM),
2362         ASPEED_PINCTRL_FUNC(VGAHS),
2363         ASPEED_PINCTRL_FUNC(VGAVS),
2364         ASPEED_PINCTRL_FUNC(VPI24),
2365         ASPEED_PINCTRL_FUNC(VPO),
2366         ASPEED_PINCTRL_FUNC(WDTRST1),
2367         ASPEED_PINCTRL_FUNC(WDTRST2),
2368 };
2369
2370 static struct aspeed_pin_config aspeed_g5_configs[] = {
2371         /* GPIOA, GPIOQ */
2372         { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 },
2373         { PIN_CONFIG_BIAS_DISABLE,   { B14, B13 }, SCU8C, 16 },
2374         { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 },
2375         { PIN_CONFIG_BIAS_DISABLE,   { A11, N20 }, SCU8C, 16 },
2376
2377         /* GPIOB, GPIOR */
2378         { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 },
2379         { PIN_CONFIG_BIAS_DISABLE,   { K19, H20 }, SCU8C, 17 },
2380         { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 },
2381         { PIN_CONFIG_BIAS_DISABLE,   { AA19, E10 }, SCU8C, 17 },
2382
2383         /* GPIOC, GPIOS*/
2384         { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 },
2385         { PIN_CONFIG_BIAS_DISABLE,   { C12, B11 }, SCU8C, 18 },
2386         { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 },
2387         { PIN_CONFIG_BIAS_DISABLE,   { V20, AA20 }, SCU8C, 18 },
2388
2389         /* GPIOD, GPIOY */
2390         { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 },
2391         { PIN_CONFIG_BIAS_DISABLE,   { F19, C21 }, SCU8C, 19 },
2392         { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 },
2393         { PIN_CONFIG_BIAS_DISABLE,   { R22, P20 }, SCU8C, 19 },
2394
2395         /* GPIOE, GPIOZ */
2396         { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 },
2397         { PIN_CONFIG_BIAS_DISABLE,   { B20, B19 }, SCU8C, 20 },
2398         { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 },
2399         { PIN_CONFIG_BIAS_DISABLE,   { Y20, W21 }, SCU8C, 20 },
2400
2401         /* GPIOF, GPIOAA */
2402         { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 },
2403         { PIN_CONFIG_BIAS_DISABLE,   { J19, H18 }, SCU8C, 21 },
2404         { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 },
2405         { PIN_CONFIG_BIAS_DISABLE,   { Y21, P19 }, SCU8C, 21 },
2406
2407         /* GPIOG, GPIOAB */
2408         { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 },
2409         { PIN_CONFIG_BIAS_DISABLE,   { A19, E14 }, SCU8C, 22 },
2410         { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 },
2411         { PIN_CONFIG_BIAS_DISABLE,   { N19, R20 }, SCU8C, 22 },
2412
2413         /* GPIOH, GPIOAC */
2414         { PIN_CONFIG_BIAS_PULL_DOWN, { A18,  D18  }, SCU8C, 23 },
2415         { PIN_CONFIG_BIAS_DISABLE,   { A18,  D18  }, SCU8C, 23 },
2416         { PIN_CONFIG_BIAS_PULL_DOWN, { G21,  G22  }, SCU8C, 23 },
2417         { PIN_CONFIG_BIAS_DISABLE,   { G21,  G22  }, SCU8C, 23 },
2418
2419         /* GPIOs [I, P] */
2420         { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },
2421         { PIN_CONFIG_BIAS_DISABLE,   { C18, A15 }, SCU8C, 24 },
2422         { PIN_CONFIG_BIAS_PULL_DOWN, { R2,  T3  }, SCU8C, 25 },
2423         { PIN_CONFIG_BIAS_DISABLE,   { R2,  T3  }, SCU8C, 25 },
2424         { PIN_CONFIG_BIAS_PULL_DOWN, { L3,  R1  }, SCU8C, 26 },
2425         { PIN_CONFIG_BIAS_DISABLE,   { L3,  R1  }, SCU8C, 26 },
2426         { PIN_CONFIG_BIAS_PULL_DOWN, { T2,  W1  }, SCU8C, 27 },
2427         { PIN_CONFIG_BIAS_DISABLE,   { T2,  W1  }, SCU8C, 27 },
2428         { PIN_CONFIG_BIAS_PULL_DOWN, { Y1,  T5  }, SCU8C, 28 },
2429         { PIN_CONFIG_BIAS_DISABLE,   { Y1,  T5  }, SCU8C, 28 },
2430         { PIN_CONFIG_BIAS_PULL_DOWN, { V2,  T4  }, SCU8C, 29 },
2431         { PIN_CONFIG_BIAS_DISABLE,   { V2,  T4  }, SCU8C, 29 },
2432         { PIN_CONFIG_BIAS_PULL_DOWN, { U5,  W4  }, SCU8C, 30 },
2433         { PIN_CONFIG_BIAS_DISABLE,   { U5,  W4  }, SCU8C, 30 },
2434         { PIN_CONFIG_BIAS_PULL_DOWN, { V4,  V6  }, SCU8C, 31 },
2435         { PIN_CONFIG_BIAS_DISABLE,   { V4,  V6  }, SCU8C, 31 },
2436
2437         /* GPIOs T[0-5] (RGMII1 Tx pins) */
2438         { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 },
2439         { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 },
2440         { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 },
2441         { PIN_CONFIG_BIAS_DISABLE,   { B5, D7 }, SCU90, 12 },
2442
2443         /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2444         { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 },
2445         { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 },
2446         { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 },
2447         { PIN_CONFIG_BIAS_DISABLE,   { B2, D4 }, SCU90, 14 },
2448
2449         /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2450         { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 },
2451         { PIN_CONFIG_BIAS_DISABLE,   { B4, C4 }, SCU90, 13 },
2452
2453         /* GPIOs V[2-7] (RGMII2 Rx pins) */
2454         { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 },
2455         { PIN_CONFIG_BIAS_DISABLE,   { C2, E6 }, SCU90, 15 },
2456
2457         /* ADC pull-downs (SCUA8[19:4]) */
2458         { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 },
2459         { PIN_CONFIG_BIAS_DISABLE,   { F4, F4 }, SCUA8, 4 },
2460         { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 },
2461         { PIN_CONFIG_BIAS_DISABLE,   { F5, F5 }, SCUA8, 5 },
2462         { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 },
2463         { PIN_CONFIG_BIAS_DISABLE,   { E2, E2 }, SCUA8, 6 },
2464         { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 },
2465         { PIN_CONFIG_BIAS_DISABLE,   { E1, E1 }, SCUA8, 7 },
2466         { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 },
2467         { PIN_CONFIG_BIAS_DISABLE,   { F3, F3 }, SCUA8, 8 },
2468         { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 },
2469         { PIN_CONFIG_BIAS_DISABLE,   { E3, E3 }, SCUA8, 9 },
2470         { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 },
2471         { PIN_CONFIG_BIAS_DISABLE,   { G5, G5 }, SCUA8, 10 },
2472         { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 },
2473         { PIN_CONFIG_BIAS_DISABLE,   { G4, G4 }, SCUA8, 11 },
2474         { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 },
2475         { PIN_CONFIG_BIAS_DISABLE,   { F2, F2 }, SCUA8, 12 },
2476         { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 },
2477         { PIN_CONFIG_BIAS_DISABLE,   { G3, G3 }, SCUA8, 13 },
2478         { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 },
2479         { PIN_CONFIG_BIAS_DISABLE,   { G2, G2 }, SCUA8, 14 },
2480         { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 },
2481         { PIN_CONFIG_BIAS_DISABLE,   { F1, F1 }, SCUA8, 15 },
2482         { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 },
2483         { PIN_CONFIG_BIAS_DISABLE,   { H5, H5 }, SCUA8, 16 },
2484         { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 },
2485         { PIN_CONFIG_BIAS_DISABLE,   { G1, G1 }, SCUA8, 17 },
2486         { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 },
2487         { PIN_CONFIG_BIAS_DISABLE,   { H3, H3 }, SCUA8, 18 },
2488         { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 },
2489         { PIN_CONFIG_BIAS_DISABLE,   { H4, H4 }, SCUA8, 19 },
2490
2491         /*
2492          * Debounce settings for GPIOs D and E passthrough mode are in
2493          * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
2494          * banks D and E is handled by the GPIO driver - GPIO passthrough is
2495          * treated like any other non-GPIO mux function. There is a catch
2496          * however, in that the debounce period is configured in the GPIO
2497          * controller. Due to this tangle between GPIO and pinctrl we don't yet
2498          * fully support pass-through debounce.
2499          */
2500         { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 },
2501         { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 },
2502         { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 },
2503         { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 },
2504         { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 },
2505         { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 },
2506         { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 },
2507         { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
2508 };
2509
2510 static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
2511                                                int ip)
2512 {
2513         if (ip == ASPEED_IP_SCU) {
2514                 WARN(!ctx->maps[ip], "Missing SCU syscon!");
2515                 return ctx->maps[ip];
2516         }
2517
2518         if (ip >= ASPEED_NR_PINMUX_IPS)
2519                 return ERR_PTR(-EINVAL);
2520
2521         if (likely(ctx->maps[ip]))
2522                 return ctx->maps[ip];
2523
2524         if (ip == ASPEED_IP_GFX) {
2525                 struct device_node *node;
2526                 struct regmap *map;
2527
2528                 node = of_parse_phandle(ctx->dev->of_node,
2529                                         "aspeed,external-nodes", 0);
2530                 if (node) {
2531                         map = syscon_node_to_regmap(node);
2532                         of_node_put(node);
2533                         if (IS_ERR(map))
2534                                 return map;
2535                 } else
2536                         return ERR_PTR(-ENODEV);
2537
2538                 ctx->maps[ASPEED_IP_GFX] = map;
2539                 dev_dbg(ctx->dev, "Acquired GFX regmap");
2540                 return map;
2541         }
2542
2543         if (ip == ASPEED_IP_LPC) {
2544                 struct device_node *node;
2545                 struct regmap *map;
2546
2547                 node = of_parse_phandle(ctx->dev->of_node,
2548                                         "aspeed,external-nodes", 1);
2549                 if (node) {
2550                         map = syscon_node_to_regmap(node->parent);
2551                         of_node_put(node);
2552                         if (IS_ERR(map))
2553                                 return map;
2554                 } else
2555                         map = ERR_PTR(-ENODEV);
2556
2557                 ctx->maps[ASPEED_IP_LPC] = map;
2558                 dev_dbg(ctx->dev, "Acquired LPC regmap");
2559                 return map;
2560         }
2561
2562         return ERR_PTR(-EINVAL);
2563 }
2564
2565 /**
2566  * Configure a pin's signal by applying an expression's descriptor state for
2567  * all descriptors in the expression.
2568  *
2569  * @ctx: The pinmux context
2570  * @expr: The expression associated with the function whose signal is to be
2571  *        configured
2572  * @enable: true to enable an function's signal through a pin's signal
2573  *          expression, false to disable the function's signal
2574  *
2575  * Return: 0 if the expression is configured as requested and a negative error
2576  * code otherwise
2577  */
2578 static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
2579                                   const struct aspeed_sig_expr *expr,
2580                                   bool enable)
2581 {
2582         int ret;
2583         int i;
2584
2585         for (i = 0; i < expr->ndescs; i++) {
2586                 const struct aspeed_sig_desc *desc = &expr->descs[i];
2587                 u32 pattern = enable ? desc->enable : desc->disable;
2588                 u32 val = (pattern << __ffs(desc->mask));
2589                 struct regmap *map;
2590
2591                 map = aspeed_g5_acquire_regmap(ctx, desc->ip);
2592                 if (IS_ERR(map)) {
2593                         dev_err(ctx->dev,
2594                                 "Failed to acquire regmap for IP block %d\n",
2595                                 desc->ip);
2596                         return PTR_ERR(map);
2597                 }
2598
2599                 /*
2600                  * Strap registers are configured in hardware or by early-boot
2601                  * firmware. Treat them as read-only despite that we can write
2602                  * them. This may mean that certain functions cannot be
2603                  * deconfigured and is the reason we re-evaluate after writing
2604                  * all descriptor bits.
2605                  *
2606                  * Port D and port E GPIO loopback modes are the only exception
2607                  * as those are commonly used with front-panel buttons to allow
2608                  * normal operation of the host when the BMC is powered off or
2609                  * fails to boot. Once the BMC has booted, the loopback mode
2610                  * must be disabled for the BMC to control host power-on and
2611                  * reset.
2612                  */
2613                 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
2614                     !(desc->mask & (BIT(21) | BIT(22))))
2615                         continue;
2616
2617                 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
2618                         continue;
2619
2620                 /* On AST2500, Set bits in SCU70 are cleared from SCU7C */
2621                 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
2622                         u32 value = ~val & desc->mask;
2623
2624                         if (value) {
2625                                 ret = regmap_write(ctx->maps[desc->ip],
2626                                                    HW_REVISION_ID, value);
2627                                 if (ret < 0)
2628                                         return ret;
2629                         }
2630                 }
2631
2632                 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
2633                                          desc->mask, val);
2634
2635                 if (ret)
2636                         return ret;
2637         }
2638
2639         ret = aspeed_sig_expr_eval(ctx, expr, enable);
2640         if (ret < 0)
2641                 return ret;
2642
2643         if (!ret)
2644                 return -EPERM;
2645
2646         return 0;
2647 }
2648
2649 static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2650         .set = aspeed_g5_sig_expr_set,
2651 };
2652
2653 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
2654         .pins = aspeed_g5_pins,
2655         .npins = ARRAY_SIZE(aspeed_g5_pins),
2656         .pinmux = {
2657                 .ops = &aspeed_g5_ops,
2658                 .groups = aspeed_g5_groups,
2659                 .ngroups = ARRAY_SIZE(aspeed_g5_groups),
2660                 .functions = aspeed_g5_functions,
2661                 .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
2662         },
2663         .configs = aspeed_g5_configs,
2664         .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
2665 };
2666
2667 static const struct pinmux_ops aspeed_g5_pinmux_ops = {
2668         .get_functions_count = aspeed_pinmux_get_fn_count,
2669         .get_function_name = aspeed_pinmux_get_fn_name,
2670         .get_function_groups = aspeed_pinmux_get_fn_groups,
2671         .set_mux = aspeed_pinmux_set_mux,
2672         .gpio_request_enable = aspeed_gpio_request_enable,
2673         .strict = true,
2674 };
2675
2676 static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
2677         .get_groups_count = aspeed_pinctrl_get_groups_count,
2678         .get_group_name = aspeed_pinctrl_get_group_name,
2679         .get_group_pins = aspeed_pinctrl_get_group_pins,
2680         .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
2681         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2682         .dt_free_map = pinctrl_utils_free_map,
2683 };
2684
2685 static const struct pinconf_ops aspeed_g5_conf_ops = {
2686         .is_generic = true,
2687         .pin_config_get = aspeed_pin_config_get,
2688         .pin_config_set = aspeed_pin_config_set,
2689         .pin_config_group_get = aspeed_pin_config_group_get,
2690         .pin_config_group_set = aspeed_pin_config_group_set,
2691 };
2692
2693 static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
2694         .name = "aspeed-g5-pinctrl",
2695         .pins = aspeed_g5_pins,
2696         .npins = ARRAY_SIZE(aspeed_g5_pins),
2697         .pctlops = &aspeed_g5_pinctrl_ops,
2698         .pmxops = &aspeed_g5_pinmux_ops,
2699         .confops = &aspeed_g5_conf_ops,
2700 };
2701
2702 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
2703 {
2704         int i;
2705
2706         for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
2707                 aspeed_g5_pins[i].number = i;
2708
2709         aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
2710
2711         return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
2712                         &aspeed_g5_pinctrl_data);
2713 }
2714
2715 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
2716         { .compatible = "aspeed,ast2500-pinctrl", },
2717         { .compatible = "aspeed,g5-pinctrl", },
2718         { },
2719 };
2720
2721 static struct platform_driver aspeed_g5_pinctrl_driver = {
2722         .probe = aspeed_g5_pinctrl_probe,
2723         .driver = {
2724                 .name = "aspeed-g5-pinctrl",
2725                 .of_match_table = aspeed_g5_pinctrl_of_match,
2726         },
2727 };
2728
2729 static int aspeed_g5_pinctrl_init(void)
2730 {
2731         return platform_driver_register(&aspeed_g5_pinctrl_driver);
2732 }
2733
2734 arch_initcall(aspeed_g5_pinctrl_init);