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bna: use device model DMA API
[linux/fpc-iii.git] / drivers / tty / serial / amba-pl011.c
blobe76d7d000128f9060a2993c7912cc8e18b70d6c2
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 * Copyright (C) 2010 ST-Ericsson SA
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * This is a generic driver for ARM AMBA-type serial ports. They
27 * have a lot of 16550-like features, but are not register compatible.
28 * Note that although they do have CTS, DCD and DSR inputs, they do
29 * not have an RI input, nor do they have DTR or RTS outputs. If
30 * required, these have to be supplied via some other means (eg, GPIO)
31 * and hooked into this driver.
32 */
33
34 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
35 #define SUPPORT_SYSRQ
36 #endif
37
38 #include <linux/module.h>
39 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/console.h>
42 #include <linux/sysrq.h>
43 #include <linux/device.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial_core.h>
47 #include <linux/serial.h>
48 #include <linux/amba/bus.h>
49 #include <linux/amba/serial.h>
50 #include <linux/clk.h>
51 #include <linux/slab.h>
52 #include <linux/dmaengine.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/scatterlist.h>
55
56 #include <asm/io.h>
57 #include <asm/sizes.h>
58
59 #define UART_NR 14
60
61 #define SERIAL_AMBA_MAJOR 204
62 #define SERIAL_AMBA_MINOR 64
63 #define SERIAL_AMBA_NR UART_NR
64
65 #define AMBA_ISR_PASS_LIMIT 256
66
67 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
68 #define UART_DUMMY_DR_RX (1 << 16)
69
70 /* There is by now at least one vendor with differing details, so handle it */
71 struct vendor_data {
72 unsigned int ifls;
73 unsigned int fifosize;
74 unsigned int lcrh_tx;
75 unsigned int lcrh_rx;
76 bool oversampling;
77 bool dma_threshold;
78 };
79
80 static struct vendor_data vendor_arm = {
81 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
82 .fifosize = 16,
83 .lcrh_tx = UART011_LCRH,
84 .lcrh_rx = UART011_LCRH,
85 .oversampling = false,
86 .dma_threshold = false,
87 };
88
89 static struct vendor_data vendor_st = {
90 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
91 .fifosize = 64,
92 .lcrh_tx = ST_UART011_LCRH_TX,
93 .lcrh_rx = ST_UART011_LCRH_RX,
94 .oversampling = true,
95 .dma_threshold = true,
96 };
97
98 /* Deals with DMA transactions */
99 struct pl011_dmatx_data {
100 struct dma_chan *chan;
101 struct scatterlist sg;
102 char *buf;
103 bool queued;
104 };
105
106 /*
107 * We wrap our port structure around the generic uart_port.
108 */
109 struct uart_amba_port {
110 struct uart_port port;
111 struct clk *clk;
112 const struct vendor_data *vendor;
113 unsigned int dmacr; /* dma control reg */
114 unsigned int im; /* interrupt mask */
115 unsigned int old_status;
116 unsigned int fifosize; /* vendor-specific */
117 unsigned int lcrh_tx; /* vendor-specific */
118 unsigned int lcrh_rx; /* vendor-specific */
119 bool autorts;
120 char type[12];
121 #ifdef CONFIG_DMA_ENGINE
122 /* DMA stuff */
123 bool using_dma;
124 struct pl011_dmatx_data dmatx;
125 #endif
126 };
127
128 /*
129 * All the DMA operation mode stuff goes inside this ifdef.
130 * This assumes that you have a generic DMA device interface,
131 * no custom DMA interfaces are supported.
132 */
133 #ifdef CONFIG_DMA_ENGINE
134
135 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
136
137 static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
138 {
139 /* DMA is the sole user of the platform data right now */
140 struct amba_pl011_data *plat = uap->port.dev->platform_data;
141 struct dma_slave_config tx_conf = {
142 .dst_addr = uap->port.mapbase + UART01x_DR,
143 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
144 .direction = DMA_TO_DEVICE,
145 .dst_maxburst = uap->fifosize >> 1,
146 };
147 struct dma_chan *chan;
148 dma_cap_mask_t mask;
149
150 /* We need platform data */
151 if (!plat || !plat->dma_filter) {
152 dev_info(uap->port.dev, "no DMA platform data\n");
153 return;
154 }
155
156 /* Try to acquire a generic DMA engine slave channel */
157 dma_cap_zero(mask);
158 dma_cap_set(DMA_SLAVE, mask);
159
160 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
161 if (!chan) {
162 dev_err(uap->port.dev, "no TX DMA channel!\n");
163 return;
164 }
165
166 dmaengine_slave_config(chan, &tx_conf);
167 uap->dmatx.chan = chan;
168
169 dev_info(uap->port.dev, "DMA channel TX %s\n",
170 dma_chan_name(uap->dmatx.chan));
171 }
172
173 #ifndef MODULE
174 /*
175 * Stack up the UARTs and let the above initcall be done at device
176 * initcall time, because the serial driver is called as an arch
177 * initcall, and at this time the DMA subsystem is not yet registered.
178 * At this point the driver will switch over to using DMA where desired.
179 */
180 struct dma_uap {
181 struct list_head node;
182 struct uart_amba_port *uap;
183 };
184
185 static LIST_HEAD(pl011_dma_uarts);
186
187 static int __init pl011_dma_initcall(void)
188 {
189 struct list_head *node, *tmp;
190
191 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
192 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
193 pl011_dma_probe_initcall(dmau->uap);
194 list_del(node);
195 kfree(dmau);
196 }
197 return 0;
198 }
199
200 device_initcall(pl011_dma_initcall);
201
202 static void pl011_dma_probe(struct uart_amba_port *uap)
203 {
204 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
205 if (dmau) {
206 dmau->uap = uap;
207 list_add_tail(&dmau->node, &pl011_dma_uarts);
208 }
209 }
210 #else
211 static void pl011_dma_probe(struct uart_amba_port *uap)
212 {
213 pl011_dma_probe_initcall(uap);
214 }
215 #endif
216
217 static void pl011_dma_remove(struct uart_amba_port *uap)
218 {
219 /* TODO: remove the initcall if it has not yet executed */
220 if (uap->dmatx.chan)
221 dma_release_channel(uap->dmatx.chan);
222 }
223
224
225 /* Forward declare this for the refill routine */
226 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
227
228 /*
229 * The current DMA TX buffer has been sent.
230 * Try to queue up another DMA buffer.
231 */
232 static void pl011_dma_tx_callback(void *data)
233 {
234 struct uart_amba_port *uap = data;
235 struct pl011_dmatx_data *dmatx = &uap->dmatx;
236 unsigned long flags;
237 u16 dmacr;
238
239 spin_lock_irqsave(&uap->port.lock, flags);
240 if (uap->dmatx.queued)
241 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
242 DMA_TO_DEVICE);
243
244 dmacr = uap->dmacr;
245 uap->dmacr = dmacr & ~UART011_TXDMAE;
246 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
247
248 /*
249 * If TX DMA was disabled, it means that we've stopped the DMA for
250 * some reason (eg, XOFF received, or we want to send an X-char.)
251 *
252 * Note: we need to be careful here of a potential race between DMA
253 * and the rest of the driver - if the driver disables TX DMA while
254 * a TX buffer completing, we must update the tx queued status to
255 * get further refills (hence we check dmacr).
256 */
257 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
258 uart_circ_empty(&uap->port.state->xmit)) {
259 uap->dmatx.queued = false;
260 spin_unlock_irqrestore(&uap->port.lock, flags);
261 return;
262 }
263
264 if (pl011_dma_tx_refill(uap) <= 0) {
265 /*
266 * We didn't queue a DMA buffer for some reason, but we
267 * have data pending to be sent. Re-enable the TX IRQ.
268 */
269 uap->im |= UART011_TXIM;
270 writew(uap->im, uap->port.membase + UART011_IMSC);
271 }
272 spin_unlock_irqrestore(&uap->port.lock, flags);
273 }
274
275 /*
276 * Try to refill the TX DMA buffer.
277 * Locking: called with port lock held and IRQs disabled.
278 * Returns:
279 * 1 if we queued up a TX DMA buffer.
280 * 0 if we didn't want to handle this by DMA
281 * <0 on error
282 */
283 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
284 {
285 struct pl011_dmatx_data *dmatx = &uap->dmatx;
286 struct dma_chan *chan = dmatx->chan;
287 struct dma_device *dma_dev = chan->device;
288 struct dma_async_tx_descriptor *desc;
289 struct circ_buf *xmit = &uap->port.state->xmit;
290 unsigned int count;
291
292 /*
293 * Try to avoid the overhead involved in using DMA if the
294 * transaction fits in the first half of the FIFO, by using
295 * the standard interrupt handling. This ensures that we
296 * issue a uart_write_wakeup() at the appropriate time.
297 */
298 count = uart_circ_chars_pending(xmit);
299 if (count < (uap->fifosize >> 1)) {
300 uap->dmatx.queued = false;
301 return 0;
302 }
303
304 /*
305 * Bodge: don't send the last character by DMA, as this
306 * will prevent XON from notifying us to restart DMA.
307 */
308 count -= 1;
309
310 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
311 if (count > PL011_DMA_BUFFER_SIZE)
312 count = PL011_DMA_BUFFER_SIZE;
313
314 if (xmit->tail < xmit->head)
315 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
316 else {
317 size_t first = UART_XMIT_SIZE - xmit->tail;
318 size_t second = xmit->head;
319
320 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
321 if (second)
322 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
323 }
324
325 dmatx->sg.length = count;
326
327 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
328 uap->dmatx.queued = false;
329 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
330 return -EBUSY;
331 }
332
333 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
334 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
335 if (!desc) {
336 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
337 uap->dmatx.queued = false;
338 /*
339 * If DMA cannot be used right now, we complete this
340 * transaction via IRQ and let the TTY layer retry.
341 */
342 dev_dbg(uap->port.dev, "TX DMA busy\n");
343 return -EBUSY;
344 }
345
346 /* Some data to go along to the callback */
347 desc->callback = pl011_dma_tx_callback;
348 desc->callback_param = uap;
349
350 /* All errors should happen at prepare time */
351 dmaengine_submit(desc);
352
353 /* Fire the DMA transaction */
354 dma_dev->device_issue_pending(chan);
355
356 uap->dmacr |= UART011_TXDMAE;
357 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
358 uap->dmatx.queued = true;
359
360 /*
361 * Now we know that DMA will fire, so advance the ring buffer
362 * with the stuff we just dispatched.
363 */
364 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
365 uap->port.icount.tx += count;
366
367 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
368 uart_write_wakeup(&uap->port);
369
370 return 1;
371 }
372
373 /*
374 * We received a transmit interrupt without a pending X-char but with
375 * pending characters.
376 * Locking: called with port lock held and IRQs disabled.
377 * Returns:
378 * false if we want to use PIO to transmit
379 * true if we queued a DMA buffer
380 */
381 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
382 {
383 if (!uap->using_dma)
384 return false;
385
386 /*
387 * If we already have a TX buffer queued, but received a
388 * TX interrupt, it will be because we've just sent an X-char.
389 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
390 */
391 if (uap->dmatx.queued) {
392 uap->dmacr |= UART011_TXDMAE;
393 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
394 uap->im &= ~UART011_TXIM;
395 writew(uap->im, uap->port.membase + UART011_IMSC);
396 return true;
397 }
398
399 /*
400 * We don't have a TX buffer queued, so try to queue one.
401 * If we succesfully queued a buffer, mask the TX IRQ.
402 */
403 if (pl011_dma_tx_refill(uap) > 0) {
404 uap->im &= ~UART011_TXIM;
405 writew(uap->im, uap->port.membase + UART011_IMSC);
406 return true;
407 }
408 return false;
409 }
410
411 /*
412 * Stop the DMA transmit (eg, due to received XOFF).
413 * Locking: called with port lock held and IRQs disabled.
414 */
415 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
416 {
417 if (uap->dmatx.queued) {
418 uap->dmacr &= ~UART011_TXDMAE;
419 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
420 }
421 }
422
423 /*
424 * Try to start a DMA transmit, or in the case of an XON/OFF
425 * character queued for send, try to get that character out ASAP.
426 * Locking: called with port lock held and IRQs disabled.
427 * Returns:
428 * false if we want the TX IRQ to be enabled
429 * true if we have a buffer queued
430 */
431 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
432 {
433 u16 dmacr;
434
435 if (!uap->using_dma)
436 return false;
437
438 if (!uap->port.x_char) {
439 /* no X-char, try to push chars out in DMA mode */
440 bool ret = true;
441
442 if (!uap->dmatx.queued) {
443 if (pl011_dma_tx_refill(uap) > 0) {
444 uap->im &= ~UART011_TXIM;
445 ret = true;
446 } else {
447 uap->im |= UART011_TXIM;
448 ret = false;
449 }
450 writew(uap->im, uap->port.membase + UART011_IMSC);
451 } else if (!(uap->dmacr & UART011_TXDMAE)) {
452 uap->dmacr |= UART011_TXDMAE;
453 writew(uap->dmacr,
454 uap->port.membase + UART011_DMACR);
455 }
456 return ret;
457 }
458
459 /*
460 * We have an X-char to send. Disable DMA to prevent it loading
461 * the TX fifo, and then see if we can stuff it into the FIFO.
462 */
463 dmacr = uap->dmacr;
464 uap->dmacr &= ~UART011_TXDMAE;
465 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
466
467 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
468 /*
469 * No space in the FIFO, so enable the transmit interrupt
470 * so we know when there is space. Note that once we've
471 * loaded the character, we should just re-enable DMA.
472 */
473 return false;
474 }
475
476 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
477 uap->port.icount.tx++;
478 uap->port.x_char = 0;
479
480 /* Success - restore the DMA state */
481 uap->dmacr = dmacr;
482 writew(dmacr, uap->port.membase + UART011_DMACR);
483
484 return true;
485 }
486
487 /*
488 * Flush the transmit buffer.
489 * Locking: called with port lock held and IRQs disabled.
490 */
491 static void pl011_dma_flush_buffer(struct uart_port *port)
492 {
493 struct uart_amba_port *uap = (struct uart_amba_port *)port;
494
495 if (!uap->using_dma)
496 return;
497
498 /* Avoid deadlock with the DMA engine callback */
499 spin_unlock(&uap->port.lock);
500 dmaengine_terminate_all(uap->dmatx.chan);
501 spin_lock(&uap->port.lock);
502 if (uap->dmatx.queued) {
503 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
504 DMA_TO_DEVICE);
505 uap->dmatx.queued = false;
506 uap->dmacr &= ~UART011_TXDMAE;
507 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
508 }
509 }
510
511
512 static void pl011_dma_startup(struct uart_amba_port *uap)
513 {
514 if (!uap->dmatx.chan)
515 return;
516
517 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
518 if (!uap->dmatx.buf) {
519 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
520 uap->port.fifosize = uap->fifosize;
521 return;
522 }
523
524 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
525
526 /* The DMA buffer is now the FIFO the TTY subsystem can use */
527 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
528 uap->using_dma = true;
529
530 /* Turn on DMA error (RX/TX will be enabled on demand) */
531 uap->dmacr |= UART011_DMAONERR;
532 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
533
534 /*
535 * ST Micro variants has some specific dma burst threshold
536 * compensation. Set this to 16 bytes, so burst will only
537 * be issued above/below 16 bytes.
538 */
539 if (uap->vendor->dma_threshold)
540 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
541 uap->port.membase + ST_UART011_DMAWM);
542 }
543
544 static void pl011_dma_shutdown(struct uart_amba_port *uap)
545 {
546 if (!uap->using_dma)
547 return;
548
549 /* Disable RX and TX DMA */
550 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
551 barrier();
552
553 spin_lock_irq(&uap->port.lock);
554 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
555 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
556 spin_unlock_irq(&uap->port.lock);
557
558 /* In theory, this should already be done by pl011_dma_flush_buffer */
559 dmaengine_terminate_all(uap->dmatx.chan);
560 if (uap->dmatx.queued) {
561 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
562 DMA_TO_DEVICE);
563 uap->dmatx.queued = false;
564 }
565
566 kfree(uap->dmatx.buf);
567
568 uap->using_dma = false;
569 }
570
571 #else
572 /* Blank functions if the DMA engine is not available */
573 static inline void pl011_dma_probe(struct uart_amba_port *uap)
574 {
575 }
576
577 static inline void pl011_dma_remove(struct uart_amba_port *uap)
578 {
579 }
580
581 static inline void pl011_dma_startup(struct uart_amba_port *uap)
582 {
583 }
584
585 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
586 {
587 }
588
589 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
590 {
591 return false;
592 }
593
594 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
595 {
596 }
597
598 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
599 {
600 return false;
601 }
602
603 #define pl011_dma_flush_buffer NULL
604 #endif
605
606
607 static void pl011_stop_tx(struct uart_port *port)
608 {
609 struct uart_amba_port *uap = (struct uart_amba_port *)port;
610
611 uap->im &= ~UART011_TXIM;
612 writew(uap->im, uap->port.membase + UART011_IMSC);
613 pl011_dma_tx_stop(uap);
614 }
615
616 static void pl011_start_tx(struct uart_port *port)
617 {
618 struct uart_amba_port *uap = (struct uart_amba_port *)port;
619
620 if (!pl011_dma_tx_start(uap)) {
621 uap->im |= UART011_TXIM;
622 writew(uap->im, uap->port.membase + UART011_IMSC);
623 }
624 }
625
626 static void pl011_stop_rx(struct uart_port *port)
627 {
628 struct uart_amba_port *uap = (struct uart_amba_port *)port;
629
630 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
631 UART011_PEIM|UART011_BEIM|UART011_OEIM);
632 writew(uap->im, uap->port.membase + UART011_IMSC);
633 }
634
635 static void pl011_enable_ms(struct uart_port *port)
636 {
637 struct uart_amba_port *uap = (struct uart_amba_port *)port;
638
639 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
640 writew(uap->im, uap->port.membase + UART011_IMSC);
641 }
642
643 static void pl011_rx_chars(struct uart_amba_port *uap)
644 {
645 struct tty_struct *tty = uap->port.state->port.tty;
646 unsigned int status, ch, flag, max_count = 256;
647
648 status = readw(uap->port.membase + UART01x_FR);
649 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
650 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
651 flag = TTY_NORMAL;
652 uap->port.icount.rx++;
653
654 /*
655 * Note that the error handling code is
656 * out of the main execution path
657 */
658 if (unlikely(ch & UART_DR_ERROR)) {
659 if (ch & UART011_DR_BE) {
660 ch &= ~(UART011_DR_FE | UART011_DR_PE);
661 uap->port.icount.brk++;
662 if (uart_handle_break(&uap->port))
663 goto ignore_char;
664 } else if (ch & UART011_DR_PE)
665 uap->port.icount.parity++;
666 else if (ch & UART011_DR_FE)
667 uap->port.icount.frame++;
668 if (ch & UART011_DR_OE)
669 uap->port.icount.overrun++;
670
671 ch &= uap->port.read_status_mask;
672
673 if (ch & UART011_DR_BE)
674 flag = TTY_BREAK;
675 else if (ch & UART011_DR_PE)
676 flag = TTY_PARITY;
677 else if (ch & UART011_DR_FE)
678 flag = TTY_FRAME;
679 }
680
681 if (uart_handle_sysrq_char(&uap->port, ch & 255))
682 goto ignore_char;
683
684 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
685
686 ignore_char:
687 status = readw(uap->port.membase + UART01x_FR);
688 }
689 spin_unlock(&uap->port.lock);
690 tty_flip_buffer_push(tty);
691 spin_lock(&uap->port.lock);
692 }
693
694 static void pl011_tx_chars(struct uart_amba_port *uap)
695 {
696 struct circ_buf *xmit = &uap->port.state->xmit;
697 int count;
698
699 if (uap->port.x_char) {
700 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
701 uap->port.icount.tx++;
702 uap->port.x_char = 0;
703 return;
704 }
705 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
706 pl011_stop_tx(&uap->port);
707 return;
708 }
709
710 /* If we are using DMA mode, try to send some characters. */
711 if (pl011_dma_tx_irq(uap))
712 return;
713
714 count = uap->fifosize >> 1;
715 do {
716 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
717 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
718 uap->port.icount.tx++;
719 if (uart_circ_empty(xmit))
720 break;
721 } while (--count > 0);
722
723 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
724 uart_write_wakeup(&uap->port);
725
726 if (uart_circ_empty(xmit))
727 pl011_stop_tx(&uap->port);
728 }
729
730 static void pl011_modem_status(struct uart_amba_port *uap)
731 {
732 unsigned int status, delta;
733
734 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
735
736 delta = status ^ uap->old_status;
737 uap->old_status = status;
738
739 if (!delta)
740 return;
741
742 if (delta & UART01x_FR_DCD)
743 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
744
745 if (delta & UART01x_FR_DSR)
746 uap->port.icount.dsr++;
747
748 if (delta & UART01x_FR_CTS)
749 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
750
751 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
752 }
753
754 static irqreturn_t pl011_int(int irq, void *dev_id)
755 {
756 struct uart_amba_port *uap = dev_id;
757 unsigned long flags;
758 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
759 int handled = 0;
760
761 spin_lock_irqsave(&uap->port.lock, flags);
762
763 status = readw(uap->port.membase + UART011_MIS);
764 if (status) {
765 do {
766 writew(status & ~(UART011_TXIS|UART011_RTIS|
767 UART011_RXIS),
768 uap->port.membase + UART011_ICR);
769
770 if (status & (UART011_RTIS|UART011_RXIS))
771 pl011_rx_chars(uap);
772 if (status & (UART011_DSRMIS|UART011_DCDMIS|
773 UART011_CTSMIS|UART011_RIMIS))
774 pl011_modem_status(uap);
775 if (status & UART011_TXIS)
776 pl011_tx_chars(uap);
777
778 if (pass_counter-- == 0)
779 break;
780
781 status = readw(uap->port.membase + UART011_MIS);
782 } while (status != 0);
783 handled = 1;
784 }
785
786 spin_unlock_irqrestore(&uap->port.lock, flags);
787
788 return IRQ_RETVAL(handled);
789 }
790
791 static unsigned int pl01x_tx_empty(struct uart_port *port)
792 {
793 struct uart_amba_port *uap = (struct uart_amba_port *)port;
794 unsigned int status = readw(uap->port.membase + UART01x_FR);
795 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
796 }
797
798 static unsigned int pl01x_get_mctrl(struct uart_port *port)
799 {
800 struct uart_amba_port *uap = (struct uart_amba_port *)port;
801 unsigned int result = 0;
802 unsigned int status = readw(uap->port.membase + UART01x_FR);
803
804 #define TIOCMBIT(uartbit, tiocmbit) \
805 if (status & uartbit) \
806 result |= tiocmbit
807
808 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
809 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
810 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
811 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
812 #undef TIOCMBIT
813 return result;
814 }
815
816 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
817 {
818 struct uart_amba_port *uap = (struct uart_amba_port *)port;
819 unsigned int cr;
820
821 cr = readw(uap->port.membase + UART011_CR);
822
823 #define TIOCMBIT(tiocmbit, uartbit) \
824 if (mctrl & tiocmbit) \
825 cr |= uartbit; \
826 else \
827 cr &= ~uartbit
828
829 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
830 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
831 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
832 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
833 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
834
835 if (uap->autorts) {
836 /* We need to disable auto-RTS if we want to turn RTS off */
837 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
838 }
839 #undef TIOCMBIT
840
841 writew(cr, uap->port.membase + UART011_CR);
842 }
843
844 static void pl011_break_ctl(struct uart_port *port, int break_state)
845 {
846 struct uart_amba_port *uap = (struct uart_amba_port *)port;
847 unsigned long flags;
848 unsigned int lcr_h;
849
850 spin_lock_irqsave(&uap->port.lock, flags);
851 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
852 if (break_state == -1)
853 lcr_h |= UART01x_LCRH_BRK;
854 else
855 lcr_h &= ~UART01x_LCRH_BRK;
856 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
857 spin_unlock_irqrestore(&uap->port.lock, flags);
858 }
859
860 #ifdef CONFIG_CONSOLE_POLL
861 static int pl010_get_poll_char(struct uart_port *port)
862 {
863 struct uart_amba_port *uap = (struct uart_amba_port *)port;
864 unsigned int status;
865
866 status = readw(uap->port.membase + UART01x_FR);
867 if (status & UART01x_FR_RXFE)
868 return NO_POLL_CHAR;
869
870 return readw(uap->port.membase + UART01x_DR);
871 }
872
873 static void pl010_put_poll_char(struct uart_port *port,
874 unsigned char ch)
875 {
876 struct uart_amba_port *uap = (struct uart_amba_port *)port;
877
878 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
879 barrier();
880
881 writew(ch, uap->port.membase + UART01x_DR);
882 }
883
884 #endif /* CONFIG_CONSOLE_POLL */
885
886 static int pl011_startup(struct uart_port *port)
887 {
888 struct uart_amba_port *uap = (struct uart_amba_port *)port;
889 unsigned int cr;
890 int retval;
891
892 /*
893 * Try to enable the clock producer.
894 */
895 retval = clk_enable(uap->clk);
896 if (retval)
897 goto out;
898
899 uap->port.uartclk = clk_get_rate(uap->clk);
900
901 /*
902 * Allocate the IRQ
903 */
904 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
905 if (retval)
906 goto clk_dis;
907
908 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
909
910 /*
911 * Provoke TX FIFO interrupt into asserting.
912 */
913 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
914 writew(cr, uap->port.membase + UART011_CR);
915 writew(0, uap->port.membase + UART011_FBRD);
916 writew(1, uap->port.membase + UART011_IBRD);
917 writew(0, uap->port.membase + uap->lcrh_rx);
918 if (uap->lcrh_tx != uap->lcrh_rx) {
919 int i;
920 /*
921 * Wait 10 PCLKs before writing LCRH_TX register,
922 * to get this delay write read only register 10 times
923 */
924 for (i = 0; i < 10; ++i)
925 writew(0xff, uap->port.membase + UART011_MIS);
926 writew(0, uap->port.membase + uap->lcrh_tx);
927 }
928 writew(0, uap->port.membase + UART01x_DR);
929 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
930 barrier();
931
932 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
933 writew(cr, uap->port.membase + UART011_CR);
934
935 /* Clear pending error interrupts */
936 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
937 uap->port.membase + UART011_ICR);
938
939 /*
940 * initialise the old status of the modem signals
941 */
942 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
943
944 /* Startup DMA */
945 pl011_dma_startup(uap);
946
947 /*
948 * Finally, enable interrupts
949 */
950 spin_lock_irq(&uap->port.lock);
951 uap->im = UART011_RXIM | UART011_RTIM;
952 writew(uap->im, uap->port.membase + UART011_IMSC);
953 spin_unlock_irq(&uap->port.lock);
954
955 return 0;
956
957 clk_dis:
958 clk_disable(uap->clk);
959 out:
960 return retval;
961 }
962
963 static void pl011_shutdown_channel(struct uart_amba_port *uap,
964 unsigned int lcrh)
965 {
966 unsigned long val;
967
968 val = readw(uap->port.membase + lcrh);
969 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
970 writew(val, uap->port.membase + lcrh);
971 }
972
973 static void pl011_shutdown(struct uart_port *port)
974 {
975 struct uart_amba_port *uap = (struct uart_amba_port *)port;
976
977 /*
978 * disable all interrupts
979 */
980 spin_lock_irq(&uap->port.lock);
981 uap->im = 0;
982 writew(uap->im, uap->port.membase + UART011_IMSC);
983 writew(0xffff, uap->port.membase + UART011_ICR);
984 spin_unlock_irq(&uap->port.lock);
985
986 pl011_dma_shutdown(uap);
987
988 /*
989 * Free the interrupt
990 */
991 free_irq(uap->port.irq, uap);
992
993 /*
994 * disable the port
995 */
996 uap->autorts = false;
997 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
998
999 /*
1000 * disable break condition and fifos
1001 */
1002 pl011_shutdown_channel(uap, uap->lcrh_rx);
1003 if (uap->lcrh_rx != uap->lcrh_tx)
1004 pl011_shutdown_channel(uap, uap->lcrh_tx);
1005
1006 /*
1007 * Shut down the clock producer
1008 */
1009 clk_disable(uap->clk);
1010 }
1011
1012 static void
1013 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1014 struct ktermios *old)
1015 {
1016 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1017 unsigned int lcr_h, old_cr;
1018 unsigned long flags;
1019 unsigned int baud, quot, clkdiv;
1020
1021 if (uap->vendor->oversampling)
1022 clkdiv = 8;
1023 else
1024 clkdiv = 16;
1025
1026 /*
1027 * Ask the core to calculate the divisor for us.
1028 */
1029 baud = uart_get_baud_rate(port, termios, old, 0,
1030 port->uartclk / clkdiv);
1031
1032 if (baud > port->uartclk/16)
1033 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1034 else
1035 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1036
1037 switch (termios->c_cflag & CSIZE) {
1038 case CS5:
1039 lcr_h = UART01x_LCRH_WLEN_5;
1040 break;
1041 case CS6:
1042 lcr_h = UART01x_LCRH_WLEN_6;
1043 break;
1044 case CS7:
1045 lcr_h = UART01x_LCRH_WLEN_7;
1046 break;
1047 default: // CS8
1048 lcr_h = UART01x_LCRH_WLEN_8;
1049 break;
1050 }
1051 if (termios->c_cflag & CSTOPB)
1052 lcr_h |= UART01x_LCRH_STP2;
1053 if (termios->c_cflag & PARENB) {
1054 lcr_h |= UART01x_LCRH_PEN;
1055 if (!(termios->c_cflag & PARODD))
1056 lcr_h |= UART01x_LCRH_EPS;
1057 }
1058 if (uap->fifosize > 1)
1059 lcr_h |= UART01x_LCRH_FEN;
1060
1061 spin_lock_irqsave(&port->lock, flags);
1062
1063 /*
1064 * Update the per-port timeout.
1065 */
1066 uart_update_timeout(port, termios->c_cflag, baud);
1067
1068 port->read_status_mask = UART011_DR_OE | 255;
1069 if (termios->c_iflag & INPCK)
1070 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1071 if (termios->c_iflag & (BRKINT | PARMRK))
1072 port->read_status_mask |= UART011_DR_BE;
1073
1074 /*
1075 * Characters to ignore
1076 */
1077 port->ignore_status_mask = 0;
1078 if (termios->c_iflag & IGNPAR)
1079 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1080 if (termios->c_iflag & IGNBRK) {
1081 port->ignore_status_mask |= UART011_DR_BE;
1082 /*
1083 * If we're ignoring parity and break indicators,
1084 * ignore overruns too (for real raw support).
1085 */
1086 if (termios->c_iflag & IGNPAR)
1087 port->ignore_status_mask |= UART011_DR_OE;
1088 }
1089
1090 /*
1091 * Ignore all characters if CREAD is not set.
1092 */
1093 if ((termios->c_cflag & CREAD) == 0)
1094 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1095
1096 if (UART_ENABLE_MS(port, termios->c_cflag))
1097 pl011_enable_ms(port);
1098
1099 /* first, disable everything */
1100 old_cr = readw(port->membase + UART011_CR);
1101 writew(0, port->membase + UART011_CR);
1102
1103 if (termios->c_cflag & CRTSCTS) {
1104 if (old_cr & UART011_CR_RTS)
1105 old_cr |= UART011_CR_RTSEN;
1106
1107 old_cr |= UART011_CR_CTSEN;
1108 uap->autorts = true;
1109 } else {
1110 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1111 uap->autorts = false;
1112 }
1113
1114 if (uap->vendor->oversampling) {
1115 if (baud > port->uartclk / 16)
1116 old_cr |= ST_UART011_CR_OVSFACT;
1117 else
1118 old_cr &= ~ST_UART011_CR_OVSFACT;
1119 }
1120
1121 /* Set baud rate */
1122 writew(quot & 0x3f, port->membase + UART011_FBRD);
1123 writew(quot >> 6, port->membase + UART011_IBRD);
1124
1125 /*
1126 * ----------v----------v----------v----------v-----
1127 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1128 * ----------^----------^----------^----------^-----
1129 */
1130 writew(lcr_h, port->membase + uap->lcrh_rx);
1131 if (uap->lcrh_rx != uap->lcrh_tx) {
1132 int i;
1133 /*
1134 * Wait 10 PCLKs before writing LCRH_TX register,
1135 * to get this delay write read only register 10 times
1136 */
1137 for (i = 0; i < 10; ++i)
1138 writew(0xff, uap->port.membase + UART011_MIS);
1139 writew(lcr_h, port->membase + uap->lcrh_tx);
1140 }
1141 writew(old_cr, port->membase + UART011_CR);
1142
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 }
1145
1146 static const char *pl011_type(struct uart_port *port)
1147 {
1148 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1149 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1150 }
1151
1152 /*
1153 * Release the memory region(s) being used by 'port'
1154 */
1155 static void pl010_release_port(struct uart_port *port)
1156 {
1157 release_mem_region(port->mapbase, SZ_4K);
1158 }
1159
1160 /*
1161 * Request the memory region(s) being used by 'port'
1162 */
1163 static int pl010_request_port(struct uart_port *port)
1164 {
1165 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1166 != NULL ? 0 : -EBUSY;
1167 }
1168
1169 /*
1170 * Configure/autoconfigure the port.
1171 */
1172 static void pl010_config_port(struct uart_port *port, int flags)
1173 {
1174 if (flags & UART_CONFIG_TYPE) {
1175 port->type = PORT_AMBA;
1176 pl010_request_port(port);
1177 }
1178 }
1179
1180 /*
1181 * verify the new serial_struct (for TIOCSSERIAL).
1182 */
1183 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1184 {
1185 int ret = 0;
1186 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1187 ret = -EINVAL;
1188 if (ser->irq < 0 || ser->irq >= nr_irqs)
1189 ret = -EINVAL;
1190 if (ser->baud_base < 9600)
1191 ret = -EINVAL;
1192 return ret;
1193 }
1194
1195 static struct uart_ops amba_pl011_pops = {
1196 .tx_empty = pl01x_tx_empty,
1197 .set_mctrl = pl011_set_mctrl,
1198 .get_mctrl = pl01x_get_mctrl,
1199 .stop_tx = pl011_stop_tx,
1200 .start_tx = pl011_start_tx,
1201 .stop_rx = pl011_stop_rx,
1202 .enable_ms = pl011_enable_ms,
1203 .break_ctl = pl011_break_ctl,
1204 .startup = pl011_startup,
1205 .shutdown = pl011_shutdown,
1206 .flush_buffer = pl011_dma_flush_buffer,
1207 .set_termios = pl011_set_termios,
1208 .type = pl011_type,
1209 .release_port = pl010_release_port,
1210 .request_port = pl010_request_port,
1211 .config_port = pl010_config_port,
1212 .verify_port = pl010_verify_port,
1213 #ifdef CONFIG_CONSOLE_POLL
1214 .poll_get_char = pl010_get_poll_char,
1215 .poll_put_char = pl010_put_poll_char,
1216 #endif
1217 };
1218
1219 static struct uart_amba_port *amba_ports[UART_NR];
1220
1221 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1222
1223 static void pl011_console_putchar(struct uart_port *port, int ch)
1224 {
1225 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1226
1227 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1228 barrier();
1229 writew(ch, uap->port.membase + UART01x_DR);
1230 }
1231
1232 static void
1233 pl011_console_write(struct console *co, const char *s, unsigned int count)
1234 {
1235 struct uart_amba_port *uap = amba_ports[co->index];
1236 unsigned int status, old_cr, new_cr;
1237
1238 clk_enable(uap->clk);
1239
1240 /*
1241 * First save the CR then disable the interrupts
1242 */
1243 old_cr = readw(uap->port.membase + UART011_CR);
1244 new_cr = old_cr & ~UART011_CR_CTSEN;
1245 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1246 writew(new_cr, uap->port.membase + UART011_CR);
1247
1248 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1249
1250 /*
1251 * Finally, wait for transmitter to become empty
1252 * and restore the TCR
1253 */
1254 do {
1255 status = readw(uap->port.membase + UART01x_FR);
1256 } while (status & UART01x_FR_BUSY);
1257 writew(old_cr, uap->port.membase + UART011_CR);
1258
1259 clk_disable(uap->clk);
1260 }
1261
1262 static void __init
1263 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1264 int *parity, int *bits)
1265 {
1266 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1267 unsigned int lcr_h, ibrd, fbrd;
1268
1269 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1270
1271 *parity = 'n';
1272 if (lcr_h & UART01x_LCRH_PEN) {
1273 if (lcr_h & UART01x_LCRH_EPS)
1274 *parity = 'e';
1275 else
1276 *parity = 'o';
1277 }
1278
1279 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1280 *bits = 7;
1281 else
1282 *bits = 8;
1283
1284 ibrd = readw(uap->port.membase + UART011_IBRD);
1285 fbrd = readw(uap->port.membase + UART011_FBRD);
1286
1287 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1288
1289 if (uap->vendor->oversampling) {
1290 if (readw(uap->port.membase + UART011_CR)
1291 & ST_UART011_CR_OVSFACT)
1292 *baud *= 2;
1293 }
1294 }
1295 }
1296
1297 static int __init pl011_console_setup(struct console *co, char *options)
1298 {
1299 struct uart_amba_port *uap;
1300 int baud = 38400;
1301 int bits = 8;
1302 int parity = 'n';
1303 int flow = 'n';
1304
1305 /*
1306 * Check whether an invalid uart number has been specified, and
1307 * if so, search for the first available port that does have
1308 * console support.
1309 */
1310 if (co->index >= UART_NR)
1311 co->index = 0;
1312 uap = amba_ports[co->index];
1313 if (!uap)
1314 return -ENODEV;
1315
1316 uap->port.uartclk = clk_get_rate(uap->clk);
1317
1318 if (options)
1319 uart_parse_options(options, &baud, &parity, &bits, &flow);
1320 else
1321 pl011_console_get_options(uap, &baud, &parity, &bits);
1322
1323 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1324 }
1325
1326 static struct uart_driver amba_reg;
1327 static struct console amba_console = {
1328 .name = "ttyAMA",
1329 .write = pl011_console_write,
1330 .device = uart_console_device,
1331 .setup = pl011_console_setup,
1332 .flags = CON_PRINTBUFFER,
1333 .index = -1,
1334 .data = &amba_reg,
1335 };
1336
1337 #define AMBA_CONSOLE (&amba_console)
1338 #else
1339 #define AMBA_CONSOLE NULL
1340 #endif
1341
1342 static struct uart_driver amba_reg = {
1343 .owner = THIS_MODULE,
1344 .driver_name = "ttyAMA",
1345 .dev_name = "ttyAMA",
1346 .major = SERIAL_AMBA_MAJOR,
1347 .minor = SERIAL_AMBA_MINOR,
1348 .nr = UART_NR,
1349 .cons = AMBA_CONSOLE,
1350 };
1351
1352 static int pl011_probe(struct amba_device *dev, struct amba_id *id)
1353 {
1354 struct uart_amba_port *uap;
1355 struct vendor_data *vendor = id->data;
1356 void __iomem *base;
1357 int i, ret;
1358
1359 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1360 if (amba_ports[i] == NULL)
1361 break;
1362
1363 if (i == ARRAY_SIZE(amba_ports)) {
1364 ret = -EBUSY;
1365 goto out;
1366 }
1367
1368 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1369 if (uap == NULL) {
1370 ret = -ENOMEM;
1371 goto out;
1372 }
1373
1374 base = ioremap(dev->res.start, resource_size(&dev->res));
1375 if (!base) {
1376 ret = -ENOMEM;
1377 goto free;
1378 }
1379
1380 uap->clk = clk_get(&dev->dev, NULL);
1381 if (IS_ERR(uap->clk)) {
1382 ret = PTR_ERR(uap->clk);
1383 goto unmap;
1384 }
1385
1386 uap->vendor = vendor;
1387 uap->lcrh_rx = vendor->lcrh_rx;
1388 uap->lcrh_tx = vendor->lcrh_tx;
1389 uap->fifosize = vendor->fifosize;
1390 uap->port.dev = &dev->dev;
1391 uap->port.mapbase = dev->res.start;
1392 uap->port.membase = base;
1393 uap->port.iotype = UPIO_MEM;
1394 uap->port.irq = dev->irq[0];
1395 uap->port.fifosize = uap->fifosize;
1396 uap->port.ops = &amba_pl011_pops;
1397 uap->port.flags = UPF_BOOT_AUTOCONF;
1398 uap->port.line = i;
1399 pl011_dma_probe(uap);
1400
1401 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1402
1403 amba_ports[i] = uap;
1404
1405 amba_set_drvdata(dev, uap);
1406 ret = uart_add_one_port(&amba_reg, &uap->port);
1407 if (ret) {
1408 amba_set_drvdata(dev, NULL);
1409 amba_ports[i] = NULL;
1410 pl011_dma_remove(uap);
1411 clk_put(uap->clk);
1412 unmap:
1413 iounmap(base);
1414 free:
1415 kfree(uap);
1416 }
1417 out:
1418 return ret;
1419 }
1420
1421 static int pl011_remove(struct amba_device *dev)
1422 {
1423 struct uart_amba_port *uap = amba_get_drvdata(dev);
1424 int i;
1425
1426 amba_set_drvdata(dev, NULL);
1427
1428 uart_remove_one_port(&amba_reg, &uap->port);
1429
1430 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1431 if (amba_ports[i] == uap)
1432 amba_ports[i] = NULL;
1433
1434 pl011_dma_remove(uap);
1435 iounmap(uap->port.membase);
1436 clk_put(uap->clk);
1437 kfree(uap);
1438 return 0;
1439 }
1440
1441 #ifdef CONFIG_PM
1442 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1443 {
1444 struct uart_amba_port *uap = amba_get_drvdata(dev);
1445
1446 if (!uap)
1447 return -EINVAL;
1448
1449 return uart_suspend_port(&amba_reg, &uap->port);
1450 }
1451
1452 static int pl011_resume(struct amba_device *dev)
1453 {
1454 struct uart_amba_port *uap = amba_get_drvdata(dev);
1455
1456 if (!uap)
1457 return -EINVAL;
1458
1459 return uart_resume_port(&amba_reg, &uap->port);
1460 }
1461 #endif
1462
1463 static struct amba_id pl011_ids[] = {
1464 {
1465 .id = 0x00041011,
1466 .mask = 0x000fffff,
1467 .data = &vendor_arm,
1468 },
1469 {
1470 .id = 0x00380802,
1471 .mask = 0x00ffffff,
1472 .data = &vendor_st,
1473 },
1474 { 0, 0 },
1475 };
1476
1477 static struct amba_driver pl011_driver = {
1478 .drv = {
1479 .name = "uart-pl011",
1480 },
1481 .id_table = pl011_ids,
1482 .probe = pl011_probe,
1483 .remove = pl011_remove,
1484 #ifdef CONFIG_PM
1485 .suspend = pl011_suspend,
1486 .resume = pl011_resume,
1487 #endif
1488 };
1489
1490 static int __init pl011_init(void)
1491 {
1492 int ret;
1493 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
1494
1495 ret = uart_register_driver(&amba_reg);
1496 if (ret == 0) {
1497 ret = amba_driver_register(&pl011_driver);
1498 if (ret)
1499 uart_unregister_driver(&amba_reg);
1500 }
1501 return ret;
1502 }
1503
1504 static void __exit pl011_exit(void)
1505 {
1506 amba_driver_unregister(&pl011_driver);
1507 uart_unregister_driver(&amba_reg);
1508 }
1509
1510 /*
1511 * While this can be a module, if builtin it's most likely the console
1512 * So let's leave module_exit but move module_init to an earlier place
1513 */
1514 arch_initcall(pl011_init);
1515 module_exit(pl011_exit);
1516
1517 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
1518 MODULE_DESCRIPTION("ARM AMBA serial port driver");
1519 MODULE_LICENSE("GPL");
Linux with added FPC-III support