2 * SuperH On-Chip RTC Support
4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
6 * Copyright (C) 2008 Angelo Castello
8 * Based on the old arch/sh/kernel/cpu/rtc.c by:
10 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/bcd.h>
20 #include <linux/rtc.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/spinlock.h>
27 #include <linux/log2.h>
28 #include <linux/clk.h>
29 #include <linux/slab.h>
32 #define DRV_NAME "sh-rtc"
33 #define DRV_VERSION "0.2.3"
35 #define RTC_REG(r) ((r) * rtc_reg_size)
37 #define R64CNT RTC_REG(0)
39 #define RSECCNT RTC_REG(1) /* RTC sec */
40 #define RMINCNT RTC_REG(2) /* RTC min */
41 #define RHRCNT RTC_REG(3) /* RTC hour */
42 #define RWKCNT RTC_REG(4) /* RTC week */
43 #define RDAYCNT RTC_REG(5) /* RTC day */
44 #define RMONCNT RTC_REG(6) /* RTC month */
45 #define RYRCNT RTC_REG(7) /* RTC year */
46 #define RSECAR RTC_REG(8) /* ALARM sec */
47 #define RMINAR RTC_REG(9) /* ALARM min */
48 #define RHRAR RTC_REG(10) /* ALARM hour */
49 #define RWKAR RTC_REG(11) /* ALARM week */
50 #define RDAYAR RTC_REG(12) /* ALARM day */
51 #define RMONAR RTC_REG(13) /* ALARM month */
52 #define RCR1 RTC_REG(14) /* Control */
53 #define RCR2 RTC_REG(15) /* Control */
56 * Note on RYRAR and RCR3: Up until this point most of the register
57 * definitions are consistent across all of the available parts. However,
58 * the placement of the optional RYRAR and RCR3 (the RYRAR control
59 * register used to control RYRCNT/RYRAR compare) varies considerably
60 * across various parts, occasionally being mapped in to a completely
61 * unrelated address space. For proper RYRAR support a separate resource
62 * would have to be handed off, but as this is purely optional in
63 * practice, we simply opt not to support it, thereby keeping the code
64 * quite a bit more simplified.
67 /* ALARM Bits - or with BCD encoded value */
68 #define AR_ENB 0x80 /* Enable for alarm cmp */
71 #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
72 #define PF_COUNT 0x200 /* Half periodic counter */
73 #define PF_OXS 0x400 /* Periodic One x Second */
74 #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
78 #define RCR1_CF 0x80 /* Carry Flag */
79 #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
80 #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
81 #define RCR1_AF 0x01 /* Alarm Flag */
84 #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
85 #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
86 #define RCR2_RTCEN 0x08 /* ENable RTC */
87 #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
88 #define RCR2_RESET 0x02 /* Reset bit */
89 #define RCR2_START 0x01 /* Start bit */
92 void __iomem
*regbase
;
93 unsigned long regsize
;
99 struct rtc_device
*rtc_dev
;
101 unsigned long capabilities
; /* See asm/rtc.h for cap bits */
102 unsigned short periodic_freq
;
105 static int __sh_rtc_interrupt(struct sh_rtc
*rtc
)
107 unsigned int tmp
, pending
;
109 tmp
= readb(rtc
->regbase
+ RCR1
);
110 pending
= tmp
& RCR1_CF
;
112 writeb(tmp
, rtc
->regbase
+ RCR1
);
114 /* Users have requested One x Second IRQ */
115 if (pending
&& rtc
->periodic_freq
& PF_OXS
)
116 rtc_update_irq(rtc
->rtc_dev
, 1, RTC_UF
| RTC_IRQF
);
121 static int __sh_rtc_alarm(struct sh_rtc
*rtc
)
123 unsigned int tmp
, pending
;
125 tmp
= readb(rtc
->regbase
+ RCR1
);
126 pending
= tmp
& RCR1_AF
;
127 tmp
&= ~(RCR1_AF
| RCR1_AIE
);
128 writeb(tmp
, rtc
->regbase
+ RCR1
);
131 rtc_update_irq(rtc
->rtc_dev
, 1, RTC_AF
| RTC_IRQF
);
136 static int __sh_rtc_periodic(struct sh_rtc
*rtc
)
138 struct rtc_device
*rtc_dev
= rtc
->rtc_dev
;
139 struct rtc_task
*irq_task
;
140 unsigned int tmp
, pending
;
142 tmp
= readb(rtc
->regbase
+ RCR2
);
143 pending
= tmp
& RCR2_PEF
;
145 writeb(tmp
, rtc
->regbase
+ RCR2
);
150 /* Half period enabled than one skipped and the next notified */
151 if ((rtc
->periodic_freq
& PF_HP
) && (rtc
->periodic_freq
& PF_COUNT
))
152 rtc
->periodic_freq
&= ~PF_COUNT
;
154 if (rtc
->periodic_freq
& PF_HP
)
155 rtc
->periodic_freq
|= PF_COUNT
;
156 if (rtc
->periodic_freq
& PF_KOU
) {
157 spin_lock(&rtc_dev
->irq_task_lock
);
158 irq_task
= rtc_dev
->irq_task
;
160 irq_task
->func(irq_task
->private_data
);
161 spin_unlock(&rtc_dev
->irq_task_lock
);
163 rtc_update_irq(rtc
->rtc_dev
, 1, RTC_PF
| RTC_IRQF
);
169 static irqreturn_t
sh_rtc_interrupt(int irq
, void *dev_id
)
171 struct sh_rtc
*rtc
= dev_id
;
174 spin_lock(&rtc
->lock
);
175 ret
= __sh_rtc_interrupt(rtc
);
176 spin_unlock(&rtc
->lock
);
178 return IRQ_RETVAL(ret
);
181 static irqreturn_t
sh_rtc_alarm(int irq
, void *dev_id
)
183 struct sh_rtc
*rtc
= dev_id
;
186 spin_lock(&rtc
->lock
);
187 ret
= __sh_rtc_alarm(rtc
);
188 spin_unlock(&rtc
->lock
);
190 return IRQ_RETVAL(ret
);
193 static irqreturn_t
sh_rtc_periodic(int irq
, void *dev_id
)
195 struct sh_rtc
*rtc
= dev_id
;
198 spin_lock(&rtc
->lock
);
199 ret
= __sh_rtc_periodic(rtc
);
200 spin_unlock(&rtc
->lock
);
202 return IRQ_RETVAL(ret
);
205 static irqreturn_t
sh_rtc_shared(int irq
, void *dev_id
)
207 struct sh_rtc
*rtc
= dev_id
;
210 spin_lock(&rtc
->lock
);
211 ret
= __sh_rtc_interrupt(rtc
);
212 ret
|= __sh_rtc_alarm(rtc
);
213 ret
|= __sh_rtc_periodic(rtc
);
214 spin_unlock(&rtc
->lock
);
216 return IRQ_RETVAL(ret
);
219 static int sh_rtc_irq_set_state(struct device
*dev
, int enable
)
221 struct sh_rtc
*rtc
= dev_get_drvdata(dev
);
224 spin_lock_irq(&rtc
->lock
);
226 tmp
= readb(rtc
->regbase
+ RCR2
);
229 rtc
->periodic_freq
|= PF_KOU
;
230 tmp
&= ~RCR2_PEF
; /* Clear PES bit */
231 tmp
|= (rtc
->periodic_freq
& ~PF_HP
); /* Set PES2-0 */
233 rtc
->periodic_freq
&= ~PF_KOU
;
234 tmp
&= ~(RCR2_PESMASK
| RCR2_PEF
);
237 writeb(tmp
, rtc
->regbase
+ RCR2
);
239 spin_unlock_irq(&rtc
->lock
);
244 static int sh_rtc_irq_set_freq(struct device
*dev
, int freq
)
246 struct sh_rtc
*rtc
= dev_get_drvdata(dev
);
249 spin_lock_irq(&rtc
->lock
);
250 tmp
= rtc
->periodic_freq
& PF_MASK
;
254 rtc
->periodic_freq
= 0x00;
257 rtc
->periodic_freq
= 0x60;
260 rtc
->periodic_freq
= 0x50;
263 rtc
->periodic_freq
= 0x40;
266 rtc
->periodic_freq
= 0x30 | PF_HP
;
269 rtc
->periodic_freq
= 0x30;
272 rtc
->periodic_freq
= 0x20 | PF_HP
;
275 rtc
->periodic_freq
= 0x20;
278 rtc
->periodic_freq
= 0x10 | PF_HP
;
281 rtc
->periodic_freq
= 0x10;
288 rtc
->periodic_freq
|= tmp
;
290 spin_unlock_irq(&rtc
->lock
);
294 static inline void sh_rtc_setaie(struct device
*dev
, unsigned int enable
)
296 struct sh_rtc
*rtc
= dev_get_drvdata(dev
);
299 spin_lock_irq(&rtc
->lock
);
301 tmp
= readb(rtc
->regbase
+ RCR1
);
308 writeb(tmp
, rtc
->regbase
+ RCR1
);
310 spin_unlock_irq(&rtc
->lock
);
313 static int sh_rtc_proc(struct device
*dev
, struct seq_file
*seq
)
315 struct sh_rtc
*rtc
= dev_get_drvdata(dev
);
318 tmp
= readb(rtc
->regbase
+ RCR1
);
319 seq_printf(seq
, "carry_IRQ\t: %s\n", (tmp
& RCR1_CIE
) ? "yes" : "no");
321 tmp
= readb(rtc
->regbase
+ RCR2
);
322 seq_printf(seq
, "periodic_IRQ\t: %s\n",
323 (tmp
& RCR2_PESMASK
) ? "yes" : "no");
328 static inline void sh_rtc_setcie(struct device
*dev
, unsigned int enable
)
330 struct sh_rtc
*rtc
= dev_get_drvdata(dev
);
333 spin_lock_irq(&rtc
->lock
);
335 tmp
= readb(rtc
->regbase
+ RCR1
);
342 writeb(tmp
, rtc
->regbase
+ RCR1
);
344 spin_unlock_irq(&rtc
->lock
);
347 static int sh_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
349 sh_rtc_setaie(dev
, enabled
);
353 static int sh_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
355 struct platform_device
*pdev
= to_platform_device(dev
);
356 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
357 unsigned int sec128
, sec2
, yr
, yr100
, cf_bit
;
362 spin_lock_irq(&rtc
->lock
);
364 tmp
= readb(rtc
->regbase
+ RCR1
);
365 tmp
&= ~RCR1_CF
; /* Clear CF-bit */
367 writeb(tmp
, rtc
->regbase
+ RCR1
);
369 sec128
= readb(rtc
->regbase
+ R64CNT
);
371 tm
->tm_sec
= bcd2bin(readb(rtc
->regbase
+ RSECCNT
));
372 tm
->tm_min
= bcd2bin(readb(rtc
->regbase
+ RMINCNT
));
373 tm
->tm_hour
= bcd2bin(readb(rtc
->regbase
+ RHRCNT
));
374 tm
->tm_wday
= bcd2bin(readb(rtc
->regbase
+ RWKCNT
));
375 tm
->tm_mday
= bcd2bin(readb(rtc
->regbase
+ RDAYCNT
));
376 tm
->tm_mon
= bcd2bin(readb(rtc
->regbase
+ RMONCNT
)) - 1;
378 if (rtc
->capabilities
& RTC_CAP_4_DIGIT_YEAR
) {
379 yr
= readw(rtc
->regbase
+ RYRCNT
);
380 yr100
= bcd2bin(yr
>> 8);
383 yr
= readb(rtc
->regbase
+ RYRCNT
);
384 yr100
= bcd2bin((yr
== 0x99) ? 0x19 : 0x20);
387 tm
->tm_year
= (yr100
* 100 + bcd2bin(yr
)) - 1900;
389 sec2
= readb(rtc
->regbase
+ R64CNT
);
390 cf_bit
= readb(rtc
->regbase
+ RCR1
) & RCR1_CF
;
392 spin_unlock_irq(&rtc
->lock
);
393 } while (cf_bit
!= 0 || ((sec128
^ sec2
) & RTC_BIT_INVERTED
) != 0);
395 #if RTC_BIT_INVERTED != 0
396 if ((sec128
& RTC_BIT_INVERTED
))
400 /* only keep the carry interrupt enabled if UIE is on */
401 if (!(rtc
->periodic_freq
& PF_OXS
))
402 sh_rtc_setcie(dev
, 0);
404 dev_dbg(dev
, "%s: tm is secs=%d, mins=%d, hours=%d, "
405 "mday=%d, mon=%d, year=%d, wday=%d\n",
407 tm
->tm_sec
, tm
->tm_min
, tm
->tm_hour
,
408 tm
->tm_mday
, tm
->tm_mon
+ 1, tm
->tm_year
, tm
->tm_wday
);
410 return rtc_valid_tm(tm
);
413 static int sh_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
415 struct platform_device
*pdev
= to_platform_device(dev
);
416 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
420 spin_lock_irq(&rtc
->lock
);
422 /* Reset pre-scaler & stop RTC */
423 tmp
= readb(rtc
->regbase
+ RCR2
);
426 writeb(tmp
, rtc
->regbase
+ RCR2
);
428 writeb(bin2bcd(tm
->tm_sec
), rtc
->regbase
+ RSECCNT
);
429 writeb(bin2bcd(tm
->tm_min
), rtc
->regbase
+ RMINCNT
);
430 writeb(bin2bcd(tm
->tm_hour
), rtc
->regbase
+ RHRCNT
);
431 writeb(bin2bcd(tm
->tm_wday
), rtc
->regbase
+ RWKCNT
);
432 writeb(bin2bcd(tm
->tm_mday
), rtc
->regbase
+ RDAYCNT
);
433 writeb(bin2bcd(tm
->tm_mon
+ 1), rtc
->regbase
+ RMONCNT
);
435 if (rtc
->capabilities
& RTC_CAP_4_DIGIT_YEAR
) {
436 year
= (bin2bcd((tm
->tm_year
+ 1900) / 100) << 8) |
437 bin2bcd(tm
->tm_year
% 100);
438 writew(year
, rtc
->regbase
+ RYRCNT
);
440 year
= tm
->tm_year
% 100;
441 writeb(bin2bcd(year
), rtc
->regbase
+ RYRCNT
);
445 tmp
= readb(rtc
->regbase
+ RCR2
);
447 tmp
|= RCR2_RTCEN
| RCR2_START
;
448 writeb(tmp
, rtc
->regbase
+ RCR2
);
450 spin_unlock_irq(&rtc
->lock
);
455 static inline int sh_rtc_read_alarm_value(struct sh_rtc
*rtc
, int reg_off
)
458 int value
= 0xff; /* return 0xff for ignored values */
460 byte
= readb(rtc
->regbase
+ reg_off
);
462 byte
&= ~AR_ENB
; /* strip the enable bit */
463 value
= bcd2bin(byte
);
469 static int sh_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*wkalrm
)
471 struct platform_device
*pdev
= to_platform_device(dev
);
472 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
473 struct rtc_time
*tm
= &wkalrm
->time
;
475 spin_lock_irq(&rtc
->lock
);
477 tm
->tm_sec
= sh_rtc_read_alarm_value(rtc
, RSECAR
);
478 tm
->tm_min
= sh_rtc_read_alarm_value(rtc
, RMINAR
);
479 tm
->tm_hour
= sh_rtc_read_alarm_value(rtc
, RHRAR
);
480 tm
->tm_wday
= sh_rtc_read_alarm_value(rtc
, RWKAR
);
481 tm
->tm_mday
= sh_rtc_read_alarm_value(rtc
, RDAYAR
);
482 tm
->tm_mon
= sh_rtc_read_alarm_value(rtc
, RMONAR
);
484 tm
->tm_mon
-= 1; /* RTC is 1-12, tm_mon is 0-11 */
485 tm
->tm_year
= 0xffff;
487 wkalrm
->enabled
= (readb(rtc
->regbase
+ RCR1
) & RCR1_AIE
) ? 1 : 0;
489 spin_unlock_irq(&rtc
->lock
);
494 static inline void sh_rtc_write_alarm_value(struct sh_rtc
*rtc
,
495 int value
, int reg_off
)
497 /* < 0 for a value that is ignored */
499 writeb(0, rtc
->regbase
+ reg_off
);
501 writeb(bin2bcd(value
) | AR_ENB
, rtc
->regbase
+ reg_off
);
504 static int sh_rtc_check_alarm(struct rtc_time
*tm
)
507 * The original rtc says anything > 0xc0 is "don't care" or "match
508 * all" - most users use 0xff but rtc-dev uses -1 for the same thing.
509 * The original rtc doesn't support years - some things use -1 and
510 * some 0xffff. We use -1 to make out tests easier.
512 if (tm
->tm_year
== 0xffff)
514 if (tm
->tm_mon
>= 0xff)
516 if (tm
->tm_mday
>= 0xff)
518 if (tm
->tm_wday
>= 0xff)
520 if (tm
->tm_hour
>= 0xff)
522 if (tm
->tm_min
>= 0xff)
524 if (tm
->tm_sec
>= 0xff)
527 if (tm
->tm_year
> 9999 ||
529 tm
->tm_mday
== 0 || tm
->tm_mday
>= 32 ||
539 static int sh_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*wkalrm
)
541 struct platform_device
*pdev
= to_platform_device(dev
);
542 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
544 struct rtc_time
*tm
= &wkalrm
->time
;
547 err
= sh_rtc_check_alarm(tm
);
548 if (unlikely(err
< 0))
551 spin_lock_irq(&rtc
->lock
);
553 /* disable alarm interrupt and clear the alarm flag */
554 rcr1
= readb(rtc
->regbase
+ RCR1
);
555 rcr1
&= ~(RCR1_AF
| RCR1_AIE
);
556 writeb(rcr1
, rtc
->regbase
+ RCR1
);
559 sh_rtc_write_alarm_value(rtc
, tm
->tm_sec
, RSECAR
);
560 sh_rtc_write_alarm_value(rtc
, tm
->tm_min
, RMINAR
);
561 sh_rtc_write_alarm_value(rtc
, tm
->tm_hour
, RHRAR
);
562 sh_rtc_write_alarm_value(rtc
, tm
->tm_wday
, RWKAR
);
563 sh_rtc_write_alarm_value(rtc
, tm
->tm_mday
, RDAYAR
);
567 sh_rtc_write_alarm_value(rtc
, mon
, RMONAR
);
569 if (wkalrm
->enabled
) {
571 writeb(rcr1
, rtc
->regbase
+ RCR1
);
574 spin_unlock_irq(&rtc
->lock
);
579 static struct rtc_class_ops sh_rtc_ops
= {
580 .read_time
= sh_rtc_read_time
,
581 .set_time
= sh_rtc_set_time
,
582 .read_alarm
= sh_rtc_read_alarm
,
583 .set_alarm
= sh_rtc_set_alarm
,
585 .alarm_irq_enable
= sh_rtc_alarm_irq_enable
,
588 static int __init
sh_rtc_probe(struct platform_device
*pdev
)
591 struct resource
*res
;
596 rtc
= devm_kzalloc(&pdev
->dev
, sizeof(*rtc
), GFP_KERNEL
);
600 spin_lock_init(&rtc
->lock
);
602 /* get periodic/carry/alarm irqs */
603 ret
= platform_get_irq(pdev
, 0);
604 if (unlikely(ret
<= 0)) {
605 dev_err(&pdev
->dev
, "No IRQ resource\n");
609 rtc
->periodic_irq
= ret
;
610 rtc
->carry_irq
= platform_get_irq(pdev
, 1);
611 rtc
->alarm_irq
= platform_get_irq(pdev
, 2);
613 res
= platform_get_resource(pdev
, IORESOURCE_IO
, 0);
614 if (unlikely(res
== NULL
)) {
615 dev_err(&pdev
->dev
, "No IO resource\n");
619 rtc
->regsize
= resource_size(res
);
621 rtc
->res
= devm_request_mem_region(&pdev
->dev
, res
->start
,
622 rtc
->regsize
, pdev
->name
);
623 if (unlikely(!rtc
->res
))
626 rtc
->regbase
= devm_ioremap_nocache(&pdev
->dev
, rtc
->res
->start
,
628 if (unlikely(!rtc
->regbase
))
632 /* With a single device, the clock id is still "rtc0" */
636 snprintf(clk_name
, sizeof(clk_name
), "rtc%d", clk_id
);
638 rtc
->clk
= devm_clk_get(&pdev
->dev
, clk_name
);
639 if (IS_ERR(rtc
->clk
)) {
641 * No error handling for rtc->clk intentionally, not all
642 * platforms will have a unique clock for the RTC, and
643 * the clk API can handle the struct clk pointer being
649 clk_enable(rtc
->clk
);
651 rtc
->capabilities
= RTC_DEF_CAPABILITIES
;
652 if (dev_get_platdata(&pdev
->dev
)) {
653 struct sh_rtc_platform_info
*pinfo
=
654 dev_get_platdata(&pdev
->dev
);
657 * Some CPUs have special capabilities in addition to the
658 * default set. Add those in here.
660 rtc
->capabilities
|= pinfo
->capabilities
;
663 if (rtc
->carry_irq
<= 0) {
664 /* register shared periodic/carry/alarm irq */
665 ret
= devm_request_irq(&pdev
->dev
, rtc
->periodic_irq
,
666 sh_rtc_shared
, 0, "sh-rtc", rtc
);
669 "request IRQ failed with %d, IRQ %d\n", ret
,
674 /* register periodic/carry/alarm irqs */
675 ret
= devm_request_irq(&pdev
->dev
, rtc
->periodic_irq
,
676 sh_rtc_periodic
, 0, "sh-rtc period", rtc
);
679 "request period IRQ failed with %d, IRQ %d\n",
680 ret
, rtc
->periodic_irq
);
684 ret
= devm_request_irq(&pdev
->dev
, rtc
->carry_irq
,
685 sh_rtc_interrupt
, 0, "sh-rtc carry", rtc
);
688 "request carry IRQ failed with %d, IRQ %d\n",
689 ret
, rtc
->carry_irq
);
693 ret
= devm_request_irq(&pdev
->dev
, rtc
->alarm_irq
,
694 sh_rtc_alarm
, 0, "sh-rtc alarm", rtc
);
697 "request alarm IRQ failed with %d, IRQ %d\n",
698 ret
, rtc
->alarm_irq
);
703 platform_set_drvdata(pdev
, rtc
);
705 /* everything disabled by default */
706 sh_rtc_irq_set_freq(&pdev
->dev
, 0);
707 sh_rtc_irq_set_state(&pdev
->dev
, 0);
708 sh_rtc_setaie(&pdev
->dev
, 0);
709 sh_rtc_setcie(&pdev
->dev
, 0);
711 rtc
->rtc_dev
= devm_rtc_device_register(&pdev
->dev
, "sh",
712 &sh_rtc_ops
, THIS_MODULE
);
713 if (IS_ERR(rtc
->rtc_dev
)) {
714 ret
= PTR_ERR(rtc
->rtc_dev
);
718 rtc
->rtc_dev
->max_user_freq
= 256;
720 /* reset rtc to epoch 0 if time is invalid */
721 if (rtc_read_time(rtc
->rtc_dev
, &r
) < 0) {
722 rtc_time_to_tm(0, &r
);
723 rtc_set_time(rtc
->rtc_dev
, &r
);
726 device_init_wakeup(&pdev
->dev
, 1);
730 clk_disable(rtc
->clk
);
735 static int __exit
sh_rtc_remove(struct platform_device
*pdev
)
737 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
739 sh_rtc_irq_set_state(&pdev
->dev
, 0);
741 sh_rtc_setaie(&pdev
->dev
, 0);
742 sh_rtc_setcie(&pdev
->dev
, 0);
744 clk_disable(rtc
->clk
);
749 static void sh_rtc_set_irq_wake(struct device
*dev
, int enabled
)
751 struct platform_device
*pdev
= to_platform_device(dev
);
752 struct sh_rtc
*rtc
= platform_get_drvdata(pdev
);
754 irq_set_irq_wake(rtc
->periodic_irq
, enabled
);
756 if (rtc
->carry_irq
> 0) {
757 irq_set_irq_wake(rtc
->carry_irq
, enabled
);
758 irq_set_irq_wake(rtc
->alarm_irq
, enabled
);
762 #ifdef CONFIG_PM_SLEEP
763 static int sh_rtc_suspend(struct device
*dev
)
765 if (device_may_wakeup(dev
))
766 sh_rtc_set_irq_wake(dev
, 1);
771 static int sh_rtc_resume(struct device
*dev
)
773 if (device_may_wakeup(dev
))
774 sh_rtc_set_irq_wake(dev
, 0);
780 static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops
, sh_rtc_suspend
, sh_rtc_resume
);
782 static struct platform_driver sh_rtc_platform_driver
= {
785 .owner
= THIS_MODULE
,
786 .pm
= &sh_rtc_pm_ops
,
788 .remove
= __exit_p(sh_rtc_remove
),
791 module_platform_driver_probe(sh_rtc_platform_driver
, sh_rtc_probe
);
793 MODULE_DESCRIPTION("SuperH on-chip RTC driver");
794 MODULE_VERSION(DRV_VERSION
);
795 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
796 "Jamie Lenehan <lenehan@twibble.org>, "
797 "Angelo Castello <angelo.castello@st.com>");
798 MODULE_LICENSE("GPL");
799 MODULE_ALIAS("platform:" DRV_NAME
);