drivers/staging/slicoss/slichw.h

   1 /**************************************************************************
   2  *
   3  * Copyright (c) 2000-2002 Alacritech, Inc.  All rights reserved.
   4  *
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above
  13  *    copyright notice, this list of conditions and the following
  14  *    disclaimer in the documentation and/or other materials provided
  15  *    with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  18  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  21  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  24  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  27  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * The views and conclusions contained in the software and documentation
  31  * are those of the authors and should not be interpreted as representing
  32  * official policies, either expressed or implied, of Alacritech, Inc.
  33  *
  34  **************************************************************************/
  35
  36 /*
  37  * FILENAME: slichw.h
  38  *
  39  * This header file contains definitions that are common to our hardware.
  40  */
  41 #ifndef __SLICHW_H__
  42 #define __SLICHW_H__
  43
  44 #define PCI_VENDOR_ID_ALACRITECH        0x139A
  45 #define SLIC_1GB_DEVICE_ID              0x0005
  46 #define SLIC_2GB_DEVICE_ID              0x0007  /* Oasis Device ID */
  47
  48 #define SLIC_1GB_CICADA_SUBSYS_ID       0x0008
  49
  50 #define SLIC_NBR_MACS           4
  51
  52 #define SLIC_RCVBUF_SIZE        2048
  53 #define SLIC_RCVBUF_HEADSIZE    34
  54 #define SLIC_RCVBUF_TAILSIZE    0
  55 #define SLIC_RCVBUF_DATASIZE    (SLIC_RCVBUF_SIZE -             \
  56                                  (SLIC_RCVBUF_HEADSIZE +        \
  57                                   SLIC_RCVBUF_TAILSIZE))
  58
  59 #define VGBSTAT_XPERR           0x40000000
  60 #define VGBSTAT_XERRSHFT        25
  61 #define VGBSTAT_XCSERR          0x23
  62 #define VGBSTAT_XUFLOW          0x22
  63 #define VGBSTAT_XHLEN           0x20
  64 #define VGBSTAT_NETERR          0x01000000
  65 #define VGBSTAT_NERRSHFT        16
  66 #define VGBSTAT_NERRMSK         0x1ff
  67 #define VGBSTAT_NCSERR          0x103
  68 #define VGBSTAT_NUFLOW          0x102
  69 #define VGBSTAT_NHLEN           0x100
  70 #define VGBSTAT_LNKERR          0x00000080
  71 #define VGBSTAT_LERRMSK         0xff
  72 #define VGBSTAT_LDEARLY         0x86
  73 #define VGBSTAT_LBOFLO          0x85
  74 #define VGBSTAT_LCODERR         0x84
  75 #define VGBSTAT_LDBLNBL         0x83
  76 #define VGBSTAT_LCRCERR         0x82
  77 #define VGBSTAT_LOFLO           0x81
  78 #define VGBSTAT_LUFLO           0x80
  79 #define IRHDDR_FLEN_MSK         0x0000ffff
  80 #define IRHDDR_SVALID           0x80000000
  81 #define IRHDDR_ERR              0x10000000
  82 #define VRHSTAT_802OE           0x80000000
  83 #define VRHSTAT_TPOFLO          0x10000000
  84 #define VRHSTATB_802UE          0x80000000
  85 #define VRHSTATB_RCVE           0x40000000
  86 #define VRHSTATB_BUFF           0x20000000
  87 #define VRHSTATB_CARRE          0x08000000
  88 #define VRHSTATB_LONGE          0x02000000
  89 #define VRHSTATB_PREA           0x01000000
  90 #define VRHSTATB_CRC            0x00800000
  91 #define VRHSTATB_DRBL           0x00400000
  92 #define VRHSTATB_CODE           0x00200000
  93 #define VRHSTATB_TPCSUM         0x00100000
  94 #define VRHSTATB_TPHLEN         0x00080000
  95 #define VRHSTATB_IPCSUM         0x00040000
  96 #define VRHSTATB_IPLERR         0x00020000
  97 #define VRHSTATB_IPHERR         0x00010000
  98 #define SLIC_MAX64_BCNT         23
  99 #define SLIC_MAX32_BCNT         26
 100 #define IHCMD_XMT_REQ           0x01
 101 #define IHFLG_IFSHFT            2
 102 #define SLIC_RSPBUF_SIZE        32
 103
 104 #define SLIC_RESET_MAGIC        0xDEAD
 105 #define ICR_INT_OFF             0
 106 #define ICR_INT_ON              1
 107 #define ICR_INT_MASK            2
 108
 109 #define ISR_ERR                 0x80000000
 110 #define ISR_RCV                 0x40000000
 111 #define ISR_CMD                 0x20000000
 112 #define ISR_IO                  0x60000000
 113 #define ISR_UPC                 0x10000000
 114 #define ISR_LEVENT              0x08000000
 115 #define ISR_RMISS               0x02000000
 116 #define ISR_UPCERR              0x01000000
 117 #define ISR_XDROP               0x00800000
 118 #define ISR_UPCBSY              0x00020000
 119 #define ISR_EVMSK               0xffff0000
 120 #define ISR_PINGMASK            0x00700000
 121 #define ISR_PINGDSMASK          0x00710000
 122 #define ISR_UPCMASK             0x11000000
 123 #define SLIC_WCS_START          0x80000000
 124 #define SLIC_WCS_COMPARE        0x40000000
 125 #define SLIC_RCVWCS_BEGIN       0x40000000
 126 #define SLIC_RCVWCS_FINISH      0x80000000
 127 #define SLIC_PM_MAXPATTERNS     6
 128 #define SLIC_PM_PATTERNSIZE     128
 129 #define SLIC_PMCAPS_WAKEONLAN   0x00000001
 130 #define MIICR_REG_PCR           0x00000000
 131 #define MIICR_REG_4             0x00040000
 132 #define MIICR_REG_9             0x00090000
 133 #define MIICR_REG_16            0x00100000
 134 #define PCR_RESET               0x8000
 135 #define PCR_POWERDOWN           0x0800
 136 #define PCR_SPEED_100           0x2000
 137 #define PCR_SPEED_1000          0x0040
 138 #define PCR_AUTONEG             0x1000
 139 #define PCR_AUTONEG_RST         0x0200
 140 #define PCR_DUPLEX_FULL         0x0100
 141 #define PSR_LINKUP              0x0004
 142
 143 #define PAR_ADV100FD            0x0100
 144 #define PAR_ADV100HD            0x0080
 145 #define PAR_ADV10FD             0x0040
 146 #define PAR_ADV10HD             0x0020
 147 #define PAR_ASYMPAUSE           0x0C00
 148 #define PAR_802_3               0x0001
 149
 150 #define PAR_ADV1000XFD          0x0020
 151 #define PAR_ADV1000XHD          0x0040
 152 #define PAR_ASYMPAUSE_FIBER     0x0180
 153
 154 #define PGC_ADV1000FD           0x0200
 155 #define PGC_ADV1000HD           0x0100
 156 #define SEEQ_LINKFAIL           0x4000
 157 #define SEEQ_SPEED              0x0080
 158 #define SEEQ_DUPLEX             0x0040
 159 #define TDK_DUPLEX              0x0800
 160 #define TDK_SPEED               0x0400
 161 #define MRV_REG16_XOVERON       0x0068
 162 #define MRV_REG16_XOVEROFF      0x0008
 163 #define MRV_SPEED_1000          0x8000
 164 #define MRV_SPEED_100           0x4000
 165 #define MRV_SPEED_10            0x0000
 166 #define MRV_FULLDUPLEX          0x2000
 167 #define MRV_LINKUP              0x0400
 168
 169 #define GIG_LINKUP              0x0001
 170 #define GIG_FULLDUPLEX          0x0002
 171 #define GIG_SPEED_MASK          0x000C
 172 #define GIG_SPEED_1000          0x0008
 173 #define GIG_SPEED_100           0x0004
 174 #define GIG_SPEED_10            0x0000
 175
 176 #define MCR_RESET               0x80000000
 177 #define MCR_CRCEN               0x40000000
 178 #define MCR_FULLD               0x10000000
 179 #define MCR_PAD                 0x02000000
 180 #define MCR_RETRYLATE           0x01000000
 181 #define MCR_BOL_SHIFT           21
 182 #define MCR_IPG1_SHIFT          14
 183 #define MCR_IPG2_SHIFT          7
 184 #define MCR_IPG3_SHIFT          0
 185 #define GMCR_RESET              0x80000000
 186 #define GMCR_GBIT               0x20000000
 187 #define GMCR_FULLD              0x10000000
 188 #define GMCR_GAPBB_SHIFT        14
 189 #define GMCR_GAPR1_SHIFT        7
 190 #define GMCR_GAPR2_SHIFT        0
 191 #define GMCR_GAPBB_1000         0x60
 192 #define GMCR_GAPR1_1000         0x2C
 193 #define GMCR_GAPR2_1000         0x40
 194 #define GMCR_GAPBB_100          0x70
 195 #define GMCR_GAPR1_100          0x2C
 196 #define GMCR_GAPR2_100          0x40
 197 #define XCR_RESET               0x80000000
 198 #define XCR_XMTEN               0x40000000
 199 #define XCR_PAUSEEN             0x20000000
 200 #define XCR_LOADRNG             0x10000000
 201 #define RCR_RESET               0x80000000
 202 #define RCR_RCVEN               0x40000000
 203 #define RCR_RCVALL              0x20000000
 204 #define RCR_RCVBAD              0x10000000
 205 #define RCR_CTLEN               0x08000000
 206 #define RCR_ADDRAEN             0x02000000
 207 #define GXCR_RESET              0x80000000
 208 #define GXCR_XMTEN              0x40000000
 209 #define GXCR_PAUSEEN            0x20000000
 210 #define GRCR_RESET              0x80000000
 211 #define GRCR_RCVEN              0x40000000
 212 #define GRCR_RCVALL             0x20000000
 213 #define GRCR_RCVBAD             0x10000000
 214 #define GRCR_CTLEN              0x08000000
 215 #define GRCR_ADDRAEN            0x02000000
 216 #define GRCR_HASHSIZE_SHIFT     17
 217 #define GRCR_HASHSIZE           14
 218
 219 #define SLIC_EEPROM_ID          0xA5A5
 220 #define SLIC_SRAM_SIZE2GB       (64 * 1024)
 221 #define SLIC_SRAM_SIZE1GB       (32 * 1024)
 222 #define SLIC_HOSTID_DEFAULT     0xFFFF          /* uninitialized hostid */
 223 #define SLIC_NBR_MACS           4
 224
 225 struct slic_rcvbuf {
 226         u8 pad1[6];
 227         u16 pad2;
 228         u32 pad3;
 229         u32 pad4;
 230         u32 buffer;
 231         u32 length;
 232         u32 status;
 233         u32 pad5;
 234         u16 pad6;
 235         u8 data[SLIC_RCVBUF_DATASIZE];
 236 };
 237
 238 struct slic_hddr_wds {
 239         union {
 240                 struct {
 241                         u32 frame_status;
 242                         u32 frame_status_b;
 243                         u32 time_stamp;
 244                         u32 checksum;
 245                 } hdrs_14port;
 246                 struct {
 247                         u32 frame_status;
 248                         u16 ByteCnt;
 249                         u16 TpChksum;
 250                         u16 CtxHash;
 251                         u16 MacHash;
 252                         u32 BufLnk;
 253                 } hdrs_gbit;
 254         } u0;
 255 };
 256
 257 #define frame_status14          u0.hdrs_14port.frame_status
 258 #define frame_status_b14        u0.hdrs_14port.frame_status_b
 259 #define frame_statusGB          u0.hdrs_gbit.frame_status
 260
 261 struct slic_host64sg {
 262         u32 paddrl;
 263         u32 paddrh;
 264         u32 length;
 265 };
 266
 267 struct slic_host64_cmd {
 268         u32 hosthandle;
 269         u32 RSVD;
 270         u8 command;
 271         u8 flags;
 272         union {
 273                 u16 rsv1;
 274                 u16 rsv2;
 275         } u0;
 276         union {
 277                 struct {
 278                         u32 totlen;
 279                         struct slic_host64sg bufs[SLIC_MAX64_BCNT];
 280                 } slic_buffers;
 281         } u;
 282 };
 283
 284 struct slic_rspbuf {
 285         u32 hosthandle;
 286         u32 pad0;
 287         u32 pad1;
 288         u32 status;
 289         u32 pad2[4];
 290 };
 291
 292 struct slic_regs {
 293         u32     slic_reset;     /* Reset Register */
 294         u32     pad0;
 295
 296         u32     slic_icr;       /* Interrupt Control Register */
 297         u32     pad2;
 298 #define SLIC_ICR                0x0008
 299
 300         u32     slic_isp;       /* Interrupt status pointer */
 301         u32     pad1;
 302 #define SLIC_ISP                0x0010
 303
 304         u32     slic_isr;       /* Interrupt status */
 305         u32     pad3;
 306 #define SLIC_ISR                0x0018
 307
 308         u32     slic_hbar;      /* Header buffer address reg */
 309         u32     pad4;
 310         /* 31-8 - phy addr of set of contiguous hdr buffers
 311             7-0 - number of buffers passed
 312            Buffers are 256 bytes long on 256-byte boundaries. */
 313 #define SLIC_HBAR               0x0020
 314 #define SLIC_HBAR_CNT_MSK       0x000000FF
 315
 316         u32     slic_dbar;      /* Data buffer handle & address reg */
 317         u32     pad5;
 318
 319         /* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
 320 #define SLIC_DBAR               0x0028
 321 #define SLIC_DBAR_SIZE          2048
 322
 323         u32     slic_cbar;      /* Xmt Cmd buf addr regs.*/
 324         /* 1 per XMT interface
 325            31-5 - phy addr of host command buffer
 326             4-0 - length of cmd in multiples of 32 bytes
 327            Buffers are 32 bytes up to 512 bytes long */
 328 #define SLIC_CBAR               0x0030
 329 #define SLIC_CBAR_LEN_MSK       0x0000001F
 330 #define SLIC_CBAR_ALIGN         0x00000020
 331
 332         u32     slic_wcs;       /* write control store*/
 333 #define SLIC_WCS                0x0034
 334 #define SLIC_WCS_START          0x80000000      /*Start the SLIC (Jump to WCS)*/
 335 #define SLIC_WCS_COMPARE        0x40000000      /* Compare with value in WCS*/
 336
 337         u32     slic_rbar;      /* Response buffer address reg.*/
 338         u32     pad7;
 339          /*31-8 - phy addr of set of contiguous response buffers
 340           7-0 - number of buffers passed
 341          Buffers are 32 bytes long on 32-byte boundaries.*/
 342 #define SLIC_RBAR               0x0038
 343 #define SLIC_RBAR_CNT_MSK       0x000000FF
 344 #define SLIC_RBAR_SIZE          32
 345
 346         u32     slic_stats;     /* read statistics (UPR) */
 347         u32     pad8;
 348 #define SLIC_RSTAT              0x0040
 349
 350         u32     slic_rlsr;      /* read link status */
 351         u32     pad9;
 352 #define SLIC_LSTAT              0x0048
 353
 354         u32     slic_wmcfg;     /* Write Mac Config */
 355         u32     pad10;
 356 #define SLIC_WMCFG              0x0050
 357
 358         u32     slic_wphy;      /* Write phy register */
 359         u32     pad11;
 360 #define SLIC_WPHY               0x0058
 361
 362         u32     slic_rcbar;     /* Rcv Cmd buf addr reg */
 363         u32     pad12;
 364 #define SLIC_RCBAR              0x0060
 365
 366         u32     slic_rconfig;   /* Read SLIC Config*/
 367         u32     pad13;
 368 #define SLIC_RCONFIG    0x0068
 369
 370         u32     slic_intagg;    /* Interrupt aggregation time */
 371         u32     pad14;
 372 #define SLIC_INTAGG             0x0070
 373
 374         u32     slic_wxcfg;     /* Write XMIT config reg*/
 375         u32     pad16;
 376 #define SLIC_WXCFG              0x0078
 377
 378         u32     slic_wrcfg;     /* Write RCV config reg*/
 379         u32     pad17;
 380 #define SLIC_WRCFG              0x0080
 381
 382         u32     slic_wraddral;  /* Write rcv addr a low*/
 383         u32     pad18;
 384 #define SLIC_WRADDRAL   0x0088
 385
 386         u32     slic_wraddrah;  /* Write rcv addr a high*/
 387         u32     pad19;
 388 #define SLIC_WRADDRAH   0x0090
 389
 390         u32     slic_wraddrbl;  /* Write rcv addr b low*/
 391         u32     pad20;
 392 #define SLIC_WRADDRBL   0x0098
 393
 394         u32     slic_wraddrbh;  /* Write rcv addr b high*/
 395         u32             pad21;
 396 #define SLIC_WRADDRBH   0x00a0
 397
 398         u32     slic_mcastlow;  /* Low bits of mcast mask*/
 399         u32             pad22;
 400 #define SLIC_MCASTLOW   0x00a8
 401
 402         u32     slic_mcasthigh; /* High bits of mcast mask*/
 403         u32             pad23;
 404 #define SLIC_MCASTHIGH  0x00b0
 405
 406         u32     slic_ping;      /* Ping the card*/
 407         u32     pad24;
 408 #define SLIC_PING               0x00b8
 409
 410         u32     slic_dump_cmd;  /* Dump command */
 411         u32     pad25;
 412 #define SLIC_DUMP_CMD   0x00c0
 413
 414         u32     slic_dump_data; /* Dump data pointer */
 415         u32     pad26;
 416 #define SLIC_DUMP_DATA  0x00c8
 417
 418         u32     slic_pcistatus; /* Read card's pci_status register */
 419         u32     pad27;
 420 #define SLIC_PCISTATUS  0x00d0
 421
 422         u32     slic_wrhostid;  /* Write hostid field */
 423         u32             pad28;
 424 #define SLIC_WRHOSTID            0x00d8
 425 #define SLIC_RDHOSTID_1GB        0x1554
 426 #define SLIC_RDHOSTID_2GB        0x1554
 427
 428         u32     slic_low_power; /* Put card in a low power state */
 429         u32     pad29;
 430 #define SLIC_LOW_POWER  0x00e0
 431
 432         u32     slic_quiesce;   /* force slic into quiescent state
 433                                    before soft reset */
 434         u32     pad30;
 435 #define SLIC_QUIESCE    0x00e8
 436
 437         u32     slic_reset_iface;/* reset interface queues */
 438         u32     pad31;
 439 #define SLIC_RESET_IFACE 0x00f0
 440
 441         u32     slic_addr_upper;/* Bits 63-32 for host i/f addrs */
 442         u32     pad32;
 443 #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
 444
 445         u32     slic_hbar64;    /* 64 bit Header buffer address reg */
 446         u32     pad33;
 447 #define SLIC_HBAR64             0x0100
 448
 449         u32     slic_dbar64;    /* 64 bit Data buffer handle & address reg */
 450         u32     pad34;
 451 #define SLIC_DBAR64             0x0108
 452
 453         u32     slic_cbar64;    /* 64 bit Xmt Cmd buf addr regs. */
 454         u32     pad35;
 455 #define SLIC_CBAR64             0x0110
 456
 457         u32     slic_rbar64;    /* 64 bit Response buffer address reg.*/
 458         u32     pad36;
 459 #define SLIC_RBAR64             0x0118
 460
 461         u32     slic_rcbar64;   /* 64 bit Rcv Cmd buf addr reg*/
 462         u32     pad37;
 463 #define SLIC_RCBAR64    0x0120
 464
 465         u32     slic_stats64;   /* read statistics (64 bit UPR) */
 466         u32     pad38;
 467 #define SLIC_RSTAT64    0x0128
 468
 469         u32     slic_rcv_wcs;   /*Download Gigabit RCV sequencer ucode*/
 470         u32     pad39;
 471 #define SLIC_RCV_WCS    0x0130
 472 #define SLIC_RCVWCS_BEGIN       0x40000000
 473 #define SLIC_RCVWCS_FINISH      0x80000000
 474
 475         u32     slic_wrvlanid;  /* Write VlanId field */
 476         u32     pad40;
 477 #define SLIC_WRVLANID   0x0138
 478
 479         u32     slic_read_xf_info;      /* Read Transformer info */
 480         u32     pad41;
 481 #define SLIC_READ_XF_INFO       0x0140
 482
 483         u32     slic_write_xf_info;     /* Write Transformer info */
 484         u32     pad42;
 485 #define SLIC_WRITE_XF_INFO      0x0148
 486
 487         u32     RSVD1;          /* TOE Only */
 488         u32     pad43;
 489
 490         u32     RSVD2;          /* TOE Only */
 491         u32     pad44;
 492
 493         u32     RSVD3;          /* TOE Only */
 494         u32     pad45;
 495
 496         u32     RSVD4;          /* TOE Only */
 497         u32     pad46;
 498
 499         u32     slic_ticks_per_sec; /* Write card ticks per second */
 500         u32     pad47;
 501 #define SLIC_TICKS_PER_SEC      0x0170
 502 };
 503
 504 enum UPR_REQUEST {
 505         SLIC_UPR_STATS,
 506         SLIC_UPR_RLSR,
 507         SLIC_UPR_WCFG,
 508         SLIC_UPR_RCONFIG,
 509         SLIC_UPR_RPHY,
 510         SLIC_UPR_ENLB,
 511         SLIC_UPR_ENCT,
 512         SLIC_UPR_PDWN,
 513         SLIC_UPR_PING,
 514         SLIC_UPR_DUMP,
 515 };
 516
 517 struct inicpm_wakepattern {
 518         u32 patternlength;
 519         u8 pattern[SLIC_PM_PATTERNSIZE];
 520         u8 mask[SLIC_PM_PATTERNSIZE];
 521 };
 522
 523 struct inicpm_state {
 524         u32 powercaps;
 525         u32 powerstate;
 526         u32 wake_linkstatus;
 527         u32 wake_magicpacket;
 528         u32 wake_framepattern;
 529         struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
 530 };
 531
 532 struct slicpm_packet_pattern {
 533         u32 priority;
 534         u32 reserved;
 535         u32 masksize;
 536         u32 patternoffset;
 537         u32 patternsize;
 538         u32 patternflags;
 539 };
 540
 541 enum slicpm_power_state {
 542         slicpm_state_unspecified = 0,
 543         slicpm_state_d0,
 544         slicpm_state_d1,
 545         slicpm_state_d2,
 546         slicpm_state_d3,
 547         slicpm_state_maximum
 548 };
 549
 550 struct slicpm_wakeup_capabilities {
 551         enum slicpm_power_state min_magic_packet_wakeup;
 552         enum slicpm_power_state min_pattern_wakeup;
 553         enum slicpm_power_state min_link_change_wakeup;
 554 };
 555
 556 struct slic_pnp_capabilities {
 557         u32 flags;
 558         struct slicpm_wakeup_capabilities wakeup_capabilities;
 559 };
 560
 561 struct xmt_stats {
 562         u32 xmit_tcp_bytes;
 563         u32 xmit_tcp_segs;
 564         u32 xmit_bytes;
 565         u32 xmit_collisions;
 566         u32 xmit_unicasts;
 567         u32 xmit_other_error;
 568         u32 xmit_excess_collisions;
 569 };
 570
 571 struct rcv_stats {
 572         u32 rcv_tcp_bytes;
 573         u32 rcv_tcp_segs;
 574         u32 rcv_bytes;
 575         u32 rcv_unicasts;
 576         u32 rcv_other_error;
 577         u32 rcv_drops;
 578 };
 579
 580 struct xmt_statsgb {
 581         u64 xmit_tcp_bytes;
 582         u64 xmit_tcp_segs;
 583         u64 xmit_bytes;
 584         u64 xmit_collisions;
 585         u64 xmit_unicasts;
 586         u64 xmit_other_error;
 587         u64 xmit_excess_collisions;
 588 };
 589
 590 struct rcv_statsgb {
 591         u64 rcv_tcp_bytes;
 592         u64 rcv_tcp_segs;
 593         u64 rcv_bytes;
 594         u64 rcv_unicasts;
 595         u64 rcv_other_error;
 596         u64 rcv_drops;
 597 };
 598
 599 struct slic_stats {
 600         union {
 601                 struct {
 602                         struct xmt_stats xmt100;
 603                         struct rcv_stats rcv100;
 604                 } stats_100;
 605                 struct {
 606                         struct xmt_statsgb xmtGB;
 607                         struct rcv_statsgb rcvGB;
 608                 } stats_GB;
 609         } u;
 610 };
 611
 612 #define xmit_tcp_segs100                u.stats_100.xmt100.xmit_tcp_segs
 613 #define xmit_tcp_bytes100               u.stats_100.xmt100.xmit_tcp_bytes
 614 #define xmit_bytes100                   u.stats_100.xmt100.xmit_bytes
 615 #define xmit_collisions100              u.stats_100.xmt100.xmit_collisions
 616 #define xmit_unicasts100                u.stats_100.xmt100.xmit_unicasts
 617 #define xmit_other_error100             u.stats_100.xmt100.xmit_other_error
 618 #define xmit_excess_collisions100       u.stats_100.xmt100.xmit_excess_collisions
 619 #define rcv_tcp_segs100                 u.stats_100.rcv100.rcv_tcp_segs
 620 #define rcv_tcp_bytes100                u.stats_100.rcv100.rcv_tcp_bytes
 621 #define rcv_bytes100                    u.stats_100.rcv100.rcv_bytes
 622 #define rcv_unicasts100                 u.stats_100.rcv100.rcv_unicasts
 623 #define rcv_other_error100              u.stats_100.rcv100.rcv_other_error
 624 #define rcv_drops100                    u.stats_100.rcv100.rcv_drops
 625 #define xmit_tcp_segs_gb                u.stats_GB.xmtGB.xmit_tcp_segs
 626 #define xmit_tcp_bytes_gb               u.stats_GB.xmtGB.xmit_tcp_bytes
 627 #define xmit_bytes_gb                   u.stats_GB.xmtGB.xmit_bytes
 628 #define xmit_collisions_gb              u.stats_GB.xmtGB.xmit_collisions
 629 #define xmit_unicasts_gb                u.stats_GB.xmtGB.xmit_unicasts
 630 #define xmit_other_error_gb             u.stats_GB.xmtGB.xmit_other_error
 631 #define xmit_excess_collisions_gb       u.stats_GB.xmtGB.xmit_excess_collisions
 632
 633 #define rcv_tcp_segs_gb                 u.stats_GB.rcvGB.rcv_tcp_segs
 634 #define rcv_tcp_bytes_gb                u.stats_GB.rcvGB.rcv_tcp_bytes
 635 #define rcv_bytes_gb                    u.stats_GB.rcvGB.rcv_bytes
 636 #define rcv_unicasts_gb                 u.stats_GB.rcvGB.rcv_unicasts
 637 #define rcv_other_error_gb              u.stats_GB.rcvGB.rcv_other_error
 638 #define rcv_drops_gb                    u.stats_GB.rcvGB.rcv_drops
 639
 640 struct slic_config_mac {
 641         u8 macaddrA[6];
 642 };
 643
 644 #define ATK_FRU_FORMAT          0x00
 645 #define VENDOR1_FRU_FORMAT      0x01
 646 #define VENDOR2_FRU_FORMAT      0x02
 647 #define VENDOR3_FRU_FORMAT      0x03
 648 #define VENDOR4_FRU_FORMAT      0x04
 649 #define NO_FRU_FORMAT           0xFF
 650
 651 struct atk_fru {
 652         u8 assembly[6];
 653         u8 revision[2];
 654         u8 serial[14];
 655         u8 pad[3];
 656 };
 657
 658 struct vendor1_fru {
 659         u8 commodity;
 660         u8 assembly[4];
 661         u8 revision[2];
 662         u8 supplier[2];
 663         u8 date[2];
 664         u8 sequence[3];
 665         u8 pad[13];
 666 };
 667
 668 struct vendor2_fru {
 669         u8 part[8];
 670         u8 supplier[5];
 671         u8 date[3];
 672         u8 sequence[4];
 673         u8 pad[7];
 674 };
 675
 676 struct vendor3_fru {
 677         u8 assembly[6];
 678         u8 revision[2];
 679         u8 serial[14];
 680         u8 pad[3];
 681 };
 682
 683 struct vendor4_fru {
 684         u8 number[8];
 685         u8 part[8];
 686         u8 version[8];
 687         u8 pad[3];
 688 };
 689
 690 union oemfru {
 691         struct vendor1_fru vendor1_fru;
 692         struct vendor2_fru vendor2_fru;
 693         struct vendor3_fru vendor3_fru;
 694         struct vendor4_fru vendor4_fru;
 695 };
 696
 697 /*
 698  * SLIC EEPROM structure for Mojave
 699  */
 700 struct slic_eeprom {
 701         u16 Id;                 /* 00 EEPROM/FLASH Magic code 'A5A5'*/
 702         u16 EecodeSize;         /* 01 Size of EEPROM Codes (bytes * 4)*/
 703         u16 FlashSize;          /* 02 Flash size */
 704         u16 EepromSize;         /* 03 EEPROM Size */
 705         u16 VendorId;           /* 04 Vendor ID */
 706         u16 DeviceId;           /* 05 Device ID */
 707         u8 RevisionId;          /* 06 Revision ID */
 708         u8 ClassCode[3];        /* 07 Class Code */
 709         u8 DbgIntPin;           /* 08 Debug Interrupt pin */
 710         u8 NetIntPin0;          /*    Network Interrupt Pin */
 711         u8 MinGrant;            /* 09 Minimum grant */
 712         u8 MaxLat;              /*    Maximum Latency */
 713         u16 PciStatus;          /* 10 PCI Status */
 714         u16 SubSysVId;          /* 11 Subsystem Vendor Id */
 715         u16 SubSysId;           /* 12 Subsystem ID */
 716         u16 DbgDevId;           /* 13 Debug Device Id */
 717         u16 DramRomFn;          /* 14 Dram/Rom function */
 718         u16 DSize2Pci;          /* 15 DRAM size to PCI (bytes * 64K) */
 719         u16 RSize2Pci;          /* 16 ROM extension size to PCI (bytes * 4k) */
 720         u8 NetIntPin1;          /* 17 Network Interface Pin 1
 721                                     (simba/leone only) */
 722         u8 NetIntPin2;          /* Network Interface Pin 2 (simba/leone only)*/
 723         union {
 724                 u8 NetIntPin3;  /* 18 Network Interface Pin 3 (simba only) */
 725                 u8 FreeTime;    /* FreeTime setting (leone/mojave only) */
 726         } u1;
 727         u8 TBIctl;              /* 10-bit interface control (Mojave only) */
 728         u16 DramSize;           /* 19 DRAM size (bytes * 64k) */
 729         union {
 730                 struct {
 731                         /* Mac Interface Specific portions */
 732                         struct slic_config_mac  MacInfo[SLIC_NBR_MACS];
 733                 } mac;                          /* MAC access for all boards */
 734                 struct {
 735                         /* use above struct for MAC access */
 736                         struct slic_config_mac  pad[SLIC_NBR_MACS - 1];
 737                         u16 DeviceId2;  /* Device ID for 2nd PCI function */
 738                         u8 IntPin2;     /* Interrupt pin for 2nd PCI function */
 739                         u8 ClassCode2[3]; /* Class Code for 2nd PCI function */
 740                 } mojave;       /* 2nd function access for gigabit board */
 741         } u2;
 742         u16 CfgByte6;           /* Config Byte 6 */
 743         u16 PMECapab;           /* Power Mgment capabilities */
 744         u16 NwClkCtrls;         /* NetworkClockControls */
 745         u8 FruFormat;           /* Alacritech FRU format type */
 746         struct atk_fru  AtkFru; /* Alacritech FRU information */
 747         u8 OemFruFormat;        /* optional OEM FRU format type */
 748         union oemfru OemFru;    /* optional OEM FRU information */
 749         u8      Pad[4];         /* Pad to 128 bytes - includes 2 cksum bytes
 750                                  * (if OEM FRU info exists) and two unusable
 751                                  * bytes at the end */
 752 };
 753
 754 /* SLIC EEPROM structure for Oasis */
 755 struct oslic_eeprom {
 756         u16 Id;                 /* 00 EEPROM/FLASH Magic code 'A5A5' */
 757         u16 EecodeSize;         /* 01 Size of EEPROM Codes (bytes * 4)*/
 758         u16 FlashConfig0;       /* 02 Flash Config for SPI device 0 */
 759         u16 FlashConfig1;       /* 03 Flash Config for SPI device 1 */
 760         u16 VendorId;           /* 04 Vendor ID */
 761         u16 DeviceId;           /* 05 Device ID (function 0) */
 762         u8 RevisionId;          /* 06 Revision ID */
 763         u8 ClassCode[3];        /* 07 Class Code for PCI function 0 */
 764         u8 IntPin1;             /* 08 Interrupt pin for PCI function 1*/
 765         u8 ClassCode2[3];       /* 09 Class Code for PCI function 1 */
 766         u8 IntPin2;             /* 10 Interrupt pin for PCI function 2*/
 767         u8 IntPin0;             /*    Interrupt pin for PCI function 0*/
 768         u8 MinGrant;            /* 11 Minimum grant */
 769         u8 MaxLat;              /*    Maximum Latency */
 770         u16 SubSysVId;          /* 12 Subsystem Vendor Id */
 771         u16 SubSysId;           /* 13 Subsystem ID */
 772         u16 FlashSize;          /* 14 Flash size (bytes / 4K) */
 773         u16 DSize2Pci;          /* 15 DRAM size to PCI (bytes / 64K) */
 774         u16 RSize2Pci;          /* 16 Flash (ROM extension) size to PCI
 775                                         (bytes / 4K) */
 776         u16 DeviceId1;          /* 17 Device Id (function 1) */
 777         u16 DeviceId2;          /* 18 Device Id (function 2) */
 778         u16 CfgByte6;           /* 19 Device Status Config Bytes 6-7 */
 779         u16 PMECapab;           /* 20 Power Mgment capabilities */
 780         u8 MSICapab;            /* 21 MSI capabilities */
 781         u8 ClockDivider;        /*    Clock divider */
 782         u16 PciStatusLow;       /* 22 PCI Status bits 15:0 */
 783         u16 PciStatusHigh;      /* 23 PCI Status bits 31:16 */
 784         u16 DramConfigLow;      /* 24 DRAM Configuration bits 15:0 */
 785         u16 DramConfigHigh;     /* 25 DRAM Configuration bits 31:16 */
 786         u16 DramSize;           /* 26 DRAM size (bytes / 64K) */
 787         u16 GpioTbiCtl;         /* 27 GPIO/TBI controls for functions 1/0 */
 788         u16 EepromSize;         /* 28 EEPROM Size */
 789         struct slic_config_mac MacInfo[2];      /* 29 MAC addresses (2 ports) */
 790         u8 FruFormat;           /* 35 Alacritech FRU format type */
 791         struct atk_fru  AtkFru; /* Alacritech FRU information */
 792         u8 OemFruFormat;        /* optional OEM FRU format type */
 793         union oemfru OemFru;    /* optional OEM FRU information */
 794         u8 Pad[4];              /* Pad to 128 bytes - includes 2 checksum bytes
 795                                  * (if OEM FRU info exists) and two unusable
 796                                  * bytes at the end
 797                                  */
 798 };
 799
 800 #define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
 801 #define MIN_EECODE_SIZE 0x62    /* code size without optional OEM FRU stuff */
 802
 803 /*
 804  * SLIC CONFIG structure
 805  *
 806  * This structure lives in the CARD structure and is valid for all board types.
 807  * It is filled in from the appropriate EEPROM structure by
 808  * SlicGetConfigData()
 809  */
 810 struct slic_config {
 811         bool EepromValid;       /* Valid EEPROM flag (checksum good?) */
 812         u16 DramSize;           /* DRAM size (bytes / 64K) */
 813         struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
 814         u8 FruFormat;           /* Alacritech FRU format type */
 815         struct atk_fru  AtkFru; /* Alacritech FRU information */
 816         u8 OemFruFormat;        /* optional OEM FRU format type */
 817         union {
 818                 struct vendor1_fru vendor1_fru;
 819                 struct vendor2_fru vendor2_fru;
 820                 struct vendor3_fru vendor3_fru;
 821                 struct vendor4_fru vendor4_fru;
 822         } OemFru;
 823 };
 824
 825 #pragma pack()
 826
 827 #endif