sound/soc/codecs/tlv320aic26.h

   1 /*
   2  * Texas Instruments TLV320AIC26 low power audio CODEC
   3  * register definitions
   4  *
   5  * Copyright (C) 2008 Secret Lab Technologies Ltd.
   6  */
   7
   8 #ifndef _TLV320AIC16_H_
   9 #define _TLV320AIC16_H_
  10
  11 /* AIC26 Registers */
  12 #define AIC26_PAGE_ADDR(page, offset)   ((page << 11) | offset << 5)
  13
  14 /* Page 0: Auxiliary data registers */
  15 #define AIC26_REG_BAT1                  AIC26_PAGE_ADDR(0, 0x05)
  16 #define AIC26_REG_BAT2                  AIC26_PAGE_ADDR(0, 0x06)
  17 #define AIC26_REG_AUX                   AIC26_PAGE_ADDR(0, 0x07)
  18 #define AIC26_REG_TEMP1                 AIC26_PAGE_ADDR(0, 0x09)
  19 #define AIC26_REG_TEMP2                 AIC26_PAGE_ADDR(0, 0x0A)
  20
  21 /* Page 1: Auxiliary control registers */
  22 #define AIC26_REG_AUX_ADC               AIC26_PAGE_ADDR(1, 0x00)
  23 #define AIC26_REG_STATUS                AIC26_PAGE_ADDR(1, 0x01)
  24 #define AIC26_REG_REFERENCE             AIC26_PAGE_ADDR(1, 0x03)
  25 #define AIC26_REG_RESET                 AIC26_PAGE_ADDR(1, 0x04)
  26
  27 /* Page 2: Audio control registers */
  28 #define AIC26_REG_AUDIO_CTRL1           AIC26_PAGE_ADDR(2, 0x00)
  29 #define AIC26_REG_ADC_GAIN              AIC26_PAGE_ADDR(2, 0x01)
  30 #define AIC26_REG_DAC_GAIN              AIC26_PAGE_ADDR(2, 0x02)
  31 #define AIC26_REG_SIDETONE              AIC26_PAGE_ADDR(2, 0x03)
  32 #define AIC26_REG_AUDIO_CTRL2           AIC26_PAGE_ADDR(2, 0x04)
  33 #define AIC26_REG_POWER_CTRL            AIC26_PAGE_ADDR(2, 0x05)
  34 #define AIC26_REG_AUDIO_CTRL3           AIC26_PAGE_ADDR(2, 0x06)
  35
  36 #define AIC26_REG_FILTER_COEFF_L_N0     AIC26_PAGE_ADDR(2, 0x07)
  37 #define AIC26_REG_FILTER_COEFF_L_N1     AIC26_PAGE_ADDR(2, 0x08)
  38 #define AIC26_REG_FILTER_COEFF_L_N2     AIC26_PAGE_ADDR(2, 0x09)
  39 #define AIC26_REG_FILTER_COEFF_L_N3     AIC26_PAGE_ADDR(2, 0x0A)
  40 #define AIC26_REG_FILTER_COEFF_L_N4     AIC26_PAGE_ADDR(2, 0x0B)
  41 #define AIC26_REG_FILTER_COEFF_L_N5     AIC26_PAGE_ADDR(2, 0x0C)
  42 #define AIC26_REG_FILTER_COEFF_L_D1     AIC26_PAGE_ADDR(2, 0x0D)
  43 #define AIC26_REG_FILTER_COEFF_L_D2     AIC26_PAGE_ADDR(2, 0x0E)
  44 #define AIC26_REG_FILTER_COEFF_L_D4     AIC26_PAGE_ADDR(2, 0x0F)
  45 #define AIC26_REG_FILTER_COEFF_L_D5     AIC26_PAGE_ADDR(2, 0x10)
  46 #define AIC26_REG_FILTER_COEFF_R_N0     AIC26_PAGE_ADDR(2, 0x11)
  47 #define AIC26_REG_FILTER_COEFF_R_N1     AIC26_PAGE_ADDR(2, 0x12)
  48 #define AIC26_REG_FILTER_COEFF_R_N2     AIC26_PAGE_ADDR(2, 0x13)
  49 #define AIC26_REG_FILTER_COEFF_R_N3     AIC26_PAGE_ADDR(2, 0x14)
  50 #define AIC26_REG_FILTER_COEFF_R_N4     AIC26_PAGE_ADDR(2, 0x15)
  51 #define AIC26_REG_FILTER_COEFF_R_N5     AIC26_PAGE_ADDR(2, 0x16)
  52 #define AIC26_REG_FILTER_COEFF_R_D1     AIC26_PAGE_ADDR(2, 0x17)
  53 #define AIC26_REG_FILTER_COEFF_R_D2     AIC26_PAGE_ADDR(2, 0x18)
  54 #define AIC26_REG_FILTER_COEFF_R_D4     AIC26_PAGE_ADDR(2, 0x19)
  55 #define AIC26_REG_FILTER_COEFF_R_D5     AIC26_PAGE_ADDR(2, 0x1A)
  56
  57 #define AIC26_REG_PLL_PROG1             AIC26_PAGE_ADDR(2, 0x1B)
  58 #define AIC26_REG_PLL_PROG2             AIC26_PAGE_ADDR(2, 0x1C)
  59 #define AIC26_REG_AUDIO_CTRL4           AIC26_PAGE_ADDR(2, 0x1D)
  60 #define AIC26_REG_AUDIO_CTRL5           AIC26_PAGE_ADDR(2, 0x1E)
  61
  62 /* fsref dividers; used in register 'Audio Control 1' */
  63 enum aic26_divisors {
  64         AIC26_DIV_1     = 0,
  65         AIC26_DIV_1_5   = 1,
  66         AIC26_DIV_2     = 2,
  67         AIC26_DIV_3     = 3,
  68         AIC26_DIV_4     = 4,
  69         AIC26_DIV_5     = 5,
  70         AIC26_DIV_5_5   = 6,
  71         AIC26_DIV_6     = 7,
  72 };
  73
  74 /* Digital data format */
  75 enum aic26_datfm {
  76         AIC26_DATFM_I2S         = 0 << 8,
  77         AIC26_DATFM_DSP         = 1 << 8,
  78         AIC26_DATFM_RIGHTJ      = 2 << 8, /* right justified */
  79         AIC26_DATFM_LEFTJ       = 3 << 8, /* left justified */
  80 };
  81
  82 /* Sample word length in bits; used in register 'Audio Control 1' */
  83 enum aic26_wlen {
  84         AIC26_WLEN_16   = 0 << 10,
  85         AIC26_WLEN_20   = 1 << 10,
  86         AIC26_WLEN_24   = 2 << 10,
  87         AIC26_WLEN_32   = 3 << 10,
  88 };
  89
  90 #endif /* _TLV320AIC16_H_ */