sound/soc/tegra/tegra30_i2s.c

   1 /*
   2  * tegra30_i2s.c - Tegra30 I2S driver
   3  *
   4  * Author: Stephen Warren <swarren@nvidia.com>
   5  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Based on code copyright/by:
   8  *
   9  * Copyright (c) 2009-2010, NVIDIA Corporation.
  10  * Scott Peterson <speterson@nvidia.com>
  11  *
  12  * Copyright (C) 2010 Google, Inc.
  13  * Iliyan Malchev <malchev@google.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms and conditions of the GNU General Public License,
  17  * version 2, as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope it will be useful, but WITHOUT
  20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  22  * more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/device.h>
  30 #include <linux/io.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/regmap.h>
  37 #include <linux/slab.h>
  38 #include <sound/core.h>
  39 #include <sound/pcm.h>
  40 #include <sound/pcm_params.h>
  41 #include <sound/soc.h>
  42 #include <sound/dmaengine_pcm.h>
  43
  44 #include "tegra30_ahub.h"
  45 #include "tegra30_i2s.h"
  46
  47 #define DRV_NAME "tegra30-i2s"
  48
  49 static int tegra30_i2s_runtime_suspend(struct device *dev)
  50 {
  51         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  52
  53         regcache_cache_only(i2s->regmap, true);
  54
  55         clk_disable_unprepare(i2s->clk_i2s);
  56
  57         return 0;
  58 }
  59
  60 static int tegra30_i2s_runtime_resume(struct device *dev)
  61 {
  62         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  63         int ret;
  64
  65         ret = clk_prepare_enable(i2s->clk_i2s);
  66         if (ret) {
  67                 dev_err(dev, "clk_enable failed: %d\n", ret);
  68                 return ret;
  69         }
  70
  71         regcache_cache_only(i2s->regmap, false);
  72
  73         return 0;
  74 }
  75
  76 static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
  77                         struct snd_soc_dai *dai)
  78 {
  79         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  80         int ret;
  81
  82         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  83                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
  84                                         &i2s->playback_dma_data.addr,
  85                                         &i2s->playback_dma_data.slave_id);
  86                 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  87                 i2s->playback_dma_data.maxburst = 4;
  88                 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
  89                                                i2s->playback_fifo_cif);
  90         } else {
  91                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
  92                                         &i2s->capture_dma_data.addr,
  93                                         &i2s->capture_dma_data.slave_id);
  94                 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  95                 i2s->capture_dma_data.maxburst = 4;
  96                 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
  97                                                i2s->capture_i2s_cif);
  98         }
  99
 100         return ret;
 101 }
 102
 103 static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
 104                         struct snd_soc_dai *dai)
 105 {
 106         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 107
 108         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 109                 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
 110                 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
 111         } else {
 112                 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
 113                 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
 114         }
 115 }
 116
 117 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 118                                 unsigned int fmt)
 119 {
 120         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 121         unsigned int mask, val;
 122
 123         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 124         case SND_SOC_DAIFMT_NB_NF:
 125                 break;
 126         default:
 127                 return -EINVAL;
 128         }
 129
 130         mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
 131         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 132         case SND_SOC_DAIFMT_CBS_CFS:
 133                 val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
 134                 break;
 135         case SND_SOC_DAIFMT_CBM_CFM:
 136                 break;
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
 142                 TEGRA30_I2S_CTRL_LRCK_MASK;
 143         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 144         case SND_SOC_DAIFMT_DSP_A:
 145                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 146                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 147                 break;
 148         case SND_SOC_DAIFMT_DSP_B:
 149                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 150                 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
 151                 break;
 152         case SND_SOC_DAIFMT_I2S:
 153                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 154                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 155                 break;
 156         case SND_SOC_DAIFMT_RIGHT_J:
 157                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 158                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 159                 break;
 160         case SND_SOC_DAIFMT_LEFT_J:
 161                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 162                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 163                 break;
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         pm_runtime_get_sync(dai->dev);
 169         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
 170         pm_runtime_put(dai->dev);
 171
 172         return 0;
 173 }
 174
 175 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
 176                                  struct snd_pcm_hw_params *params,
 177                                  struct snd_soc_dai *dai)
 178 {
 179         struct device *dev = dai->dev;
 180         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 181         unsigned int mask, val, reg;
 182         int ret, sample_size, srate, i2sclock, bitcnt;
 183         struct tegra30_ahub_cif_conf cif_conf;
 184
 185         if (params_channels(params) != 2)
 186                 return -EINVAL;
 187
 188         mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
 189         switch (params_format(params)) {
 190         case SNDRV_PCM_FORMAT_S16_LE:
 191                 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
 192                 sample_size = 16;
 193                 break;
 194         default:
 195                 return -EINVAL;
 196         }
 197
 198         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
 199
 200         srate = params_rate(params);
 201
 202         /* Final "* 2" required by Tegra hardware */
 203         i2sclock = srate * params_channels(params) * sample_size * 2;
 204
 205         bitcnt = (i2sclock / (2 * srate)) - 1;
 206         if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
 207                 return -EINVAL;
 208
 209         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
 210         if (ret) {
 211                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
 212                 return ret;
 213         }
 214
 215         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 216
 217         if (i2sclock % (2 * srate))
 218                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
 219
 220         regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
 221
 222         cif_conf.threshold = 0;
 223         cif_conf.audio_channels = 2;
 224         cif_conf.client_channels = 2;
 225         cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
 226         cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
 227         cif_conf.expand = 0;
 228         cif_conf.stereo_conv = 0;
 229         cif_conf.replicate = 0;
 230         cif_conf.truncate = 0;
 231         cif_conf.mono_conv = 0;
 232
 233         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 234                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
 235                 reg = TEGRA30_I2S_CIF_RX_CTRL;
 236         } else {
 237                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
 238                 reg = TEGRA30_I2S_CIF_TX_CTRL;
 239         }
 240
 241         i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
 242
 243         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
 244               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
 245         regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
 246
 247         return 0;
 248 }
 249
 250 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
 251 {
 252         tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
 253         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
 254                            TEGRA30_I2S_CTRL_XFER_EN_TX,
 255                            TEGRA30_I2S_CTRL_XFER_EN_TX);
 256 }
 257
 258 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
 259 {
 260         tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
 261         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
 262                            TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
 263 }
 264
 265 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
 266 {
 267         tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
 268         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
 269                            TEGRA30_I2S_CTRL_XFER_EN_RX,
 270                            TEGRA30_I2S_CTRL_XFER_EN_RX);
 271 }
 272
 273 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
 274 {
 275         tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
 276         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
 277                            TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
 278 }
 279
 280 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 281                                 struct snd_soc_dai *dai)
 282 {
 283         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 284
 285         switch (cmd) {
 286         case SNDRV_PCM_TRIGGER_START:
 287         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 288         case SNDRV_PCM_TRIGGER_RESUME:
 289                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 290                         tegra30_i2s_start_playback(i2s);
 291                 else
 292                         tegra30_i2s_start_capture(i2s);
 293                 break;
 294         case SNDRV_PCM_TRIGGER_STOP:
 295         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 296         case SNDRV_PCM_TRIGGER_SUSPEND:
 297                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 298                         tegra30_i2s_stop_playback(i2s);
 299                 else
 300                         tegra30_i2s_stop_capture(i2s);
 301                 break;
 302         default:
 303                 return -EINVAL;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
 310 {
 311         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 312
 313         dai->capture_dma_data = &i2s->capture_dma_data;
 314         dai->playback_dma_data = &i2s->playback_dma_data;
 315
 316         return 0;
 317 }
 318
 319 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
 320         .startup        = tegra30_i2s_startup,
 321         .shutdown       = tegra30_i2s_shutdown,
 322         .set_fmt        = tegra30_i2s_set_fmt,
 323         .hw_params      = tegra30_i2s_hw_params,
 324         .trigger        = tegra30_i2s_trigger,
 325 };
 326
 327 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
 328         .probe = tegra30_i2s_probe,
 329         .playback = {
 330                 .stream_name = "Playback",
 331                 .channels_min = 2,
 332                 .channels_max = 2,
 333                 .rates = SNDRV_PCM_RATE_8000_96000,
 334                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 335         },
 336         .capture = {
 337                 .stream_name = "Capture",
 338                 .channels_min = 2,
 339                 .channels_max = 2,
 340                 .rates = SNDRV_PCM_RATE_8000_96000,
 341                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 342         },
 343         .ops = &tegra30_i2s_dai_ops,
 344         .symmetric_rates = 1,
 345 };
 346
 347 static const struct snd_soc_component_driver tegra30_i2s_component = {
 348         .name           = DRV_NAME,
 349 };
 350
 351 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
 352 {
 353         switch (reg) {
 354         case TEGRA30_I2S_CTRL:
 355         case TEGRA30_I2S_TIMING:
 356         case TEGRA30_I2S_OFFSET:
 357         case TEGRA30_I2S_CH_CTRL:
 358         case TEGRA30_I2S_SLOT_CTRL:
 359         case TEGRA30_I2S_CIF_RX_CTRL:
 360         case TEGRA30_I2S_CIF_TX_CTRL:
 361         case TEGRA30_I2S_FLOWCTL:
 362         case TEGRA30_I2S_TX_STEP:
 363         case TEGRA30_I2S_FLOW_STATUS:
 364         case TEGRA30_I2S_FLOW_TOTAL:
 365         case TEGRA30_I2S_FLOW_OVER:
 366         case TEGRA30_I2S_FLOW_UNDER:
 367         case TEGRA30_I2S_LCOEF_1_4_0:
 368         case TEGRA30_I2S_LCOEF_1_4_1:
 369         case TEGRA30_I2S_LCOEF_1_4_2:
 370         case TEGRA30_I2S_LCOEF_1_4_3:
 371         case TEGRA30_I2S_LCOEF_1_4_4:
 372         case TEGRA30_I2S_LCOEF_1_4_5:
 373         case TEGRA30_I2S_LCOEF_2_4_0:
 374         case TEGRA30_I2S_LCOEF_2_4_1:
 375         case TEGRA30_I2S_LCOEF_2_4_2:
 376                 return true;
 377         default:
 378                 return false;
 379         }
 380 }
 381
 382 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
 383 {
 384         switch (reg) {
 385         case TEGRA30_I2S_FLOW_STATUS:
 386         case TEGRA30_I2S_FLOW_TOTAL:
 387         case TEGRA30_I2S_FLOW_OVER:
 388         case TEGRA30_I2S_FLOW_UNDER:
 389                 return true;
 390         default:
 391                 return false;
 392         }
 393 }
 394
 395 static const struct regmap_config tegra30_i2s_regmap_config = {
 396         .reg_bits = 32,
 397         .reg_stride = 4,
 398         .val_bits = 32,
 399         .max_register = TEGRA30_I2S_LCOEF_2_4_2,
 400         .writeable_reg = tegra30_i2s_wr_rd_reg,
 401         .readable_reg = tegra30_i2s_wr_rd_reg,
 402         .volatile_reg = tegra30_i2s_volatile_reg,
 403         .cache_type = REGCACHE_RBTREE,
 404 };
 405
 406 static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
 407         .set_audio_cif = tegra30_ahub_set_cif,
 408 };
 409
 410 static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
 411         .set_audio_cif = tegra124_ahub_set_cif,
 412 };
 413
 414 static const struct of_device_id tegra30_i2s_of_match[] = {
 415         { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
 416         { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
 417         {},
 418 };
 419
 420 static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 421 {
 422         struct tegra30_i2s *i2s;
 423         const struct of_device_id *match;
 424         u32 cif_ids[2];
 425         struct resource *mem, *memregion;
 426         void __iomem *regs;
 427         int ret;
 428
 429         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
 430         if (!i2s) {
 431                 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
 432                 ret = -ENOMEM;
 433                 goto err;
 434         }
 435         dev_set_drvdata(&pdev->dev, i2s);
 436
 437         match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
 438         if (!match) {
 439                 dev_err(&pdev->dev, "Error: No device match found\n");
 440                 ret = -ENODEV;
 441                 goto err;
 442         }
 443         i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
 444
 445         i2s->dai = tegra30_i2s_dai_template;
 446         i2s->dai.name = dev_name(&pdev->dev);
 447
 448         ret = of_property_read_u32_array(pdev->dev.of_node,
 449                                          "nvidia,ahub-cif-ids", cif_ids,
 450                                          ARRAY_SIZE(cif_ids));
 451         if (ret < 0)
 452                 goto err;
 453
 454         i2s->playback_i2s_cif = cif_ids[0];
 455         i2s->capture_i2s_cif = cif_ids[1];
 456
 457         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
 458         if (IS_ERR(i2s->clk_i2s)) {
 459                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 460                 ret = PTR_ERR(i2s->clk_i2s);
 461                 goto err;
 462         }
 463
 464         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 465         if (!mem) {
 466                 dev_err(&pdev->dev, "No memory resource\n");
 467                 ret = -ENODEV;
 468                 goto err_clk_put;
 469         }
 470
 471         memregion = devm_request_mem_region(&pdev->dev, mem->start,
 472                                             resource_size(mem), DRV_NAME);
 473         if (!memregion) {
 474                 dev_err(&pdev->dev, "Memory region already claimed\n");
 475                 ret = -EBUSY;
 476                 goto err_clk_put;
 477         }
 478
 479         regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 480         if (!regs) {
 481                 dev_err(&pdev->dev, "ioremap failed\n");
 482                 ret = -ENOMEM;
 483                 goto err_clk_put;
 484         }
 485
 486         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 487                                             &tegra30_i2s_regmap_config);
 488         if (IS_ERR(i2s->regmap)) {
 489                 dev_err(&pdev->dev, "regmap init failed\n");
 490                 ret = PTR_ERR(i2s->regmap);
 491                 goto err_clk_put;
 492         }
 493         regcache_cache_only(i2s->regmap, true);
 494
 495         pm_runtime_enable(&pdev->dev);
 496         if (!pm_runtime_enabled(&pdev->dev)) {
 497                 ret = tegra30_i2s_runtime_resume(&pdev->dev);
 498                 if (ret)
 499                         goto err_pm_disable;
 500         }
 501
 502         ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
 503                                    &i2s->dai, 1);
 504         if (ret) {
 505                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 506                 ret = -ENOMEM;
 507                 goto err_suspend;
 508         }
 509
 510         ret = tegra_pcm_platform_register(&pdev->dev);
 511         if (ret) {
 512                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 513                 goto err_unregister_component;
 514         }
 515
 516         return 0;
 517
 518 err_unregister_component:
 519         snd_soc_unregister_component(&pdev->dev);
 520 err_suspend:
 521         if (!pm_runtime_status_suspended(&pdev->dev))
 522                 tegra30_i2s_runtime_suspend(&pdev->dev);
 523 err_pm_disable:
 524         pm_runtime_disable(&pdev->dev);
 525 err_clk_put:
 526         clk_put(i2s->clk_i2s);
 527 err:
 528         return ret;
 529 }
 530
 531 static int tegra30_i2s_platform_remove(struct platform_device *pdev)
 532 {
 533         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
 534
 535         pm_runtime_disable(&pdev->dev);
 536         if (!pm_runtime_status_suspended(&pdev->dev))
 537                 tegra30_i2s_runtime_suspend(&pdev->dev);
 538
 539         tegra_pcm_platform_unregister(&pdev->dev);
 540         snd_soc_unregister_component(&pdev->dev);
 541
 542         clk_put(i2s->clk_i2s);
 543
 544         return 0;
 545 }
 546
 547 #ifdef CONFIG_PM_SLEEP
 548 static int tegra30_i2s_suspend(struct device *dev)
 549 {
 550         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 551
 552         regcache_mark_dirty(i2s->regmap);
 553
 554         return 0;
 555 }
 556
 557 static int tegra30_i2s_resume(struct device *dev)
 558 {
 559         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 560         int ret;
 561
 562         ret = pm_runtime_get_sync(dev);
 563         if (ret < 0)
 564                 return ret;
 565         ret = regcache_sync(i2s->regmap);
 566         pm_runtime_put(dev);
 567
 568         return ret;
 569 }
 570 #endif
 571
 572 static const struct dev_pm_ops tegra30_i2s_pm_ops = {
 573         SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
 574                            tegra30_i2s_runtime_resume, NULL)
 575         SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
 576 };
 577
 578 static struct platform_driver tegra30_i2s_driver = {
 579         .driver = {
 580                 .name = DRV_NAME,
 581                 .owner = THIS_MODULE,
 582                 .of_match_table = tegra30_i2s_of_match,
 583                 .pm = &tegra30_i2s_pm_ops,
 584         },
 585         .probe = tegra30_i2s_platform_probe,
 586         .remove = tegra30_i2s_platform_remove,
 587 };
 588 module_platform_driver(tegra30_i2s_driver);
 589
 590 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 591 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
 592 MODULE_LICENSE("GPL");
 593 MODULE_ALIAS("platform:" DRV_NAME);
 594 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);