drivers/irqchip/irq-sun4i.c

   1 /*
   2  * Allwinner A1X SoCs IRQ chip driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <asm/exception.h>
  24 #include <asm/mach/irq.h>
  25
  26 #include "irqchip.h"
  27
  28 #define SUN4I_IRQ_VECTOR_REG            0x00
  29 #define SUN4I_IRQ_PROTECTION_REG        0x08
  30 #define SUN4I_IRQ_NMI_CTRL_REG          0x0c
  31 #define SUN4I_IRQ_PENDING_REG(x)        (0x10 + 0x4 * x)
  32 #define SUN4I_IRQ_FIQ_PENDING_REG(x)    (0x20 + 0x4 * x)
  33 #define SUN4I_IRQ_ENABLE_REG(x)         (0x40 + 0x4 * x)
  34 #define SUN4I_IRQ_MASK_REG(x)           (0x50 + 0x4 * x)
  35
  36 static void __iomem *sun4i_irq_base;
  37 static struct irq_domain *sun4i_irq_domain;
  38
  39 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
  40
  41 static void sun4i_irq_ack(struct irq_data *irqd)
  42 {
  43         unsigned int irq = irqd_to_hwirq(irqd);
  44
  45         if (irq != 0)
  46                 return; /* Only IRQ 0 / the ENMI needs to be acked */
  47
  48         writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
  49 }
  50
  51 static void sun4i_irq_mask(struct irq_data *irqd)
  52 {
  53         unsigned int irq = irqd_to_hwirq(irqd);
  54         unsigned int irq_off = irq % 32;
  55         int reg = irq / 32;
  56         u32 val;
  57
  58         val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  59         writel(val & ~(1 << irq_off),
  60                sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  61 }
  62
  63 static void sun4i_irq_unmask(struct irq_data *irqd)
  64 {
  65         unsigned int irq = irqd_to_hwirq(irqd);
  66         unsigned int irq_off = irq % 32;
  67         int reg = irq / 32;
  68         u32 val;
  69
  70         val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  71         writel(val | (1 << irq_off),
  72                sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
  73 }
  74
  75 static struct irq_chip sun4i_irq_chip = {
  76         .name           = "sun4i_irq",
  77         .irq_eoi        = sun4i_irq_ack,
  78         .irq_mask       = sun4i_irq_mask,
  79         .irq_unmask     = sun4i_irq_unmask,
  80         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
  81 };
  82
  83 static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
  84                          irq_hw_number_t hw)
  85 {
  86         irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
  87         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
  88
  89         return 0;
  90 }
  91
  92 static struct irq_domain_ops sun4i_irq_ops = {
  93         .map = sun4i_irq_map,
  94         .xlate = irq_domain_xlate_onecell,
  95 };
  96
  97 static int __init sun4i_of_init(struct device_node *node,
  98                                 struct device_node *parent)
  99 {
 100         sun4i_irq_base = of_iomap(node, 0);
 101         if (!sun4i_irq_base)
 102                 panic("%s: unable to map IC registers\n",
 103                         node->full_name);
 104
 105         /* Disable all interrupts */
 106         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
 107         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
 108         writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
 109
 110         /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
 111         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
 112         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
 113         writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
 114
 115         /* Clear all the pending interrupts */
 116         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
 117         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
 118         writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
 119
 120         /* Enable protection mode */
 121         writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
 122
 123         /* Configure the external interrupt source type */
 124         writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
 125
 126         sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
 127                                                  &sun4i_irq_ops, NULL);
 128         if (!sun4i_irq_domain)
 129                 panic("%s: unable to create IRQ domain\n", node->full_name);
 130
 131         set_handle_irq(sun4i_handle_irq);
 132
 133         return 0;
 134 }
 135 IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
 136
 137 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
 138 {
 139         u32 irq, hwirq;
 140
 141         /*
 142          * hwirq == 0 can mean one of 3 things:
 143          * 1) no more irqs pending
 144          * 2) irq 0 pending
 145          * 3) spurious irq
 146          * So if we immediately get a reading of 0, check the irq-pending reg
 147          * to differentiate between 2 and 3. We only do this once to avoid
 148          * the extra check in the common case of 1 hapening after having
 149          * read the vector-reg once.
 150          */
 151         hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
 152         if (hwirq == 0 &&
 153                   !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
 154                 return;
 155
 156         do {
 157                 irq = irq_find_mapping(sun4i_irq_domain, hwirq);
 158                 handle_IRQ(irq, regs);
 159                 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
 160         } while (hwirq != 0);
 161 }