drivers/mtd/nand/onenand/omap2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  OneNAND driver for OMAP2 / OMAP3
   4  *
   5  *  Copyright © 2005-2006 Nokia Corporation
   6  *
   7  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   8  *  IRQ and DMA support written by Timo Teras
   9  */
  10
  11 #include <linux/device.h>
  12 #include <linux/module.h>
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/onenand.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/of_device.h>
  17 #include <linux/omap-gpmc.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/gpio/consumer.h>
  26
  27 #include <asm/mach/flash.h>
  28
  29 #define DRIVER_NAME "omap2-onenand"
  30
  31 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  32
  33 struct omap2_onenand {
  34         struct platform_device *pdev;
  35         int gpmc_cs;
  36         unsigned long phys_base;
  37         struct gpio_desc *int_gpiod;
  38         struct mtd_info mtd;
  39         struct onenand_chip onenand;
  40         struct completion irq_done;
  41         struct completion dma_done;
  42         struct dma_chan *dma_chan;
  43 };
  44
  45 static void omap2_onenand_dma_complete_func(void *completion)
  46 {
  47         complete(completion);
  48 }
  49
  50 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  51 {
  52         struct omap2_onenand *c = dev_id;
  53
  54         complete(&c->irq_done);
  55
  56         return IRQ_HANDLED;
  57 }
  58
  59 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  60 {
  61         return readw(c->onenand.base + reg);
  62 }
  63
  64 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  65                              int reg)
  66 {
  67         writew(value, c->onenand.base + reg);
  68 }
  69
  70 static int omap2_onenand_set_cfg(struct omap2_onenand *c,
  71                                  bool sr, bool sw,
  72                                  int latency, int burst_len)
  73 {
  74         unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
  75
  76         reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
  77
  78         switch (burst_len) {
  79         case 0:         /* continuous */
  80                 break;
  81         case 4:
  82                 reg |= ONENAND_SYS_CFG1_BL_4;
  83                 break;
  84         case 8:
  85                 reg |= ONENAND_SYS_CFG1_BL_8;
  86                 break;
  87         case 16:
  88                 reg |= ONENAND_SYS_CFG1_BL_16;
  89                 break;
  90         case 32:
  91                 reg |= ONENAND_SYS_CFG1_BL_32;
  92                 break;
  93         default:
  94                 return -EINVAL;
  95         }
  96
  97         if (latency > 5)
  98                 reg |= ONENAND_SYS_CFG1_HF;
  99         if (latency > 7)
 100                 reg |= ONENAND_SYS_CFG1_VHF;
 101         if (sr)
 102                 reg |= ONENAND_SYS_CFG1_SYNC_READ;
 103         if (sw)
 104                 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 105
 106         write_reg(c, reg, ONENAND_REG_SYS_CFG1);
 107
 108         return 0;
 109 }
 110
 111 static int omap2_onenand_get_freq(int ver)
 112 {
 113         switch ((ver >> 4) & 0xf) {
 114         case 0:
 115                 return 40;
 116         case 1:
 117                 return 54;
 118         case 2:
 119                 return 66;
 120         case 3:
 121                 return 83;
 122         case 4:
 123                 return 104;
 124         }
 125
 126         return -EINVAL;
 127 }
 128
 129 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
 130 {
 131         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
 132                msg, state, ctrl, intr);
 133 }
 134
 135 static void wait_warn(char *msg, int state, unsigned int ctrl,
 136                       unsigned int intr)
 137 {
 138         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 139                "intr 0x%04x\n", msg, state, ctrl, intr);
 140 }
 141
 142 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 143 {
 144         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 145         struct onenand_chip *this = mtd->priv;
 146         unsigned int intr = 0;
 147         unsigned int ctrl, ctrl_mask;
 148         unsigned long timeout;
 149         u32 syscfg;
 150
 151         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 152             state == FL_VERIFYING_ERASE) {
 153                 int i = 21;
 154                 unsigned int intr_flags = ONENAND_INT_MASTER;
 155
 156                 switch (state) {
 157                 case FL_RESETING:
 158                         intr_flags |= ONENAND_INT_RESET;
 159                         break;
 160                 case FL_PREPARING_ERASE:
 161                         intr_flags |= ONENAND_INT_ERASE;
 162                         break;
 163                 case FL_VERIFYING_ERASE:
 164                         i = 101;
 165                         break;
 166                 }
 167
 168                 while (--i) {
 169                         udelay(1);
 170                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 171                         if (intr & ONENAND_INT_MASTER)
 172                                 break;
 173                 }
 174                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 175                 if (ctrl & ONENAND_CTRL_ERROR) {
 176                         wait_err("controller error", state, ctrl, intr);
 177                         return -EIO;
 178                 }
 179                 if ((intr & intr_flags) == intr_flags)
 180                         return 0;
 181                 /* Continue in wait for interrupt branch */
 182         }
 183
 184         if (state != FL_READING) {
 185                 int result;
 186
 187                 /* Turn interrupts on */
 188                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 189                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 190                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 191                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 192                         /* Add a delay to let GPIO settle */
 193                         syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 194                 }
 195
 196                 reinit_completion(&c->irq_done);
 197                 result = gpiod_get_value(c->int_gpiod);
 198                 if (result < 0) {
 199                         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 200                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 201                         wait_err("gpio error", state, ctrl, intr);
 202                         return result;
 203                 } else if (result == 0) {
 204                         int retry_cnt = 0;
 205 retry:
 206                         if (!wait_for_completion_io_timeout(&c->irq_done,
 207                                                 msecs_to_jiffies(20))) {
 208                                 /* Timeout after 20ms */
 209                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 210                                 if (ctrl & ONENAND_CTRL_ONGO &&
 211                                     !this->ongoing) {
 212                                         /*
 213                                          * The operation seems to be still going
 214                                          * so give it some more time.
 215                                          */
 216                                         retry_cnt += 1;
 217                                         if (retry_cnt < 3)
 218                                                 goto retry;
 219                                         intr = read_reg(c,
 220                                                         ONENAND_REG_INTERRUPT);
 221                                         wait_err("timeout", state, ctrl, intr);
 222                                         return -EIO;
 223                                 }
 224                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 225                                 if ((intr & ONENAND_INT_MASTER) == 0)
 226                                         wait_warn("timeout", state, ctrl, intr);
 227                         }
 228                 }
 229         } else {
 230                 int retry_cnt = 0;
 231
 232                 /* Turn interrupts off */
 233                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 234                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 235                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 236
 237                 timeout = jiffies + msecs_to_jiffies(20);
 238                 while (1) {
 239                         if (time_before(jiffies, timeout)) {
 240                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 241                                 if (intr & ONENAND_INT_MASTER)
 242                                         break;
 243                         } else {
 244                                 /* Timeout after 20ms */
 245                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 246                                 if (ctrl & ONENAND_CTRL_ONGO) {
 247                                         /*
 248                                          * The operation seems to be still going
 249                                          * so give it some more time.
 250                                          */
 251                                         retry_cnt += 1;
 252                                         if (retry_cnt < 3) {
 253                                                 timeout = jiffies +
 254                                                           msecs_to_jiffies(20);
 255                                                 continue;
 256                                         }
 257                                 }
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 264         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 265
 266         if (intr & ONENAND_INT_READ) {
 267                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 268
 269                 if (ecc) {
 270                         unsigned int addr1, addr8;
 271
 272                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 273                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 274                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 275                                 printk(KERN_ERR "onenand_wait: ECC error = "
 276                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 277                                        ecc, addr1, addr8);
 278                                 mtd->ecc_stats.failed++;
 279                                 return -EBADMSG;
 280                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 281                                 printk(KERN_NOTICE "onenand_wait: correctable "
 282                                        "ECC error = 0x%04x, addr1 %#x, "
 283                                        "addr8 %#x\n", ecc, addr1, addr8);
 284                                 mtd->ecc_stats.corrected++;
 285                         }
 286                 }
 287         } else if (state == FL_READING) {
 288                 wait_err("timeout", state, ctrl, intr);
 289                 return -EIO;
 290         }
 291
 292         if (ctrl & ONENAND_CTRL_ERROR) {
 293                 wait_err("controller error", state, ctrl, intr);
 294                 if (ctrl & ONENAND_CTRL_LOCK)
 295                         printk(KERN_ERR "onenand_wait: "
 296                                         "Device is write protected!!!\n");
 297                 return -EIO;
 298         }
 299
 300         ctrl_mask = 0xFE9F;
 301         if (this->ongoing)
 302                 ctrl_mask &= ~0x8000;
 303
 304         if (ctrl & ctrl_mask)
 305                 wait_warn("unexpected controller status", state, ctrl, intr);
 306
 307         return 0;
 308 }
 309
 310 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 311 {
 312         struct onenand_chip *this = mtd->priv;
 313
 314         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 315                 if (area == ONENAND_DATARAM)
 316                         return this->writesize;
 317                 if (area == ONENAND_SPARERAM)
 318                         return mtd->oobsize;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 325                                              dma_addr_t src, dma_addr_t dst,
 326                                              size_t count)
 327 {
 328         struct dma_async_tx_descriptor *tx;
 329         dma_cookie_t cookie;
 330
 331         tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
 332         if (!tx) {
 333                 dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
 334                 return -EIO;
 335         }
 336
 337         reinit_completion(&c->dma_done);
 338
 339         tx->callback = omap2_onenand_dma_complete_func;
 340         tx->callback_param = &c->dma_done;
 341
 342         cookie = tx->tx_submit(tx);
 343         if (dma_submit_error(cookie)) {
 344                 dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
 345                 return -EIO;
 346         }
 347
 348         dma_async_issue_pending(c->dma_chan);
 349
 350         if (!wait_for_completion_io_timeout(&c->dma_done,
 351                                             msecs_to_jiffies(20))) {
 352                 dmaengine_terminate_sync(c->dma_chan);
 353                 return -ETIMEDOUT;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 360                                         unsigned char *buffer, int offset,
 361                                         size_t count)
 362 {
 363         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 364         struct onenand_chip *this = mtd->priv;
 365         struct device *dev = &c->pdev->dev;
 366         void *buf = (void *)buffer;
 367         dma_addr_t dma_src, dma_dst;
 368         int bram_offset, err;
 369         size_t xtra;
 370
 371         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 372         /*
 373          * If the buffer address is not DMA-able, len is not long enough to make
 374          * DMA transfers profitable or panic_write() may be in an interrupt
 375          * context fallback to PIO mode.
 376          */
 377         if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
 378             count < 384 || in_interrupt() || oops_in_progress )
 379                 goto out_copy;
 380
 381         xtra = count & 3;
 382         if (xtra) {
 383                 count -= xtra;
 384                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 385         }
 386
 387         dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
 388         dma_src = c->phys_base + bram_offset;
 389
 390         if (dma_mapping_error(dev, dma_dst)) {
 391                 dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
 392                 goto out_copy;
 393         }
 394
 395         err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 396         dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
 397         if (!err)
 398                 return 0;
 399
 400         dev_err(dev, "timeout waiting for DMA\n");
 401
 402 out_copy:
 403         memcpy(buf, this->base + bram_offset, count);
 404         return 0;
 405 }
 406
 407 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 408                                          const unsigned char *buffer,
 409                                          int offset, size_t count)
 410 {
 411         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 412         struct onenand_chip *this = mtd->priv;
 413         struct device *dev = &c->pdev->dev;
 414         void *buf = (void *)buffer;
 415         dma_addr_t dma_src, dma_dst;
 416         int bram_offset, err;
 417
 418         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 419         /*
 420          * If the buffer address is not DMA-able, len is not long enough to make
 421          * DMA transfers profitable or panic_write() may be in an interrupt
 422          * context fallback to PIO mode.
 423          */
 424         if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
 425             count < 384 || in_interrupt() || oops_in_progress )
 426                 goto out_copy;
 427
 428         dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
 429         dma_dst = c->phys_base + bram_offset;
 430         if (dma_mapping_error(dev, dma_src)) {
 431                 dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
 432                 goto out_copy;
 433         }
 434
 435         err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 436         dma_unmap_page(dev, dma_src, count, DMA_TO_DEVICE);
 437         if (!err)
 438                 return 0;
 439
 440         dev_err(dev, "timeout waiting for DMA\n");
 441
 442 out_copy:
 443         memcpy(this->base + bram_offset, buf, count);
 444         return 0;
 445 }
 446
 447 static void omap2_onenand_shutdown(struct platform_device *pdev)
 448 {
 449         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 450
 451         /* With certain content in the buffer RAM, the OMAP boot ROM code
 452          * can recognize the flash chip incorrectly. Zero it out before
 453          * soft reset.
 454          */
 455         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 456 }
 457
 458 static int omap2_onenand_probe(struct platform_device *pdev)
 459 {
 460         u32 val;
 461         dma_cap_mask_t mask;
 462         int freq, latency, r;
 463         struct resource *res;
 464         struct omap2_onenand *c;
 465         struct gpmc_onenand_info info;
 466         struct device *dev = &pdev->dev;
 467         struct device_node *np = dev->of_node;
 468
 469         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 470         if (!res) {
 471                 dev_err(dev, "error getting memory resource\n");
 472                 return -EINVAL;
 473         }
 474
 475         r = of_property_read_u32(np, "reg", &val);
 476         if (r) {
 477                 dev_err(dev, "reg not found in DT\n");
 478                 return r;
 479         }
 480
 481         c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
 482         if (!c)
 483                 return -ENOMEM;
 484
 485         init_completion(&c->irq_done);
 486         init_completion(&c->dma_done);
 487         c->gpmc_cs = val;
 488         c->phys_base = res->start;
 489
 490         c->onenand.base = devm_ioremap_resource(dev, res);
 491         if (IS_ERR(c->onenand.base))
 492                 return PTR_ERR(c->onenand.base);
 493
 494         c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
 495         if (IS_ERR(c->int_gpiod)) {
 496                 r = PTR_ERR(c->int_gpiod);
 497                 /* Just try again if this happens */
 498                 if (r != -EPROBE_DEFER)
 499                         dev_err(dev, "error getting gpio: %d\n", r);
 500                 return r;
 501         }
 502
 503         if (c->int_gpiod) {
 504                 r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
 505                                      omap2_onenand_interrupt,
 506                                      IRQF_TRIGGER_RISING, "onenand", c);
 507                 if (r)
 508                         return r;
 509
 510                 c->onenand.wait = omap2_onenand_wait;
 511         }
 512
 513         dma_cap_zero(mask);
 514         dma_cap_set(DMA_MEMCPY, mask);
 515
 516         c->dma_chan = dma_request_channel(mask, NULL, NULL);
 517         if (c->dma_chan) {
 518                 c->onenand.read_bufferram = omap2_onenand_read_bufferram;
 519                 c->onenand.write_bufferram = omap2_onenand_write_bufferram;
 520         }
 521
 522         c->pdev = pdev;
 523         c->mtd.priv = &c->onenand;
 524         c->mtd.dev.parent = dev;
 525         mtd_set_of_node(&c->mtd, dev->of_node);
 526
 527         dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
 528                  c->gpmc_cs, c->phys_base, c->onenand.base,
 529                  c->dma_chan ? "DMA" : "PIO");
 530
 531         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 532                 goto err_release_dma;
 533
 534         freq = omap2_onenand_get_freq(c->onenand.version_id);
 535         if (freq > 0) {
 536                 switch (freq) {
 537                 case 104:
 538                         latency = 7;
 539                         break;
 540                 case 83:
 541                         latency = 6;
 542                         break;
 543                 case 66:
 544                         latency = 5;
 545                         break;
 546                 case 56:
 547                         latency = 4;
 548                         break;
 549                 default:        /* 40 MHz or lower */
 550                         latency = 3;
 551                         break;
 552                 }
 553
 554                 r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
 555                                                   freq, latency, &info);
 556                 if (r)
 557                         goto err_release_onenand;
 558
 559                 r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
 560                                           latency, info.burst_len);
 561                 if (r)
 562                         goto err_release_onenand;
 563
 564                 if (info.sync_read || info.sync_write)
 565                         dev_info(dev, "optimized timings for %d MHz\n", freq);
 566         }
 567
 568         r = mtd_device_register(&c->mtd, NULL, 0);
 569         if (r)
 570                 goto err_release_onenand;
 571
 572         platform_set_drvdata(pdev, c);
 573
 574         return 0;
 575
 576 err_release_onenand:
 577         onenand_release(&c->mtd);
 578 err_release_dma:
 579         if (c->dma_chan)
 580                 dma_release_channel(c->dma_chan);
 581
 582         return r;
 583 }
 584
 585 static int omap2_onenand_remove(struct platform_device *pdev)
 586 {
 587         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 588
 589         onenand_release(&c->mtd);
 590         if (c->dma_chan)
 591                 dma_release_channel(c->dma_chan);
 592         omap2_onenand_shutdown(pdev);
 593
 594         return 0;
 595 }
 596
 597 static const struct of_device_id omap2_onenand_id_table[] = {
 598         { .compatible = "ti,omap2-onenand", },
 599         {},
 600 };
 601 MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
 602
 603 static struct platform_driver omap2_onenand_driver = {
 604         .probe          = omap2_onenand_probe,
 605         .remove         = omap2_onenand_remove,
 606         .shutdown       = omap2_onenand_shutdown,
 607         .driver         = {
 608                 .name   = DRIVER_NAME,
 609                 .of_match_table = omap2_onenand_id_table,
 610         },
 611 };
 612
 613 module_platform_driver(omap2_onenand_driver);
 614
 615 MODULE_ALIAS("platform:" DRIVER_NAME);
 616 MODULE_LICENSE("GPL");
 617 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 618 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");