drivers/thunderbolt/tb_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Thunderbolt driver - Port/Switch config area registers
   4  *
   5  * Every thunderbolt device consists (logically) of a switch with multiple
   6  * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
   7  * COUNTERS) which are used to configure the device.
   8  *
   9  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  10  * Copyright (C) 2018, Intel Corporation
  11  */
  12
  13 #ifndef _TB_REGS
  14 #define _TB_REGS
  15
  16 #include <linux/types.h>
  17
  18
  19 #define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */
  20
  21
  22 /*
  23  * TODO: should be 63? But we do not know how to receive frames larger than 256
  24  * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
  25  */
  26 #define TB_MAX_CONFIG_RW_LENGTH 60
  27
  28 enum tb_switch_cap {
  29         TB_SWITCH_CAP_VSE               = 0x05,
  30 };
  31
  32 enum tb_switch_vse_cap {
  33         TB_VSE_CAP_PLUG_EVENTS          = 0x01, /* also EEPROM */
  34         TB_VSE_CAP_TIME2                = 0x03,
  35         TB_VSE_CAP_IECS                 = 0x04,
  36         TB_VSE_CAP_LINK_CONTROLLER      = 0x06, /* also IECS */
  37 };
  38
  39 enum tb_port_cap {
  40         TB_PORT_CAP_PHY                 = 0x01,
  41         TB_PORT_CAP_TIME1               = 0x03,
  42         TB_PORT_CAP_ADAP                = 0x04,
  43         TB_PORT_CAP_VSE                 = 0x05,
  44 };
  45
  46 enum tb_port_state {
  47         TB_PORT_DISABLED        = 0, /* tb_cap_phy.disable == 1 */
  48         TB_PORT_CONNECTING      = 1, /* retry */
  49         TB_PORT_UP              = 2,
  50         TB_PORT_UNPLUGGED       = 7,
  51 };
  52
  53 /* capability headers */
  54
  55 struct tb_cap_basic {
  56         u8 next;
  57         /* enum tb_cap cap:8; prevent "narrower than values of its type" */
  58         u8 cap; /* if cap == 0x05 then we have a extended capability */
  59 } __packed;
  60
  61 /**
  62  * struct tb_cap_extended_short - Switch extended short capability
  63  * @next: Pointer to the next capability. If @next and @length are zero
  64  *        then we have a long cap.
  65  * @cap: Base capability ID (see &enum tb_switch_cap)
  66  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  67  * @length: Length of this capability
  68  */
  69 struct tb_cap_extended_short {
  70         u8 next;
  71         u8 cap;
  72         u8 vsec_id;
  73         u8 length;
  74 } __packed;
  75
  76 /**
  77  * struct tb_cap_extended_long - Switch extended long capability
  78  * @zero1: This field should be zero
  79  * @cap: Base capability ID (see &enum tb_switch_cap)
  80  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  81  * @zero2: This field should be zero
  82  * @next: Pointer to the next capability
  83  * @length: Length of this capability
  84  */
  85 struct tb_cap_extended_long {
  86         u8 zero1;
  87         u8 cap;
  88         u8 vsec_id;
  89         u8 zero2;
  90         u16 next;
  91         u16 length;
  92 } __packed;
  93
  94 /* capabilities */
  95
  96 struct tb_cap_link_controller {
  97         struct tb_cap_extended_long cap_header;
  98         u32 count:4; /* number of link controllers */
  99         u32 unknown1:4;
 100         u32 base_offset:8; /*
 101                             * offset (into this capability) of the configuration
 102                             * area of the first link controller
 103                             */
 104         u32 length:12; /* link controller configuration area length */
 105         u32 unknown2:4; /* TODO check that length is correct */
 106 } __packed;
 107
 108 struct tb_cap_phy {
 109         struct tb_cap_basic cap_header;
 110         u32 unknown1:16;
 111         u32 unknown2:14;
 112         bool disable:1;
 113         u32 unknown3:11;
 114         enum tb_port_state state:4;
 115         u32 unknown4:2;
 116 } __packed;
 117
 118 struct tb_eeprom_ctl {
 119         bool clock:1; /* send pulse to transfer one bit */
 120         bool access_low:1; /* set to 0 before access */
 121         bool data_out:1; /* to eeprom */
 122         bool data_in:1; /* from eeprom */
 123         bool access_high:1; /* set to 1 before access */
 124         bool not_present:1; /* should be 0 */
 125         bool unknown1:1;
 126         bool present:1; /* should be 1 */
 127         u32 unknown2:24;
 128 } __packed;
 129
 130 struct tb_cap_plug_events {
 131         struct tb_cap_extended_short cap_header;
 132         u32 __unknown1:2;
 133         u32 plug_events:5;
 134         u32 __unknown2:25;
 135         u32 __unknown3;
 136         u32 __unknown4;
 137         struct tb_eeprom_ctl eeprom_ctl;
 138         u32 __unknown5[7];
 139         u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
 140 } __packed;
 141
 142 /* device headers */
 143
 144 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
 145 struct tb_regs_switch_header {
 146         /* DWORD 0 */
 147         u16 vendor_id;
 148         u16 device_id;
 149         /* DWORD 1 */
 150         u32 first_cap_offset:8;
 151         u32 upstream_port_number:6;
 152         u32 max_port_number:6;
 153         u32 depth:3;
 154         u32 __unknown1:1;
 155         u32 revision:8;
 156         /* DWORD 2 */
 157         u32 route_lo;
 158         /* DWORD 3 */
 159         u32 route_hi:31;
 160         bool enabled:1;
 161         /* DWORD 4 */
 162         u32 plug_events_delay:8; /*
 163                                   * RW, pause between plug events in
 164                                   * milliseconds. Writing 0x00 is interpreted
 165                                   * as 255ms.
 166                                   */
 167         u32 __unknown4:16;
 168         u32 thunderbolt_version:8;
 169 } __packed;
 170
 171 enum tb_port_type {
 172         TB_TYPE_INACTIVE        = 0x000000,
 173         TB_TYPE_PORT            = 0x000001,
 174         TB_TYPE_NHI             = 0x000002,
 175         /* TB_TYPE_ETHERNET     = 0x020000, lower order bits are not known */
 176         /* TB_TYPE_SATA         = 0x080000, lower order bits are not known */
 177         TB_TYPE_DP_HDMI_IN      = 0x0e0101,
 178         TB_TYPE_DP_HDMI_OUT     = 0x0e0102,
 179         TB_TYPE_PCIE_DOWN       = 0x100101,
 180         TB_TYPE_PCIE_UP         = 0x100102,
 181         /* TB_TYPE_USB          = 0x200000, lower order bits are not known */
 182 };
 183
 184 /* Present on every port in TB_CF_PORT at address zero. */
 185 struct tb_regs_port_header {
 186         /* DWORD 0 */
 187         u16 vendor_id;
 188         u16 device_id;
 189         /* DWORD 1 */
 190         u32 first_cap_offset:8;
 191         u32 max_counters:11;
 192         u32 __unknown1:5;
 193         u32 revision:8;
 194         /* DWORD 2 */
 195         enum tb_port_type type:24;
 196         u32 thunderbolt_version:8;
 197         /* DWORD 3 */
 198         u32 __unknown2:20;
 199         u32 port_number:6;
 200         u32 __unknown3:6;
 201         /* DWORD 4 */
 202         u32 nfc_credits;
 203         /* DWORD 5 */
 204         u32 max_in_hop_id:11;
 205         u32 max_out_hop_id:11;
 206         u32 __unknown4:10;
 207         /* DWORD 6 */
 208         u32 __unknown5;
 209         /* DWORD 7 */
 210         u32 __unknown6;
 211
 212 } __packed;
 213
 214 /* Basic adapter configuration registers */
 215 #define ADP_CS_4                                0x04
 216 #define ADP_CS_4_NFC_BUFFERS_MASK               GENMASK(9, 0)
 217 #define ADP_CS_4_TOTAL_BUFFERS_MASK             GENMASK(29, 20)
 218 #define ADP_CS_4_TOTAL_BUFFERS_SHIFT            20
 219 #define ADP_CS_5                                0x05
 220 #define ADP_CS_5_LCA_MASK                       GENMASK(28, 22)
 221 #define ADP_CS_5_LCA_SHIFT                      22
 222
 223 /* Lane adapter registers */
 224 #define LANE_ADP_CS_0                           0x00
 225 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK      GENMASK(25, 20)
 226 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT     20
 227 #define LANE_ADP_CS_1                           0x01
 228 #define LANE_ADP_CS_1_TARGET_WIDTH_MASK         GENMASK(9, 4)
 229 #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT        4
 230 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE       0x1
 231 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL         0x3
 232 #define LANE_ADP_CS_1_LB                        BIT(15)
 233 #define LANE_ADP_CS_1_CURRENT_SPEED_MASK        GENMASK(19, 16)
 234 #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT       16
 235 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2        0x8
 236 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3        0x4
 237 #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK        GENMASK(25, 20)
 238 #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT       20
 239
 240 /* Display Port adapter registers */
 241 #define ADP_DP_CS_0                             0x00
 242 #define ADP_DP_CS_0_VIDEO_HOPID_MASK            GENMASK(26, 16)
 243 #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT           16
 244 #define ADP_DP_CS_0_AE                          BIT(30)
 245 #define ADP_DP_CS_0_VE                          BIT(31)
 246 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK           GENMASK(10, 0)
 247 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK           GENMASK(21, 11)
 248 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT          11
 249 #define ADP_DP_CS_2                             0x02
 250 #define ADP_DP_CS_2_HDP                         BIT(6)
 251 #define ADP_DP_CS_3                             0x03
 252 #define ADP_DP_CS_3_HDPC                        BIT(9)
 253 #define DP_LOCAL_CAP                            0x04
 254 #define DP_REMOTE_CAP                           0x05
 255 #define DP_STATUS_CTRL                          0x06
 256 #define DP_STATUS_CTRL_CMHS                     BIT(25)
 257 #define DP_STATUS_CTRL_UF                       BIT(26)
 258 #define DP_COMMON_CAP                           0x07
 259 /*
 260  * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
 261  * with exception of DPRX done.
 262  */
 263 #define DP_COMMON_CAP_RATE_MASK                 GENMASK(11, 8)
 264 #define DP_COMMON_CAP_RATE_SHIFT                8
 265 #define DP_COMMON_CAP_RATE_RBR                  0x0
 266 #define DP_COMMON_CAP_RATE_HBR                  0x1
 267 #define DP_COMMON_CAP_RATE_HBR2                 0x2
 268 #define DP_COMMON_CAP_RATE_HBR3                 0x3
 269 #define DP_COMMON_CAP_LANES_MASK                GENMASK(14, 12)
 270 #define DP_COMMON_CAP_LANES_SHIFT               12
 271 #define DP_COMMON_CAP_1_LANE                    0x0
 272 #define DP_COMMON_CAP_2_LANES                   0x1
 273 #define DP_COMMON_CAP_4_LANES                   0x2
 274 #define DP_COMMON_CAP_DPRX_DONE                 BIT(31)
 275
 276 /* PCIe adapter registers */
 277 #define ADP_PCIE_CS_0                           0x00
 278 #define ADP_PCIE_CS_0_PE                        BIT(31)
 279
 280 /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
 281 struct tb_regs_hop {
 282         /* DWORD 0 */
 283         u32 next_hop:11; /*
 284                           * hop to take after sending the packet through
 285                           * out_port (on the incoming port of the next switch)
 286                           */
 287         u32 out_port:6; /* next port of the path (on the same switch) */
 288         u32 initial_credits:8;
 289         u32 unknown1:6; /* set to zero */
 290         bool enable:1;
 291
 292         /* DWORD 1 */
 293         u32 weight:4;
 294         u32 unknown2:4; /* set to zero */
 295         u32 priority:3;
 296         bool drop_packages:1;
 297         u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
 298         bool counter_enable:1;
 299         bool ingress_fc:1;
 300         bool egress_fc:1;
 301         bool ingress_shared_buffer:1;
 302         bool egress_shared_buffer:1;
 303         bool pending:1;
 304         u32 unknown3:3; /* set to zero */
 305 } __packed;
 306
 307 /* Common link controller registers */
 308 #define TB_LC_DESC                      0x02
 309 #define TB_LC_DESC_NLC_MASK             GENMASK(3, 0)
 310 #define TB_LC_DESC_SIZE_SHIFT           8
 311 #define TB_LC_DESC_SIZE_MASK            GENMASK(15, 8)
 312 #define TB_LC_DESC_PORT_SIZE_SHIFT      16
 313 #define TB_LC_DESC_PORT_SIZE_MASK       GENMASK(27, 16)
 314 #define TB_LC_FUSE                      0x03
 315 #define TB_LC_SNK_ALLOCATION            0x10
 316 #define TB_LC_SNK_ALLOCATION_SNK0_MASK  GENMASK(3, 0)
 317 #define TB_LC_SNK_ALLOCATION_SNK0_CM    0x1
 318 #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
 319 #define TB_LC_SNK_ALLOCATION_SNK1_MASK  GENMASK(7, 4)
 320 #define TB_LC_SNK_ALLOCATION_SNK1_CM    0x1
 321
 322 /* Link controller registers */
 323 #define TB_LC_PORT_ATTR                 0x8d
 324 #define TB_LC_PORT_ATTR_BE              BIT(12)
 325
 326 #define TB_LC_SX_CTRL                   0x96
 327 #define TB_LC_SX_CTRL_L1C               BIT(16)
 328 #define TB_LC_SX_CTRL_L2C               BIT(20)
 329 #define TB_LC_SX_CTRL_UPSTREAM          BIT(30)
 330 #define TB_LC_SX_CTRL_SLP               BIT(31)
 331
 332 #endif