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usb: xhci: Fix build warning seen with CONFIG_PM=n
[linux/fpc-iii.git] / drivers / usb / host / xhci-tegra.c
blobbf9065438320c2efc17745fb17c1f43bb8a88bd4
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (C) 2014 NVIDIA Corporation
6 * Copyright (C) 2014 Google, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/tegra/xusb.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <soc/tegra/pmc.h>
27
28 #include "xhci.h"
29
30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
32
33 /* FPCI CFG registers */
34 #define XUSB_CFG_1 0x004
35 #define XUSB_IO_SPACE_EN BIT(0)
36 #define XUSB_MEM_SPACE_EN BIT(1)
37 #define XUSB_BUS_MASTER_EN BIT(2)
38 #define XUSB_CFG_4 0x010
39 #define XUSB_BASE_ADDR_SHIFT 15
40 #define XUSB_BASE_ADDR_MASK 0x1ffff
41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
42 #define XUSB_CFG_CSB_BASE_ADDR 0x800
43
44 /* FPCI mailbox registers */
45 /* XUSB_CFG_ARU_MBOX_CMD */
46 #define MBOX_DEST_FALC BIT(27)
47 #define MBOX_DEST_PME BIT(28)
48 #define MBOX_DEST_SMI BIT(29)
49 #define MBOX_DEST_XHCI BIT(30)
50 #define MBOX_INT_EN BIT(31)
51 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
52 #define CMD_DATA_SHIFT 0
53 #define CMD_DATA_MASK 0xffffff
54 #define CMD_TYPE_SHIFT 24
55 #define CMD_TYPE_MASK 0xff
56 /* XUSB_CFG_ARU_MBOX_OWNER */
57 #define MBOX_OWNER_NONE 0
58 #define MBOX_OWNER_FW 1
59 #define MBOX_OWNER_SW 2
60 #define XUSB_CFG_ARU_SMI_INTR 0x428
61 #define MBOX_SMI_INTR_FW_HANG BIT(1)
62 #define MBOX_SMI_INTR_EN BIT(3)
63
64 /* IPFS registers */
65 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
66 #define IPFS_EN_FPCI BIT(0)
67 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
68 #define IPFS_IP_INT_MASK BIT(16)
69 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
70
71 #define CSB_PAGE_SELECT_MASK 0x7fffff
72 #define CSB_PAGE_SELECT_SHIFT 9
73 #define CSB_PAGE_OFFSET_MASK 0x1ff
74 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
75 CSB_PAGE_SELECT_MASK)
76 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
77
78 /* Falcon CSB registers */
79 #define XUSB_FALC_CPUCTL 0x100
80 #define CPUCTL_STARTCPU BIT(1)
81 #define CPUCTL_STATE_HALTED BIT(4)
82 #define CPUCTL_STATE_STOPPED BIT(5)
83 #define XUSB_FALC_BOOTVEC 0x104
84 #define XUSB_FALC_DMACTL 0x10c
85 #define XUSB_FALC_IMFILLRNG1 0x154
86 #define IMFILLRNG1_TAG_MASK 0xffff
87 #define IMFILLRNG1_TAG_LO_SHIFT 0
88 #define IMFILLRNG1_TAG_HI_SHIFT 16
89 #define XUSB_FALC_IMFILLCTL 0x158
90
91 /* MP CSB registers */
92 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
93 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
94 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
95 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
96 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
97 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
98 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
99 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
100 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
101 #define L2IMEMOP_ACTION_SHIFT 24
102 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
103 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
104 #define XUSB_CSB_MP_APMAP 0x10181c
105 #define APMAP_BOOTPATH BIT(31)
106
107 #define IMEM_BLOCK_SIZE 256
108
109 struct tegra_xusb_fw_header {
110 __le32 boot_loadaddr_in_imem;
111 __le32 boot_codedfi_offset;
112 __le32 boot_codetag;
113 __le32 boot_codesize;
114 __le32 phys_memaddr;
115 __le16 reqphys_memsize;
116 __le16 alloc_phys_memsize;
117 __le32 rodata_img_offset;
118 __le32 rodata_section_start;
119 __le32 rodata_section_end;
120 __le32 main_fnaddr;
121 __le32 fwimg_cksum;
122 __le32 fwimg_created_time;
123 __le32 imem_resident_start;
124 __le32 imem_resident_end;
125 __le32 idirect_start;
126 __le32 idirect_end;
127 __le32 l2_imem_start;
128 __le32 l2_imem_end;
129 __le32 version_id;
130 u8 init_ddirect;
131 u8 reserved[3];
132 __le32 phys_addr_log_buffer;
133 __le32 total_log_entries;
134 __le32 dequeue_ptr;
135 __le32 dummy_var[2];
136 __le32 fwimg_len;
137 u8 magic[8];
138 __le32 ss_low_power_entry_timeout;
139 u8 num_hsic_port;
140 u8 padding[139]; /* Pad to 256 bytes */
141 };
142
143 struct tegra_xusb_phy_type {
144 const char *name;
145 unsigned int num;
146 };
147
148 struct tega_xusb_mbox_regs {
149 u16 cmd;
150 u16 data_in;
151 u16 data_out;
152 u16 owner;
153 };
154
155 struct tegra_xusb_soc {
156 const char *firmware;
157 const char * const *supply_names;
158 unsigned int num_supplies;
159 const struct tegra_xusb_phy_type *phy_types;
160 unsigned int num_types;
161
162 struct {
163 struct {
164 unsigned int offset;
165 unsigned int count;
166 } usb2, ulpi, hsic, usb3;
167 } ports;
168
169 struct tega_xusb_mbox_regs mbox;
170
171 bool scale_ss_clock;
172 bool has_ipfs;
173 };
174
175 struct tegra_xusb {
176 struct device *dev;
177 void __iomem *regs;
178 struct usb_hcd *hcd;
179
180 struct mutex lock;
181
182 int xhci_irq;
183 int mbox_irq;
184
185 void __iomem *ipfs_base;
186 void __iomem *fpci_base;
187
188 const struct tegra_xusb_soc *soc;
189
190 struct regulator_bulk_data *supplies;
191
192 struct tegra_xusb_padctl *padctl;
193
194 struct clk *host_clk;
195 struct clk *falcon_clk;
196 struct clk *ss_clk;
197 struct clk *ss_src_clk;
198 struct clk *hs_src_clk;
199 struct clk *fs_src_clk;
200 struct clk *pll_u_480m;
201 struct clk *clk_m;
202 struct clk *pll_e;
203
204 struct reset_control *host_rst;
205 struct reset_control *ss_rst;
206
207 struct device *genpd_dev_host;
208 struct device *genpd_dev_ss;
209 struct device_link *genpd_dl_host;
210 struct device_link *genpd_dl_ss;
211
212 struct phy **phys;
213 unsigned int num_phys;
214
215 /* Firmware loading related */
216 struct {
217 size_t size;
218 void *virt;
219 dma_addr_t phys;
220 } fw;
221 };
222
223 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
224
225 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
226 {
227 return readl(tegra->fpci_base + offset);
228 }
229
230 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
231 unsigned int offset)
232 {
233 writel(value, tegra->fpci_base + offset);
234 }
235
236 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
237 {
238 return readl(tegra->ipfs_base + offset);
239 }
240
241 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
242 unsigned int offset)
243 {
244 writel(value, tegra->ipfs_base + offset);
245 }
246
247 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
248 {
249 u32 page = CSB_PAGE_SELECT(offset);
250 u32 ofs = CSB_PAGE_OFFSET(offset);
251
252 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
253
254 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
255 }
256
257 static void csb_writel(struct tegra_xusb *tegra, u32 value,
258 unsigned int offset)
259 {
260 u32 page = CSB_PAGE_SELECT(offset);
261 u32 ofs = CSB_PAGE_OFFSET(offset);
262
263 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
264 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
265 }
266
267 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
268 unsigned long rate)
269 {
270 unsigned long new_parent_rate, old_parent_rate;
271 struct clk *clk = tegra->ss_src_clk;
272 unsigned int div;
273 int err;
274
275 if (clk_get_rate(clk) == rate)
276 return 0;
277
278 switch (rate) {
279 case TEGRA_XHCI_SS_HIGH_SPEED:
280 /*
281 * Reparent to PLLU_480M. Set divider first to avoid
282 * overclocking.
283 */
284 old_parent_rate = clk_get_rate(clk_get_parent(clk));
285 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
286 div = new_parent_rate / rate;
287
288 err = clk_set_rate(clk, old_parent_rate / div);
289 if (err)
290 return err;
291
292 err = clk_set_parent(clk, tegra->pll_u_480m);
293 if (err)
294 return err;
295
296 /*
297 * The rate should already be correct, but set it again just
298 * to be sure.
299 */
300 err = clk_set_rate(clk, rate);
301 if (err)
302 return err;
303
304 break;
305
306 case TEGRA_XHCI_SS_LOW_SPEED:
307 /* Reparent to CLK_M */
308 err = clk_set_parent(clk, tegra->clk_m);
309 if (err)
310 return err;
311
312 err = clk_set_rate(clk, rate);
313 if (err)
314 return err;
315
316 break;
317
318 default:
319 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
320 return -EINVAL;
321 }
322
323 if (clk_get_rate(clk) != rate) {
324 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
325 return -EINVAL;
326 }
327
328 return 0;
329 }
330
331 static unsigned long extract_field(u32 value, unsigned int start,
332 unsigned int count)
333 {
334 return (value >> start) & ((1 << count) - 1);
335 }
336
337 /* Command requests from the firmware */
338 enum tegra_xusb_mbox_cmd {
339 MBOX_CMD_MSG_ENABLED = 1,
340 MBOX_CMD_INC_FALC_CLOCK,
341 MBOX_CMD_DEC_FALC_CLOCK,
342 MBOX_CMD_INC_SSPI_CLOCK,
343 MBOX_CMD_DEC_SSPI_CLOCK,
344 MBOX_CMD_SET_BW, /* no ACK/NAK required */
345 MBOX_CMD_SET_SS_PWR_GATING,
346 MBOX_CMD_SET_SS_PWR_UNGATING,
347 MBOX_CMD_SAVE_DFE_CTLE_CTX,
348 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
349 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
350 MBOX_CMD_START_HSIC_IDLE,
351 MBOX_CMD_STOP_HSIC_IDLE,
352 MBOX_CMD_DBC_WAKE_STACK, /* unused */
353 MBOX_CMD_HSIC_PRETEND_CONNECT,
354 MBOX_CMD_RESET_SSPI,
355 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
356 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
357
358 MBOX_CMD_MAX,
359
360 /* Response message to above commands */
361 MBOX_CMD_ACK = 128,
362 MBOX_CMD_NAK
363 };
364
365 struct tegra_xusb_mbox_msg {
366 u32 cmd;
367 u32 data;
368 };
369
370 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
371 {
372 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
373 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
374 }
375 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
376 u32 value)
377 {
378 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
379 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
380 }
381
382 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
383 {
384 switch (cmd) {
385 case MBOX_CMD_SET_BW:
386 case MBOX_CMD_ACK:
387 case MBOX_CMD_NAK:
388 return false;
389
390 default:
391 return true;
392 }
393 }
394
395 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
396 const struct tegra_xusb_mbox_msg *msg)
397 {
398 bool wait_for_idle = false;
399 u32 value;
400
401 /*
402 * Acquire the mailbox. The firmware still owns the mailbox for
403 * ACK/NAK messages.
404 */
405 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
406 value = fpci_readl(tegra, tegra->soc->mbox.owner);
407 if (value != MBOX_OWNER_NONE) {
408 dev_err(tegra->dev, "mailbox is busy\n");
409 return -EBUSY;
410 }
411
412 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
413
414 value = fpci_readl(tegra, tegra->soc->mbox.owner);
415 if (value != MBOX_OWNER_SW) {
416 dev_err(tegra->dev, "failed to acquire mailbox\n");
417 return -EBUSY;
418 }
419
420 wait_for_idle = true;
421 }
422
423 value = tegra_xusb_mbox_pack(msg);
424 fpci_writel(tegra, value, tegra->soc->mbox.data_in);
425
426 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
427 value |= MBOX_INT_EN | MBOX_DEST_FALC;
428 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
429
430 if (wait_for_idle) {
431 unsigned long timeout = jiffies + msecs_to_jiffies(250);
432
433 while (time_before(jiffies, timeout)) {
434 value = fpci_readl(tegra, tegra->soc->mbox.owner);
435 if (value == MBOX_OWNER_NONE)
436 break;
437
438 usleep_range(10, 20);
439 }
440
441 if (time_after(jiffies, timeout))
442 value = fpci_readl(tegra, tegra->soc->mbox.owner);
443
444 if (value != MBOX_OWNER_NONE)
445 return -ETIMEDOUT;
446 }
447
448 return 0;
449 }
450
451 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
452 {
453 struct tegra_xusb *tegra = data;
454 u32 value;
455
456 /* clear mailbox interrupts */
457 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
458 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
459
460 if (value & MBOX_SMI_INTR_FW_HANG)
461 dev_err(tegra->dev, "controller firmware hang\n");
462
463 return IRQ_WAKE_THREAD;
464 }
465
466 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
467 const struct tegra_xusb_mbox_msg *msg)
468 {
469 struct tegra_xusb_padctl *padctl = tegra->padctl;
470 const struct tegra_xusb_soc *soc = tegra->soc;
471 struct device *dev = tegra->dev;
472 struct tegra_xusb_mbox_msg rsp;
473 unsigned long mask;
474 unsigned int port;
475 bool idle, enable;
476 int err = 0;
477
478 memset(&rsp, 0, sizeof(rsp));
479
480 switch (msg->cmd) {
481 case MBOX_CMD_INC_FALC_CLOCK:
482 case MBOX_CMD_DEC_FALC_CLOCK:
483 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
484 if (rsp.data != msg->data)
485 rsp.cmd = MBOX_CMD_NAK;
486 else
487 rsp.cmd = MBOX_CMD_ACK;
488
489 break;
490
491 case MBOX_CMD_INC_SSPI_CLOCK:
492 case MBOX_CMD_DEC_SSPI_CLOCK:
493 if (tegra->soc->scale_ss_clock) {
494 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
495 if (err < 0)
496 rsp.cmd = MBOX_CMD_NAK;
497 else
498 rsp.cmd = MBOX_CMD_ACK;
499
500 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
501 } else {
502 rsp.cmd = MBOX_CMD_ACK;
503 rsp.data = msg->data;
504 }
505
506 break;
507
508 case MBOX_CMD_SET_BW:
509 /*
510 * TODO: Request bandwidth once EMC scaling is supported.
511 * Ignore for now since ACK/NAK is not required for SET_BW
512 * messages.
513 */
514 break;
515
516 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
517 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
518 if (err < 0) {
519 dev_err(dev, "failed to save context for USB3#%u: %d\n",
520 msg->data, err);
521 rsp.cmd = MBOX_CMD_NAK;
522 } else {
523 rsp.cmd = MBOX_CMD_ACK;
524 }
525
526 rsp.data = msg->data;
527 break;
528
529 case MBOX_CMD_START_HSIC_IDLE:
530 case MBOX_CMD_STOP_HSIC_IDLE:
531 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
532 idle = false;
533 else
534 idle = true;
535
536 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
537 soc->ports.hsic.count);
538
539 for_each_set_bit(port, &mask, 32) {
540 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
541 idle);
542 if (err < 0)
543 break;
544 }
545
546 if (err < 0) {
547 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
548 idle ? "idle" : "busy", err);
549 rsp.cmd = MBOX_CMD_NAK;
550 } else {
551 rsp.cmd = MBOX_CMD_ACK;
552 }
553
554 rsp.data = msg->data;
555 break;
556
557 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
558 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
559 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
560 enable = false;
561 else
562 enable = true;
563
564 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
565 soc->ports.usb3.count);
566
567 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
568 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
569 port,
570 enable);
571 if (err < 0)
572 break;
573 }
574
575 if (err < 0) {
576 dev_err(dev,
577 "failed to %s LFPS detection on USB3#%u: %d\n",
578 enable ? "enable" : "disable", port, err);
579 rsp.cmd = MBOX_CMD_NAK;
580 } else {
581 rsp.cmd = MBOX_CMD_ACK;
582 }
583
584 rsp.data = msg->data;
585 break;
586
587 default:
588 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
589 break;
590 }
591
592 if (rsp.cmd) {
593 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
594
595 err = tegra_xusb_mbox_send(tegra, &rsp);
596 if (err < 0)
597 dev_err(dev, "failed to send %s: %d\n", cmd, err);
598 }
599 }
600
601 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
602 {
603 struct tegra_xusb *tegra = data;
604 struct tegra_xusb_mbox_msg msg;
605 u32 value;
606
607 mutex_lock(&tegra->lock);
608
609 value = fpci_readl(tegra, tegra->soc->mbox.data_out);
610 tegra_xusb_mbox_unpack(&msg, value);
611
612 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
613 value &= ~MBOX_DEST_SMI;
614 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
615
616 /* clear mailbox owner if no ACK/NAK is required */
617 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
618 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
619
620 tegra_xusb_mbox_handle(tegra, &msg);
621
622 mutex_unlock(&tegra->lock);
623 return IRQ_HANDLED;
624 }
625
626 static void tegra_xusb_config(struct tegra_xusb *tegra,
627 struct resource *regs)
628 {
629 u32 value;
630
631 if (tegra->soc->has_ipfs) {
632 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
633 value |= IPFS_EN_FPCI;
634 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
635
636 usleep_range(10, 20);
637 }
638
639 /* Program BAR0 space */
640 value = fpci_readl(tegra, XUSB_CFG_4);
641 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
642 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
643 fpci_writel(tegra, value, XUSB_CFG_4);
644
645 usleep_range(100, 200);
646
647 /* Enable bus master */
648 value = fpci_readl(tegra, XUSB_CFG_1);
649 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
650 fpci_writel(tegra, value, XUSB_CFG_1);
651
652 if (tegra->soc->has_ipfs) {
653 /* Enable interrupt assertion */
654 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
655 value |= IPFS_IP_INT_MASK;
656 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
657
658 /* Set hysteresis */
659 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
660 }
661 }
662
663 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
664 {
665 int err;
666
667 err = clk_prepare_enable(tegra->pll_e);
668 if (err < 0)
669 return err;
670
671 err = clk_prepare_enable(tegra->host_clk);
672 if (err < 0)
673 goto disable_plle;
674
675 err = clk_prepare_enable(tegra->ss_clk);
676 if (err < 0)
677 goto disable_host;
678
679 err = clk_prepare_enable(tegra->falcon_clk);
680 if (err < 0)
681 goto disable_ss;
682
683 err = clk_prepare_enable(tegra->fs_src_clk);
684 if (err < 0)
685 goto disable_falc;
686
687 err = clk_prepare_enable(tegra->hs_src_clk);
688 if (err < 0)
689 goto disable_fs_src;
690
691 if (tegra->soc->scale_ss_clock) {
692 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
693 if (err < 0)
694 goto disable_hs_src;
695 }
696
697 return 0;
698
699 disable_hs_src:
700 clk_disable_unprepare(tegra->hs_src_clk);
701 disable_fs_src:
702 clk_disable_unprepare(tegra->fs_src_clk);
703 disable_falc:
704 clk_disable_unprepare(tegra->falcon_clk);
705 disable_ss:
706 clk_disable_unprepare(tegra->ss_clk);
707 disable_host:
708 clk_disable_unprepare(tegra->host_clk);
709 disable_plle:
710 clk_disable_unprepare(tegra->pll_e);
711 return err;
712 }
713
714 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
715 {
716 clk_disable_unprepare(tegra->pll_e);
717 clk_disable_unprepare(tegra->host_clk);
718 clk_disable_unprepare(tegra->ss_clk);
719 clk_disable_unprepare(tegra->falcon_clk);
720 clk_disable_unprepare(tegra->fs_src_clk);
721 clk_disable_unprepare(tegra->hs_src_clk);
722 }
723
724 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
725 {
726 unsigned int i;
727 int err;
728
729 for (i = 0; i < tegra->num_phys; i++) {
730 err = phy_init(tegra->phys[i]);
731 if (err)
732 goto disable_phy;
733
734 err = phy_power_on(tegra->phys[i]);
735 if (err) {
736 phy_exit(tegra->phys[i]);
737 goto disable_phy;
738 }
739 }
740
741 return 0;
742
743 disable_phy:
744 while (i--) {
745 phy_power_off(tegra->phys[i]);
746 phy_exit(tegra->phys[i]);
747 }
748
749 return err;
750 }
751
752 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
753 {
754 unsigned int i;
755
756 for (i = 0; i < tegra->num_phys; i++) {
757 phy_power_off(tegra->phys[i]);
758 phy_exit(tegra->phys[i]);
759 }
760 }
761
762 static int tegra_xusb_runtime_suspend(struct device *dev)
763 {
764 struct tegra_xusb *tegra = dev_get_drvdata(dev);
765
766 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
767 tegra_xusb_clk_disable(tegra);
768
769 return 0;
770 }
771
772 static int tegra_xusb_runtime_resume(struct device *dev)
773 {
774 struct tegra_xusb *tegra = dev_get_drvdata(dev);
775 int err;
776
777 err = tegra_xusb_clk_enable(tegra);
778 if (err) {
779 dev_err(dev, "failed to enable clocks: %d\n", err);
780 return err;
781 }
782
783 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
784 if (err) {
785 dev_err(dev, "failed to enable regulators: %d\n", err);
786 goto disable_clk;
787 }
788
789 return 0;
790
791 disable_clk:
792 tegra_xusb_clk_disable(tegra);
793 return err;
794 }
795
796 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
797 {
798 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
799 struct tegra_xusb_fw_header *header;
800 struct device *dev = tegra->dev;
801 const struct firmware *fw;
802 unsigned long timeout;
803 time64_t timestamp;
804 struct tm time;
805 u64 address;
806 u32 value;
807 int err;
808
809 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
810 if (err < 0) {
811 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
812 return err;
813 }
814
815 /* Load Falcon controller with its firmware. */
816 header = (struct tegra_xusb_fw_header *)fw->data;
817 tegra->fw.size = le32_to_cpu(header->fwimg_len);
818
819 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
820 &tegra->fw.phys, GFP_KERNEL);
821 if (!tegra->fw.virt) {
822 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
823 release_firmware(fw);
824 return -ENOMEM;
825 }
826
827 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
828 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
829 release_firmware(fw);
830
831 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
832 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
833 csb_readl(tegra, XUSB_FALC_CPUCTL));
834 return 0;
835 }
836
837 /* Program the size of DFI into ILOAD_ATTR. */
838 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
839
840 /*
841 * Boot code of the firmware reads the ILOAD_BASE registers
842 * to get to the start of the DFI in system memory.
843 */
844 address = tegra->fw.phys + sizeof(*header);
845 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
846 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
847
848 /* Set BOOTPATH to 1 in APMAP. */
849 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
850
851 /* Invalidate L2IMEM. */
852 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
853
854 /*
855 * Initiate fetch of bootcode from system memory into L2IMEM.
856 * Program bootcode location and size in system memory.
857 */
858 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
859 IMEM_BLOCK_SIZE);
860 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
861 IMEM_BLOCK_SIZE);
862 code_blocks = code_tag_blocks + code_size_blocks;
863
864 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
865 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
866 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
867 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
868 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
869
870 /* Trigger L2IMEM load operation. */
871 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
872 XUSB_CSB_MP_L2IMEMOP_TRIG);
873
874 /* Setup Falcon auto-fill. */
875 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
876
877 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
878 IMFILLRNG1_TAG_LO_SHIFT) |
879 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
880 IMFILLRNG1_TAG_HI_SHIFT);
881 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
882
883 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
884
885 msleep(50);
886
887 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
888 XUSB_FALC_BOOTVEC);
889
890 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
891 timeout = jiffies + msecs_to_jiffies(5);
892
893 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
894
895 while (time_before(jiffies, timeout)) {
896 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
897 break;
898
899 usleep_range(100, 200);
900 }
901
902 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
903 dev_err(dev, "Falcon failed to start, state: %#x\n",
904 csb_readl(tegra, XUSB_FALC_CPUCTL));
905 return -EIO;
906 }
907
908 timestamp = le32_to_cpu(header->fwimg_created_time);
909 time64_to_tm(timestamp, 0, &time);
910
911 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
912 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
913 time.tm_hour, time.tm_min, time.tm_sec);
914
915 return 0;
916 }
917
918 static void tegra_xusb_powerdomain_remove(struct device *dev,
919 struct tegra_xusb *tegra)
920 {
921 if (tegra->genpd_dl_ss)
922 device_link_del(tegra->genpd_dl_ss);
923 if (tegra->genpd_dl_host)
924 device_link_del(tegra->genpd_dl_host);
925 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
926 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
927 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
928 dev_pm_domain_detach(tegra->genpd_dev_host, true);
929 }
930
931 static int tegra_xusb_powerdomain_init(struct device *dev,
932 struct tegra_xusb *tegra)
933 {
934 int err;
935
936 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
937 if (IS_ERR(tegra->genpd_dev_host)) {
938 err = PTR_ERR(tegra->genpd_dev_host);
939 dev_err(dev, "failed to get host pm-domain: %d\n", err);
940 return err;
941 }
942
943 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
944 if (IS_ERR(tegra->genpd_dev_ss)) {
945 err = PTR_ERR(tegra->genpd_dev_ss);
946 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
947 return err;
948 }
949
950 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
951 DL_FLAG_PM_RUNTIME |
952 DL_FLAG_STATELESS);
953 if (!tegra->genpd_dl_host) {
954 dev_err(dev, "adding host device link failed!\n");
955 return -ENODEV;
956 }
957
958 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
959 DL_FLAG_PM_RUNTIME |
960 DL_FLAG_STATELESS);
961 if (!tegra->genpd_dl_ss) {
962 dev_err(dev, "adding superspeed device link failed!\n");
963 return -ENODEV;
964 }
965
966 return 0;
967 }
968
969 static int tegra_xusb_probe(struct platform_device *pdev)
970 {
971 struct tegra_xusb_mbox_msg msg;
972 struct resource *regs;
973 struct tegra_xusb *tegra;
974 struct xhci_hcd *xhci;
975 unsigned int i, j, k;
976 struct phy *phy;
977 int err;
978
979 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
980
981 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
982 if (!tegra)
983 return -ENOMEM;
984
985 tegra->soc = of_device_get_match_data(&pdev->dev);
986 mutex_init(&tegra->lock);
987 tegra->dev = &pdev->dev;
988
989 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
991 if (IS_ERR(tegra->regs))
992 return PTR_ERR(tegra->regs);
993
994 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
995 if (IS_ERR(tegra->fpci_base))
996 return PTR_ERR(tegra->fpci_base);
997
998 if (tegra->soc->has_ipfs) {
999 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1000 if (IS_ERR(tegra->ipfs_base))
1001 return PTR_ERR(tegra->ipfs_base);
1002 }
1003
1004 tegra->xhci_irq = platform_get_irq(pdev, 0);
1005 if (tegra->xhci_irq < 0)
1006 return tegra->xhci_irq;
1007
1008 tegra->mbox_irq = platform_get_irq(pdev, 1);
1009 if (tegra->mbox_irq < 0)
1010 return tegra->mbox_irq;
1011
1012 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1013 if (IS_ERR(tegra->padctl))
1014 return PTR_ERR(tegra->padctl);
1015
1016 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1017 if (IS_ERR(tegra->host_clk)) {
1018 err = PTR_ERR(tegra->host_clk);
1019 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1020 goto put_padctl;
1021 }
1022
1023 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1024 if (IS_ERR(tegra->falcon_clk)) {
1025 err = PTR_ERR(tegra->falcon_clk);
1026 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1027 goto put_padctl;
1028 }
1029
1030 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1031 if (IS_ERR(tegra->ss_clk)) {
1032 err = PTR_ERR(tegra->ss_clk);
1033 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1034 goto put_padctl;
1035 }
1036
1037 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1038 if (IS_ERR(tegra->ss_src_clk)) {
1039 err = PTR_ERR(tegra->ss_src_clk);
1040 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1041 goto put_padctl;
1042 }
1043
1044 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1045 if (IS_ERR(tegra->hs_src_clk)) {
1046 err = PTR_ERR(tegra->hs_src_clk);
1047 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1048 goto put_padctl;
1049 }
1050
1051 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1052 if (IS_ERR(tegra->fs_src_clk)) {
1053 err = PTR_ERR(tegra->fs_src_clk);
1054 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1055 goto put_padctl;
1056 }
1057
1058 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1059 if (IS_ERR(tegra->pll_u_480m)) {
1060 err = PTR_ERR(tegra->pll_u_480m);
1061 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1062 goto put_padctl;
1063 }
1064
1065 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1066 if (IS_ERR(tegra->clk_m)) {
1067 err = PTR_ERR(tegra->clk_m);
1068 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1069 goto put_padctl;
1070 }
1071
1072 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1073 if (IS_ERR(tegra->pll_e)) {
1074 err = PTR_ERR(tegra->pll_e);
1075 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1076 goto put_padctl;
1077 }
1078
1079 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1080 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1081 "xusb_host");
1082 if (IS_ERR(tegra->host_rst)) {
1083 err = PTR_ERR(tegra->host_rst);
1084 dev_err(&pdev->dev,
1085 "failed to get xusb_host reset: %d\n", err);
1086 goto put_padctl;
1087 }
1088
1089 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1090 if (IS_ERR(tegra->ss_rst)) {
1091 err = PTR_ERR(tegra->ss_rst);
1092 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1093 err);
1094 goto put_padctl;
1095 }
1096
1097 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1098 tegra->ss_clk,
1099 tegra->ss_rst);
1100 if (err) {
1101 dev_err(&pdev->dev,
1102 "failed to enable XUSBA domain: %d\n", err);
1103 goto put_padctl;
1104 }
1105
1106 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1107 tegra->host_clk,
1108 tegra->host_rst);
1109 if (err) {
1110 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1111 dev_err(&pdev->dev,
1112 "failed to enable XUSBC domain: %d\n", err);
1113 goto put_padctl;
1114 }
1115 } else {
1116 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1117 if (err)
1118 goto put_powerdomains;
1119 }
1120
1121 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1122 sizeof(*tegra->supplies), GFP_KERNEL);
1123 if (!tegra->supplies) {
1124 err = -ENOMEM;
1125 goto put_powerdomains;
1126 }
1127
1128 regulator_bulk_set_supply_names(tegra->supplies,
1129 tegra->soc->supply_names,
1130 tegra->soc->num_supplies);
1131
1132 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1133 tegra->supplies);
1134 if (err) {
1135 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1136 goto put_powerdomains;
1137 }
1138
1139 for (i = 0; i < tegra->soc->num_types; i++)
1140 tegra->num_phys += tegra->soc->phy_types[i].num;
1141
1142 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1143 sizeof(*tegra->phys), GFP_KERNEL);
1144 if (!tegra->phys) {
1145 err = -ENOMEM;
1146 goto put_powerdomains;
1147 }
1148
1149 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1150 char prop[8];
1151
1152 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1153 snprintf(prop, sizeof(prop), "%s-%d",
1154 tegra->soc->phy_types[i].name, j);
1155
1156 phy = devm_phy_optional_get(&pdev->dev, prop);
1157 if (IS_ERR(phy)) {
1158 dev_err(&pdev->dev,
1159 "failed to get PHY %s: %ld\n", prop,
1160 PTR_ERR(phy));
1161 err = PTR_ERR(phy);
1162 goto put_powerdomains;
1163 }
1164
1165 tegra->phys[k++] = phy;
1166 }
1167 }
1168
1169 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1170 dev_name(&pdev->dev));
1171 if (!tegra->hcd) {
1172 err = -ENOMEM;
1173 goto put_powerdomains;
1174 }
1175
1176 /*
1177 * This must happen after usb_create_hcd(), because usb_create_hcd()
1178 * will overwrite the drvdata of the device with the hcd it creates.
1179 */
1180 platform_set_drvdata(pdev, tegra);
1181
1182 err = tegra_xusb_phy_enable(tegra);
1183 if (err < 0) {
1184 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1185 goto put_hcd;
1186 }
1187
1188 pm_runtime_enable(&pdev->dev);
1189 if (pm_runtime_enabled(&pdev->dev))
1190 err = pm_runtime_get_sync(&pdev->dev);
1191 else
1192 err = tegra_xusb_runtime_resume(&pdev->dev);
1193
1194 if (err < 0) {
1195 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1196 goto disable_phy;
1197 }
1198
1199 tegra_xusb_config(tegra, regs);
1200
1201 /*
1202 * The XUSB Falcon microcontroller can only address 40 bits, so set
1203 * the DMA mask accordingly.
1204 */
1205 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1206 if (err < 0) {
1207 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1208 goto put_rpm;
1209 }
1210
1211 err = tegra_xusb_load_firmware(tegra);
1212 if (err < 0) {
1213 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1214 goto put_rpm;
1215 }
1216
1217 tegra->hcd->regs = tegra->regs;
1218 tegra->hcd->rsrc_start = regs->start;
1219 tegra->hcd->rsrc_len = resource_size(regs);
1220
1221 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1222 if (err < 0) {
1223 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1224 goto put_rpm;
1225 }
1226
1227 device_wakeup_enable(tegra->hcd->self.controller);
1228
1229 xhci = hcd_to_xhci(tegra->hcd);
1230
1231 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1232 &pdev->dev,
1233 dev_name(&pdev->dev),
1234 tegra->hcd);
1235 if (!xhci->shared_hcd) {
1236 dev_err(&pdev->dev, "failed to create shared HCD\n");
1237 err = -ENOMEM;
1238 goto remove_usb2;
1239 }
1240
1241 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1242 if (err < 0) {
1243 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1244 goto put_usb3;
1245 }
1246
1247 mutex_lock(&tegra->lock);
1248
1249 /* Enable firmware messages from controller. */
1250 msg.cmd = MBOX_CMD_MSG_ENABLED;
1251 msg.data = 0;
1252
1253 err = tegra_xusb_mbox_send(tegra, &msg);
1254 if (err < 0) {
1255 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1256 mutex_unlock(&tegra->lock);
1257 goto remove_usb3;
1258 }
1259
1260 mutex_unlock(&tegra->lock);
1261
1262 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1263 tegra_xusb_mbox_irq,
1264 tegra_xusb_mbox_thread, 0,
1265 dev_name(&pdev->dev), tegra);
1266 if (err < 0) {
1267 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1268 goto remove_usb3;
1269 }
1270
1271 return 0;
1272
1273 remove_usb3:
1274 usb_remove_hcd(xhci->shared_hcd);
1275 put_usb3:
1276 usb_put_hcd(xhci->shared_hcd);
1277 remove_usb2:
1278 usb_remove_hcd(tegra->hcd);
1279 put_rpm:
1280 if (!pm_runtime_status_suspended(&pdev->dev))
1281 tegra_xusb_runtime_suspend(&pdev->dev);
1282 put_hcd:
1283 usb_put_hcd(tegra->hcd);
1284 disable_phy:
1285 tegra_xusb_phy_disable(tegra);
1286 pm_runtime_disable(&pdev->dev);
1287 put_powerdomains:
1288 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1289 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1290 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1291 } else {
1292 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1293 }
1294 put_padctl:
1295 tegra_xusb_padctl_put(tegra->padctl);
1296 return err;
1297 }
1298
1299 static int tegra_xusb_remove(struct platform_device *pdev)
1300 {
1301 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1302 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1303
1304 usb_remove_hcd(xhci->shared_hcd);
1305 usb_put_hcd(xhci->shared_hcd);
1306 xhci->shared_hcd = NULL;
1307 usb_remove_hcd(tegra->hcd);
1308 usb_put_hcd(tegra->hcd);
1309
1310 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1311 tegra->fw.phys);
1312
1313 pm_runtime_put_sync(&pdev->dev);
1314 pm_runtime_disable(&pdev->dev);
1315
1316 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1317 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1318 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1319 } else {
1320 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1321 }
1322
1323 tegra_xusb_phy_disable(tegra);
1324
1325 tegra_xusb_padctl_put(tegra->padctl);
1326
1327 return 0;
1328 }
1329
1330 #ifdef CONFIG_PM_SLEEP
1331 static int tegra_xusb_suspend(struct device *dev)
1332 {
1333 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1334 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1335 bool wakeup = device_may_wakeup(dev);
1336
1337 /* TODO: Powergate controller across suspend/resume. */
1338 return xhci_suspend(xhci, wakeup);
1339 }
1340
1341 static int tegra_xusb_resume(struct device *dev)
1342 {
1343 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1344 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1345
1346 return xhci_resume(xhci, 0);
1347 }
1348 #endif
1349
1350 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1351 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1352 tegra_xusb_runtime_resume, NULL)
1353 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1354 };
1355
1356 static const char * const tegra124_supply_names[] = {
1357 "avddio-pex",
1358 "dvddio-pex",
1359 "avdd-usb",
1360 "avdd-pll-utmip",
1361 "avdd-pll-erefe",
1362 "avdd-usb-ss-pll",
1363 "hvdd-usb-ss",
1364 "hvdd-usb-ss-pll-e",
1365 };
1366
1367 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1368 { .name = "usb3", .num = 2, },
1369 { .name = "usb2", .num = 3, },
1370 { .name = "hsic", .num = 2, },
1371 };
1372
1373 static const struct tegra_xusb_soc tegra124_soc = {
1374 .firmware = "nvidia/tegra124/xusb.bin",
1375 .supply_names = tegra124_supply_names,
1376 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1377 .phy_types = tegra124_phy_types,
1378 .num_types = ARRAY_SIZE(tegra124_phy_types),
1379 .ports = {
1380 .usb2 = { .offset = 4, .count = 4, },
1381 .hsic = { .offset = 6, .count = 2, },
1382 .usb3 = { .offset = 0, .count = 2, },
1383 },
1384 .scale_ss_clock = true,
1385 .has_ipfs = true,
1386 .mbox = {
1387 .cmd = 0xe4,
1388 .data_in = 0xe8,
1389 .data_out = 0xec,
1390 .owner = 0xf0,
1391 },
1392 };
1393 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1394
1395 static const char * const tegra210_supply_names[] = {
1396 "dvddio-pex",
1397 "hvddio-pex",
1398 "avdd-usb",
1399 "avdd-pll-utmip",
1400 "avdd-pll-uerefe",
1401 "dvdd-pex-pll",
1402 "hvdd-pex-pll-e",
1403 };
1404
1405 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1406 { .name = "usb3", .num = 4, },
1407 { .name = "usb2", .num = 4, },
1408 { .name = "hsic", .num = 1, },
1409 };
1410
1411 static const struct tegra_xusb_soc tegra210_soc = {
1412 .firmware = "nvidia/tegra210/xusb.bin",
1413 .supply_names = tegra210_supply_names,
1414 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1415 .phy_types = tegra210_phy_types,
1416 .num_types = ARRAY_SIZE(tegra210_phy_types),
1417 .ports = {
1418 .usb2 = { .offset = 4, .count = 4, },
1419 .hsic = { .offset = 8, .count = 1, },
1420 .usb3 = { .offset = 0, .count = 4, },
1421 },
1422 .scale_ss_clock = false,
1423 .has_ipfs = true,
1424 .mbox = {
1425 .cmd = 0xe4,
1426 .data_in = 0xe8,
1427 .data_out = 0xec,
1428 .owner = 0xf0,
1429 },
1430 };
1431 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1432
1433 static const char * const tegra186_supply_names[] = {
1434 };
1435
1436 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
1437 { .name = "usb3", .num = 3, },
1438 { .name = "usb2", .num = 3, },
1439 { .name = "hsic", .num = 1, },
1440 };
1441
1442 static const struct tegra_xusb_soc tegra186_soc = {
1443 .firmware = "nvidia/tegra186/xusb.bin",
1444 .supply_names = tegra186_supply_names,
1445 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
1446 .phy_types = tegra186_phy_types,
1447 .num_types = ARRAY_SIZE(tegra186_phy_types),
1448 .ports = {
1449 .usb3 = { .offset = 0, .count = 3, },
1450 .usb2 = { .offset = 3, .count = 3, },
1451 .hsic = { .offset = 6, .count = 1, },
1452 },
1453 .scale_ss_clock = false,
1454 .has_ipfs = false,
1455 .mbox = {
1456 .cmd = 0xe4,
1457 .data_in = 0xe8,
1458 .data_out = 0xec,
1459 .owner = 0xf0,
1460 },
1461 };
1462
1463 static const char * const tegra194_supply_names[] = {
1464 };
1465
1466 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
1467 { .name = "usb3", .num = 4, },
1468 { .name = "usb2", .num = 4, },
1469 };
1470
1471 static const struct tegra_xusb_soc tegra194_soc = {
1472 .firmware = "nvidia/tegra194/xusb.bin",
1473 .supply_names = tegra194_supply_names,
1474 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
1475 .phy_types = tegra194_phy_types,
1476 .num_types = ARRAY_SIZE(tegra194_phy_types),
1477 .ports = {
1478 .usb3 = { .offset = 0, .count = 4, },
1479 .usb2 = { .offset = 4, .count = 4, },
1480 },
1481 .scale_ss_clock = false,
1482 .has_ipfs = false,
1483 .mbox = {
1484 .cmd = 0x68,
1485 .data_in = 0x6c,
1486 .data_out = 0x70,
1487 .owner = 0x74,
1488 },
1489 };
1490 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
1491
1492 static const struct of_device_id tegra_xusb_of_match[] = {
1493 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1494 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1495 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
1496 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
1497 { },
1498 };
1499 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1500
1501 static struct platform_driver tegra_xusb_driver = {
1502 .probe = tegra_xusb_probe,
1503 .remove = tegra_xusb_remove,
1504 .driver = {
1505 .name = "tegra-xusb",
1506 .pm = &tegra_xusb_pm_ops,
1507 .of_match_table = tegra_xusb_of_match,
1508 },
1509 };
1510
1511 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1512 {
1513 xhci->quirks |= XHCI_PLAT;
1514 }
1515
1516 static int tegra_xhci_setup(struct usb_hcd *hcd)
1517 {
1518 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1519 }
1520
1521 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1522 .reset = tegra_xhci_setup,
1523 };
1524
1525 static int __init tegra_xusb_init(void)
1526 {
1527 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1528
1529 return platform_driver_register(&tegra_xusb_driver);
1530 }
1531 module_init(tegra_xusb_init);
1532
1533 static void __exit tegra_xusb_exit(void)
1534 {
1535 platform_driver_unregister(&tegra_xusb_driver);
1536 }
1537 module_exit(tegra_xusb_exit);
1538
1539 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1540 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1541 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support