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USB: usb-storage: unusual_devs update for Super TOP SATA bridge
[linux/fpc-iii.git] / sound / pci / rme9652 / hdspm.c
blobbc030a2088da7928d0b9ebc5830fbeb743c59a37
1 /*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
91
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
135
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
143
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
148
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
156
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
165
166
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
170
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
180
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
196
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
200
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
207
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233 * -- MADI ONLY
234 */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
239
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293 HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
311
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
333 for the AES32
334 */
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
338 * (like inp0)
339 */
340
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
363 * Interrupt
364 */
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
367
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
371
372
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431 HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437 HDSPM_SelSyncRef2)
438
439 /*
440 For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446 HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /* status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
472 /*
473 Timecode
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475 AES i+1
476 bits 3210
477 0001 32kHz
478 0010 44.1kHz
479 0011 48kHz
480 0100 64kHz
481 0101 88.2kHz
482 0110 96kHz
483 0111 128kHz
484 1000 176.4kHz
485 1001 192kHz
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
497
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
501
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
508
509 #define AES32_CHANNELS 16
510
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
519 */
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523 #define HDSPM_RAYDAT_REV 211
524 #define HDSPM_AIO_REV 212
525 #define HDSPM_MADIFACE_REV 213
526
527 /* speed factor modes */
528 #define HDSPM_SPEED_SINGLE 0
529 #define HDSPM_SPEED_DOUBLE 1
530 #define HDSPM_SPEED_QUAD 2
531
532 /* names for speed modes */
533 static char *hdspm_speed_names[] = { "single", "double", "quad" };
534
535 static char *texts_autosync_aes_tco[] = { "Word Clock",
536 "AES1", "AES2", "AES3", "AES4",
537 "AES5", "AES6", "AES7", "AES8",
538 "TCO" };
539 static char *texts_autosync_aes[] = { "Word Clock",
540 "AES1", "AES2", "AES3", "AES4",
541 "AES5", "AES6", "AES7", "AES8" };
542 static char *texts_autosync_madi_tco[] = { "Word Clock",
543 "MADI", "TCO", "Sync In" };
544 static char *texts_autosync_madi[] = { "Word Clock",
545 "MADI", "Sync In" };
546
547 static char *texts_autosync_raydat_tco[] = {
548 "Word Clock",
549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550 "AES", "SPDIF", "TCO", "Sync In"
551 };
552 static char *texts_autosync_raydat[] = {
553 "Word Clock",
554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555 "AES", "SPDIF", "Sync In"
556 };
557 static char *texts_autosync_aio_tco[] = {
558 "Word Clock",
559 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
560 };
561 static char *texts_autosync_aio[] = { "Word Clock",
562 "ADAT", "AES", "SPDIF", "Sync In" };
563
564 static char *texts_freq[] = {
565 "No Lock",
566 "32 kHz",
567 "44.1 kHz",
568 "48 kHz",
569 "64 kHz",
570 "88.2 kHz",
571 "96 kHz",
572 "128 kHz",
573 "176.4 kHz",
574 "192 kHz"
575 };
576
577 static char *texts_ports_madi[] = {
578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
589 };
590
591
592 static char *texts_ports_raydat_ss[] = {
593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598 "ADAT4.7", "ADAT4.8",
599 "AES.L", "AES.R",
600 "SPDIF.L", "SPDIF.R"
601 };
602
603 static char *texts_ports_raydat_ds[] = {
604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
608 "AES.L", "AES.R",
609 "SPDIF.L", "SPDIF.R"
610 };
611
612 static char *texts_ports_raydat_qs[] = {
613 "ADAT1.1", "ADAT1.2",
614 "ADAT2.1", "ADAT2.2",
615 "ADAT3.1", "ADAT3.2",
616 "ADAT4.1", "ADAT4.2",
617 "AES.L", "AES.R",
618 "SPDIF.L", "SPDIF.R"
619 };
620
621
622 static char *texts_ports_aio_in_ss[] = {
623 "Analogue.L", "Analogue.R",
624 "AES.L", "AES.R",
625 "SPDIF.L", "SPDIF.R",
626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
627 "ADAT.7", "ADAT.8"
628 };
629
630 static char *texts_ports_aio_out_ss[] = {
631 "Analogue.L", "Analogue.R",
632 "AES.L", "AES.R",
633 "SPDIF.L", "SPDIF.R",
634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
635 "ADAT.7", "ADAT.8",
636 "Phone.L", "Phone.R"
637 };
638
639 static char *texts_ports_aio_in_ds[] = {
640 "Analogue.L", "Analogue.R",
641 "AES.L", "AES.R",
642 "SPDIF.L", "SPDIF.R",
643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
644 };
645
646 static char *texts_ports_aio_out_ds[] = {
647 "Analogue.L", "Analogue.R",
648 "AES.L", "AES.R",
649 "SPDIF.L", "SPDIF.R",
650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
651 "Phone.L", "Phone.R"
652 };
653
654 static char *texts_ports_aio_in_qs[] = {
655 "Analogue.L", "Analogue.R",
656 "AES.L", "AES.R",
657 "SPDIF.L", "SPDIF.R",
658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
659 };
660
661 static char *texts_ports_aio_out_qs[] = {
662 "Analogue.L", "Analogue.R",
663 "AES.L", "AES.R",
664 "SPDIF.L", "SPDIF.R",
665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
666 "Phone.L", "Phone.R"
667 };
668
669 static char *texts_ports_aes32[] = {
670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
672 "AES.15", "AES.16"
673 };
674
675 /* These tables map the ALSA channels 1..N to the channels that we
676 need to use in order to find the relevant channel buffer. RME
677 refers to this kind of mapping as between "the ADAT channel and
678 the DMA channel." We index it using the logical audio channel,
679 and the value is the DMA channel (i.e. channel buffer number)
680 where the data for that channel can be read/written from/to.
681 */
682
683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684 0, 1, 2, 3, 4, 5, 6, 7,
685 8, 9, 10, 11, 12, 13, 14, 15,
686 16, 17, 18, 19, 20, 21, 22, 23,
687 24, 25, 26, 27, 28, 29, 30, 31,
688 32, 33, 34, 35, 36, 37, 38, 39,
689 40, 41, 42, 43, 44, 45, 46, 47,
690 48, 49, 50, 51, 52, 53, 54, 55,
691 56, 57, 58, 59, 60, 61, 62, 63
692 };
693
694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
699 0, 1, /* AES */
700 2, 3, /* SPDIF */
701 -1, -1, -1, -1,
702 -1, -1, -1, -1, -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
705 };
706
707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708 4, 5, 6, 7, /* ADAT 1 */
709 8, 9, 10, 11, /* ADAT 2 */
710 12, 13, 14, 15, /* ADAT 3 */
711 16, 17, 18, 19, /* ADAT 4 */
712 0, 1, /* AES */
713 2, 3, /* SPDIF */
714 -1, -1, -1, -1,
715 -1, -1, -1, -1, -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
720 };
721
722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
723 4, 5, /* ADAT 1 */
724 6, 7, /* ADAT 2 */
725 8, 9, /* ADAT 3 */
726 10, 11, /* ADAT 4 */
727 0, 1, /* AES */
728 2, 3, /* SPDIF */
729 -1, -1, -1, -1,
730 -1, -1, -1, -1, -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
736 };
737
738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
739 0, 1, /* line in */
740 8, 9, /* aes in, */
741 10, 11, /* spdif in */
742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
743 -1, -1,
744 -1, -1, -1, -1, -1, -1, -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
750 };
751
752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
753 0, 1, /* line out */
754 8, 9, /* aes out */
755 10, 11, /* spdif out */
756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757 6, 7, /* phone out */
758 -1, -1, -1, -1, -1, -1, -1, -1,
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
764 };
765
766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
767 0, 1, /* line in */
768 8, 9, /* aes in */
769 10, 11, /* spdif in */
770 12, 14, 16, 18, /* adat in */
771 -1, -1, -1, -1, -1, -1,
772 -1, -1, -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1
778 };
779
780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
781 0, 1, /* line out */
782 8, 9, /* aes out */
783 10, 11, /* spdif out */
784 12, 14, 16, 18, /* adat out */
785 6, 7, /* phone out */
786 -1, -1, -1, -1,
787 -1, -1, -1, -1, -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1
793 };
794
795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
796 0, 1, /* line in */
797 8, 9, /* aes in */
798 10, 11, /* spdif in */
799 12, 16, /* adat in */
800 -1, -1, -1, -1, -1, -1, -1, -1,
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1
807 };
808
809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
810 0, 1, /* line out */
811 8, 9, /* aes out */
812 10, 11, /* spdif out */
813 12, 16, /* adat out */
814 6, 7, /* phone out */
815 -1, -1, -1, -1, -1, -1,
816 -1, -1, -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1
822 };
823
824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825 0, 1, 2, 3, 4, 5, 6, 7,
826 8, 9, 10, 11, 12, 13, 14, 15,
827 -1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1
833 };
834
835 struct hdspm_midi {
836 struct hdspm *hdspm;
837 int id;
838 struct snd_rawmidi *rmidi;
839 struct snd_rawmidi_substream *input;
840 struct snd_rawmidi_substream *output;
841 char istimer; /* timer in use */
842 struct timer_list timer;
843 spinlock_t lock;
844 int pending;
845 int dataIn;
846 int statusIn;
847 int dataOut;
848 int statusOut;
849 int ie;
850 int irq;
851 };
852
853 struct hdspm_tco {
854 int input;
855 int framerate;
856 int wordclock;
857 int samplerate;
858 int pull;
859 int term; /* 0 = off, 1 = on */
860 };
861
862 struct hdspm {
863 spinlock_t lock;
864 /* only one playback and/or capture stream */
865 struct snd_pcm_substream *capture_substream;
866 struct snd_pcm_substream *playback_substream;
867
868 char *card_name; /* for procinfo */
869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
870
871 uint8_t io_type;
872
873 int monitor_outs; /* set up monitoring outs init flag */
874
875 u32 control_register; /* cached value */
876 u32 control2_register; /* cached value */
877 u32 settings_register;
878
879 struct hdspm_midi midi[4];
880 struct tasklet_struct midi_tasklet;
881
882 size_t period_bytes;
883 unsigned char ss_in_channels;
884 unsigned char ds_in_channels;
885 unsigned char qs_in_channels;
886 unsigned char ss_out_channels;
887 unsigned char ds_out_channels;
888 unsigned char qs_out_channels;
889
890 unsigned char max_channels_in;
891 unsigned char max_channels_out;
892
893 signed char *channel_map_in;
894 signed char *channel_map_out;
895
896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
898
899 char **port_names_in;
900 char **port_names_out;
901
902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
904
905 unsigned char *playback_buffer; /* suitably aligned address */
906 unsigned char *capture_buffer; /* suitably aligned address */
907
908 pid_t capture_pid; /* process id which uses capture */
909 pid_t playback_pid; /* process id which uses capture */
910 int running; /* running status */
911
912 int last_external_sample_rate; /* samplerate mystic ... */
913 int last_internal_sample_rate;
914 int system_sample_rate;
915
916 int dev; /* Hardware vars... */
917 int irq;
918 unsigned long port;
919 void __iomem *iobase;
920
921 int irq_count; /* for debug */
922 int midiPorts;
923
924 struct snd_card *card; /* one card */
925 struct snd_pcm *pcm; /* has one pcm */
926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
927 struct pci_dev *pci; /* and an pci info */
928
929 /* Mixer vars */
930 /* fast alsa mixer */
931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932 /* but input to much, so not used */
933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934 /* full mixer accessible over mixer ioctl or hwdep-device */
935 struct hdspm_mixer *mixer;
936
937 struct hdspm_tco *tco; /* NULL if no TCO detected */
938
939 char **texts_autosync;
940 int texts_autosync_items;
941
942 cycles_t last_interrupt;
943
944 unsigned int serial;
945
946 struct hdspm_peak_rms peak_rms;
947 };
948
949
950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
951 {
952 .vendor = PCI_VENDOR_ID_XILINX,
953 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .class = 0,
957 .class_mask = 0,
958 .driver_data = 0},
959 {0,}
960 };
961
962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
963
964 /* prototypes */
965 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966 struct hdspm * hdspm);
967 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968 struct hdspm * hdspm);
969
970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972 static int hdspm_autosync_ref(struct hdspm *hdspm);
973 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974 static void hdspm_set_sgbuf(struct hdspm *hdspm,
975 struct snd_pcm_substream *substream,
976 unsigned int reg, int channels);
977
978 static inline int HDSPM_bit2freq(int n)
979 {
980 static const int bit2freq_tab[] = {
981 0, 32000, 44100, 48000, 64000, 88200,
982 96000, 128000, 176400, 192000 };
983 if (n < 1 || n > 9)
984 return 0;
985 return bit2freq_tab[n];
986 }
987
988 /* Write/read to/from HDSPM with Adresses in Bytes
989 not words but only 32Bit writes are allowed */
990
991 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
992 unsigned int val)
993 {
994 writel(val, hdspm->iobase + reg);
995 }
996
997 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
998 {
999 return readl(hdspm->iobase + reg);
1000 }
1001
1002 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1003 mixer is write only on hardware so we have to cache him for read
1004 each fader is a u32, but uses only the first 16 bit */
1005
1006 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1007 unsigned int in)
1008 {
1009 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1010 return 0;
1011
1012 return hdspm->mixer->ch[chan].in[in];
1013 }
1014
1015 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1016 unsigned int pb)
1017 {
1018 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1019 return 0;
1020 return hdspm->mixer->ch[chan].pb[pb];
1021 }
1022
1023 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1024 unsigned int in, unsigned short data)
1025 {
1026 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1027 return -1;
1028
1029 hdspm_write(hdspm,
1030 HDSPM_MADI_mixerBase +
1031 ((in + 128 * chan) * sizeof(u32)),
1032 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1033 return 0;
1034 }
1035
1036 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1037 unsigned int pb, unsigned short data)
1038 {
1039 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1040 return -1;
1041
1042 hdspm_write(hdspm,
1043 HDSPM_MADI_mixerBase +
1044 ((64 + pb + 128 * chan) * sizeof(u32)),
1045 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1046 return 0;
1047 }
1048
1049
1050 /* enable DMA for specific channels, now available for DSP-MADI */
1051 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1052 {
1053 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1054 }
1055
1056 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1057 {
1058 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1059 }
1060
1061 /* check if same process is writing and reading */
1062 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1063 {
1064 unsigned long flags;
1065 int ret = 1;
1066
1067 spin_lock_irqsave(&hdspm->lock, flags);
1068 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1069 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1070 ret = 0;
1071 }
1072 spin_unlock_irqrestore(&hdspm->lock, flags);
1073 return ret;
1074 }
1075
1076 /* check for external sample rate */
1077 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1078 {
1079 unsigned int status, status2, timecode;
1080 int syncref, rate = 0, rate_bits;
1081
1082 switch (hdspm->io_type) {
1083 case AES32:
1084 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1085 status = hdspm_read(hdspm, HDSPM_statusRegister);
1086 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1087
1088 syncref = hdspm_autosync_ref(hdspm);
1089
1090 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1091 status & HDSPM_AES32_wcLock)
1092 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1093
1094 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1095 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1096 status2 & (HDSPM_LockAES >>
1097 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1098 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1099 return 0;
1100 break;
1101
1102 case MADIface:
1103 status = hdspm_read(hdspm, HDSPM_statusRegister);
1104
1105 if (!(status & HDSPM_madiLock)) {
1106 rate = 0; /* no lock */
1107 } else {
1108 switch (status & (HDSPM_status1_freqMask)) {
1109 case HDSPM_status1_F_0*1:
1110 rate = 32000; break;
1111 case HDSPM_status1_F_0*2:
1112 rate = 44100; break;
1113 case HDSPM_status1_F_0*3:
1114 rate = 48000; break;
1115 case HDSPM_status1_F_0*4:
1116 rate = 64000; break;
1117 case HDSPM_status1_F_0*5:
1118 rate = 88200; break;
1119 case HDSPM_status1_F_0*6:
1120 rate = 96000; break;
1121 case HDSPM_status1_F_0*7:
1122 rate = 128000; break;
1123 case HDSPM_status1_F_0*8:
1124 rate = 176400; break;
1125 case HDSPM_status1_F_0*9:
1126 rate = 192000; break;
1127 default:
1128 rate = 0; break;
1129 }
1130 }
1131
1132 break;
1133
1134 case MADI:
1135 case AIO:
1136 case RayDAT:
1137 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1138 status = hdspm_read(hdspm, HDSPM_statusRegister);
1139 rate = 0;
1140
1141 /* if wordclock has synced freq and wordclock is valid */
1142 if ((status2 & HDSPM_wcLock) != 0 &&
1143 (status2 & HDSPM_SelSyncRef0) == 0) {
1144
1145 rate_bits = status2 & HDSPM_wcFreqMask;
1146
1147
1148 switch (rate_bits) {
1149 case HDSPM_wcFreq32:
1150 rate = 32000;
1151 break;
1152 case HDSPM_wcFreq44_1:
1153 rate = 44100;
1154 break;
1155 case HDSPM_wcFreq48:
1156 rate = 48000;
1157 break;
1158 case HDSPM_wcFreq64:
1159 rate = 64000;
1160 break;
1161 case HDSPM_wcFreq88_2:
1162 rate = 88200;
1163 break;
1164 case HDSPM_wcFreq96:
1165 rate = 96000;
1166 break;
1167 default:
1168 rate = 0;
1169 break;
1170 }
1171 }
1172
1173 /* if rate detected and Syncref is Word than have it,
1174 * word has priority to MADI
1175 */
1176 if (rate != 0 &&
1177 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1178 return rate;
1179
1180 /* maybe a madi input (which is taken if sel sync is madi) */
1181 if (status & HDSPM_madiLock) {
1182 rate_bits = status & HDSPM_madiFreqMask;
1183
1184 switch (rate_bits) {
1185 case HDSPM_madiFreq32:
1186 rate = 32000;
1187 break;
1188 case HDSPM_madiFreq44_1:
1189 rate = 44100;
1190 break;
1191 case HDSPM_madiFreq48:
1192 rate = 48000;
1193 break;
1194 case HDSPM_madiFreq64:
1195 rate = 64000;
1196 break;
1197 case HDSPM_madiFreq88_2:
1198 rate = 88200;
1199 break;
1200 case HDSPM_madiFreq96:
1201 rate = 96000;
1202 break;
1203 case HDSPM_madiFreq128:
1204 rate = 128000;
1205 break;
1206 case HDSPM_madiFreq176_4:
1207 rate = 176400;
1208 break;
1209 case HDSPM_madiFreq192:
1210 rate = 192000;
1211 break;
1212 default:
1213 rate = 0;
1214 break;
1215 }
1216
1217 /* QS and DS rates normally can not be detected
1218 * automatically by the card. Only exception is MADI
1219 * in 96k frame mode.
1220 *
1221 * So if we read SS values (32 .. 48k), check for
1222 * user-provided DS/QS bits in the control register
1223 * and multiply the base frequency accordingly.
1224 */
1225 if (rate <= 48000) {
1226 if (hdspm->control_register & HDSPM_QuadSpeed)
1227 rate *= 4;
1228 else if (hdspm->control_register &
1229 HDSPM_DoubleSpeed)
1230 rate *= 2;
1231 }
1232 }
1233 break;
1234 }
1235
1236 return rate;
1237 }
1238
1239 /* return latency in samples per period */
1240 static int hdspm_get_latency(struct hdspm *hdspm)
1241 {
1242 int n;
1243
1244 n = hdspm_decode_latency(hdspm->control_register);
1245
1246 /* Special case for new RME cards with 32 samples period size.
1247 * The three latency bits in the control register
1248 * (HDSP_LatencyMask) encode latency values of 64 samples as
1249 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1250 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1251 * it corresponds to 32 samples.
1252 */
1253 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1254 n = -1;
1255
1256 return 1 << (n + 6);
1257 }
1258
1259 /* Latency function */
1260 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1261 {
1262 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1263 }
1264
1265
1266 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1267 {
1268 int position;
1269
1270 position = hdspm_read(hdspm, HDSPM_statusRegister);
1271
1272 switch (hdspm->io_type) {
1273 case RayDAT:
1274 case AIO:
1275 position &= HDSPM_BufferPositionMask;
1276 position /= 4; /* Bytes per sample */
1277 break;
1278 default:
1279 position = (position & HDSPM_BufferID) ?
1280 (hdspm->period_bytes / 4) : 0;
1281 }
1282
1283 return position;
1284 }
1285
1286
1287 static inline void hdspm_start_audio(struct hdspm * s)
1288 {
1289 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1290 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1291 }
1292
1293 static inline void hdspm_stop_audio(struct hdspm * s)
1294 {
1295 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1296 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1297 }
1298
1299 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1300 static void hdspm_silence_playback(struct hdspm *hdspm)
1301 {
1302 int i;
1303 int n = hdspm->period_bytes;
1304 void *buf = hdspm->playback_buffer;
1305
1306 if (buf == NULL)
1307 return;
1308
1309 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1310 memset(buf, 0, n);
1311 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1312 }
1313 }
1314
1315 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1316 {
1317 int n;
1318
1319 spin_lock_irq(&s->lock);
1320
1321 if (32 == frames) {
1322 /* Special case for new RME cards like RayDAT/AIO which
1323 * support period sizes of 32 samples. Since latency is
1324 * encoded in the three bits of HDSP_LatencyMask, we can only
1325 * have values from 0 .. 7. While 0 still means 64 samples and
1326 * 6 represents 4096 samples on all cards, 7 represents 8192
1327 * on older cards and 32 samples on new cards.
1328 *
1329 * In other words, period size in samples is calculated by
1330 * 2^(n+6) with n ranging from 0 .. 7.
1331 */
1332 n = 7;
1333 } else {
1334 frames >>= 7;
1335 n = 0;
1336 while (frames) {
1337 n++;
1338 frames >>= 1;
1339 }
1340 }
1341
1342 s->control_register &= ~HDSPM_LatencyMask;
1343 s->control_register |= hdspm_encode_latency(n);
1344
1345 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1346
1347 hdspm_compute_period_size(s);
1348
1349 spin_unlock_irq(&s->lock);
1350
1351 return 0;
1352 }
1353
1354 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1355 {
1356 u64 freq_const;
1357
1358 if (period == 0)
1359 return 0;
1360
1361 switch (hdspm->io_type) {
1362 case MADI:
1363 case AES32:
1364 freq_const = 110069313433624ULL;
1365 break;
1366 case RayDAT:
1367 case AIO:
1368 freq_const = 104857600000000ULL;
1369 break;
1370 case MADIface:
1371 freq_const = 131072000000000ULL;
1372 break;
1373 default:
1374 snd_BUG();
1375 return 0;
1376 }
1377
1378 return div_u64(freq_const, period);
1379 }
1380
1381
1382 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1383 {
1384 u64 n;
1385
1386 if (rate >= 112000)
1387 rate /= 4;
1388 else if (rate >= 56000)
1389 rate /= 2;
1390
1391 switch (hdspm->io_type) {
1392 case MADIface:
1393 n = 131072000000000ULL; /* 125 MHz */
1394 break;
1395 case MADI:
1396 case AES32:
1397 n = 110069313433624ULL; /* 105 MHz */
1398 break;
1399 case RayDAT:
1400 case AIO:
1401 n = 104857600000000ULL; /* 100 MHz */
1402 break;
1403 default:
1404 snd_BUG();
1405 return;
1406 }
1407
1408 n = div_u64(n, rate);
1409 /* n should be less than 2^32 for being written to FREQ register */
1410 snd_BUG_ON(n >> 32);
1411 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1412 }
1413
1414 /* dummy set rate lets see what happens */
1415 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1416 {
1417 int current_rate;
1418 int rate_bits;
1419 int not_set = 0;
1420 int current_speed, target_speed;
1421
1422 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1423 it (e.g. during module initialization).
1424 */
1425
1426 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1427
1428 /* SLAVE --- */
1429 if (called_internally) {
1430
1431 /* request from ctl or card initialization
1432 just make a warning an remember setting
1433 for future master mode switching */
1434
1435 snd_printk(KERN_WARNING "HDSPM: "
1436 "Warning: device is not running "
1437 "as a clock master.\n");
1438 not_set = 1;
1439 } else {
1440
1441 /* hw_param request while in AutoSync mode */
1442 int external_freq =
1443 hdspm_external_sample_rate(hdspm);
1444
1445 if (hdspm_autosync_ref(hdspm) ==
1446 HDSPM_AUTOSYNC_FROM_NONE) {
1447
1448 snd_printk(KERN_WARNING "HDSPM: "
1449 "Detected no Externel Sync \n");
1450 not_set = 1;
1451
1452 } else if (rate != external_freq) {
1453
1454 snd_printk(KERN_WARNING "HDSPM: "
1455 "Warning: No AutoSync source for "
1456 "requested rate\n");
1457 not_set = 1;
1458 }
1459 }
1460 }
1461
1462 current_rate = hdspm->system_sample_rate;
1463
1464 /* Changing between Singe, Double and Quad speed is not
1465 allowed if any substreams are open. This is because such a change
1466 causes a shift in the location of the DMA buffers and a reduction
1467 in the number of available buffers.
1468
1469 Note that a similar but essentially insoluble problem exists for
1470 externally-driven rate changes. All we can do is to flag rate
1471 changes in the read/write routines.
1472 */
1473
1474 if (current_rate <= 48000)
1475 current_speed = HDSPM_SPEED_SINGLE;
1476 else if (current_rate <= 96000)
1477 current_speed = HDSPM_SPEED_DOUBLE;
1478 else
1479 current_speed = HDSPM_SPEED_QUAD;
1480
1481 if (rate <= 48000)
1482 target_speed = HDSPM_SPEED_SINGLE;
1483 else if (rate <= 96000)
1484 target_speed = HDSPM_SPEED_DOUBLE;
1485 else
1486 target_speed = HDSPM_SPEED_QUAD;
1487
1488 switch (rate) {
1489 case 32000:
1490 rate_bits = HDSPM_Frequency32KHz;
1491 break;
1492 case 44100:
1493 rate_bits = HDSPM_Frequency44_1KHz;
1494 break;
1495 case 48000:
1496 rate_bits = HDSPM_Frequency48KHz;
1497 break;
1498 case 64000:
1499 rate_bits = HDSPM_Frequency64KHz;
1500 break;
1501 case 88200:
1502 rate_bits = HDSPM_Frequency88_2KHz;
1503 break;
1504 case 96000:
1505 rate_bits = HDSPM_Frequency96KHz;
1506 break;
1507 case 128000:
1508 rate_bits = HDSPM_Frequency128KHz;
1509 break;
1510 case 176400:
1511 rate_bits = HDSPM_Frequency176_4KHz;
1512 break;
1513 case 192000:
1514 rate_bits = HDSPM_Frequency192KHz;
1515 break;
1516 default:
1517 return -EINVAL;
1518 }
1519
1520 if (current_speed != target_speed
1521 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1522 snd_printk
1523 (KERN_ERR "HDSPM: "
1524 "cannot change from %s speed to %s speed mode "
1525 "(capture PID = %d, playback PID = %d)\n",
1526 hdspm_speed_names[current_speed],
1527 hdspm_speed_names[target_speed],
1528 hdspm->capture_pid, hdspm->playback_pid);
1529 return -EBUSY;
1530 }
1531
1532 hdspm->control_register &= ~HDSPM_FrequencyMask;
1533 hdspm->control_register |= rate_bits;
1534 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1535
1536 /* For AES32, need to set DDS value in FREQ register
1537 For MADI, also apparently */
1538 hdspm_set_dds_value(hdspm, rate);
1539
1540 if (AES32 == hdspm->io_type && rate != current_rate)
1541 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1542
1543 hdspm->system_sample_rate = rate;
1544
1545 if (rate <= 48000) {
1546 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1547 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1548 hdspm->max_channels_in = hdspm->ss_in_channels;
1549 hdspm->max_channels_out = hdspm->ss_out_channels;
1550 hdspm->port_names_in = hdspm->port_names_in_ss;
1551 hdspm->port_names_out = hdspm->port_names_out_ss;
1552 } else if (rate <= 96000) {
1553 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1554 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1555 hdspm->max_channels_in = hdspm->ds_in_channels;
1556 hdspm->max_channels_out = hdspm->ds_out_channels;
1557 hdspm->port_names_in = hdspm->port_names_in_ds;
1558 hdspm->port_names_out = hdspm->port_names_out_ds;
1559 } else {
1560 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1561 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1562 hdspm->max_channels_in = hdspm->qs_in_channels;
1563 hdspm->max_channels_out = hdspm->qs_out_channels;
1564 hdspm->port_names_in = hdspm->port_names_in_qs;
1565 hdspm->port_names_out = hdspm->port_names_out_qs;
1566 }
1567
1568 if (not_set != 0)
1569 return -1;
1570
1571 return 0;
1572 }
1573
1574 /* mainly for init to 0 on load */
1575 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1576 {
1577 int i, j;
1578 unsigned int gain;
1579
1580 if (sgain > UNITY_GAIN)
1581 gain = UNITY_GAIN;
1582 else if (sgain < 0)
1583 gain = 0;
1584 else
1585 gain = sgain;
1586
1587 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1588 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1589 hdspm_write_in_gain(hdspm, i, j, gain);
1590 hdspm_write_pb_gain(hdspm, i, j, gain);
1591 }
1592 }
1593
1594 /*----------------------------------------------------------------------------
1595 MIDI
1596 ----------------------------------------------------------------------------*/
1597
1598 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1599 int id)
1600 {
1601 /* the hardware already does the relevant bit-mask with 0xff */
1602 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1603 }
1604
1605 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1606 int val)
1607 {
1608 /* the hardware already does the relevant bit-mask with 0xff */
1609 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1610 }
1611
1612 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1613 {
1614 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1615 }
1616
1617 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1618 {
1619 int fifo_bytes_used;
1620
1621 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1622
1623 if (fifo_bytes_used < 128)
1624 return 128 - fifo_bytes_used;
1625 else
1626 return 0;
1627 }
1628
1629 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1630 {
1631 while (snd_hdspm_midi_input_available (hdspm, id))
1632 snd_hdspm_midi_read_byte (hdspm, id);
1633 }
1634
1635 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1636 {
1637 unsigned long flags;
1638 int n_pending;
1639 int to_write;
1640 int i;
1641 unsigned char buf[128];
1642
1643 /* Output is not interrupt driven */
1644
1645 spin_lock_irqsave (&hmidi->lock, flags);
1646 if (hmidi->output &&
1647 !snd_rawmidi_transmit_empty (hmidi->output)) {
1648 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1649 hmidi->id);
1650 if (n_pending > 0) {
1651 if (n_pending > (int)sizeof (buf))
1652 n_pending = sizeof (buf);
1653
1654 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1655 n_pending);
1656 if (to_write > 0) {
1657 for (i = 0; i < to_write; ++i)
1658 snd_hdspm_midi_write_byte (hmidi->hdspm,
1659 hmidi->id,
1660 buf[i]);
1661 }
1662 }
1663 }
1664 spin_unlock_irqrestore (&hmidi->lock, flags);
1665 return 0;
1666 }
1667
1668 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1669 {
1670 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1671 * input FIFO size
1672 */
1673 unsigned long flags;
1674 int n_pending;
1675 int i;
1676
1677 spin_lock_irqsave (&hmidi->lock, flags);
1678 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1679 if (n_pending > 0) {
1680 if (hmidi->input) {
1681 if (n_pending > (int)sizeof (buf))
1682 n_pending = sizeof (buf);
1683 for (i = 0; i < n_pending; ++i)
1684 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1685 hmidi->id);
1686 if (n_pending)
1687 snd_rawmidi_receive (hmidi->input, buf,
1688 n_pending);
1689 } else {
1690 /* flush the MIDI input FIFO */
1691 while (n_pending--)
1692 snd_hdspm_midi_read_byte (hmidi->hdspm,
1693 hmidi->id);
1694 }
1695 }
1696 hmidi->pending = 0;
1697 spin_unlock_irqrestore(&hmidi->lock, flags);
1698
1699 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1700 hmidi->hdspm->control_register |= hmidi->ie;
1701 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1702 hmidi->hdspm->control_register);
1703 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1704
1705 return snd_hdspm_midi_output_write (hmidi);
1706 }
1707
1708 static void
1709 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1710 {
1711 struct hdspm *hdspm;
1712 struct hdspm_midi *hmidi;
1713 unsigned long flags;
1714
1715 hmidi = substream->rmidi->private_data;
1716 hdspm = hmidi->hdspm;
1717
1718 spin_lock_irqsave (&hdspm->lock, flags);
1719 if (up) {
1720 if (!(hdspm->control_register & hmidi->ie)) {
1721 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1722 hdspm->control_register |= hmidi->ie;
1723 }
1724 } else {
1725 hdspm->control_register &= ~hmidi->ie;
1726 }
1727
1728 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1729 spin_unlock_irqrestore (&hdspm->lock, flags);
1730 }
1731
1732 static void snd_hdspm_midi_output_timer(unsigned long data)
1733 {
1734 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1735 unsigned long flags;
1736
1737 snd_hdspm_midi_output_write(hmidi);
1738 spin_lock_irqsave (&hmidi->lock, flags);
1739
1740 /* this does not bump hmidi->istimer, because the
1741 kernel automatically removed the timer when it
1742 expired, and we are now adding it back, thus
1743 leaving istimer wherever it was set before.
1744 */
1745
1746 if (hmidi->istimer) {
1747 hmidi->timer.expires = 1 + jiffies;
1748 add_timer(&hmidi->timer);
1749 }
1750
1751 spin_unlock_irqrestore (&hmidi->lock, flags);
1752 }
1753
1754 static void
1755 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1756 {
1757 struct hdspm_midi *hmidi;
1758 unsigned long flags;
1759
1760 hmidi = substream->rmidi->private_data;
1761 spin_lock_irqsave (&hmidi->lock, flags);
1762 if (up) {
1763 if (!hmidi->istimer) {
1764 init_timer(&hmidi->timer);
1765 hmidi->timer.function = snd_hdspm_midi_output_timer;
1766 hmidi->timer.data = (unsigned long) hmidi;
1767 hmidi->timer.expires = 1 + jiffies;
1768 add_timer(&hmidi->timer);
1769 hmidi->istimer++;
1770 }
1771 } else {
1772 if (hmidi->istimer && --hmidi->istimer <= 0)
1773 del_timer (&hmidi->timer);
1774 }
1775 spin_unlock_irqrestore (&hmidi->lock, flags);
1776 if (up)
1777 snd_hdspm_midi_output_write(hmidi);
1778 }
1779
1780 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1781 {
1782 struct hdspm_midi *hmidi;
1783
1784 hmidi = substream->rmidi->private_data;
1785 spin_lock_irq (&hmidi->lock);
1786 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1787 hmidi->input = substream;
1788 spin_unlock_irq (&hmidi->lock);
1789
1790 return 0;
1791 }
1792
1793 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1794 {
1795 struct hdspm_midi *hmidi;
1796
1797 hmidi = substream->rmidi->private_data;
1798 spin_lock_irq (&hmidi->lock);
1799 hmidi->output = substream;
1800 spin_unlock_irq (&hmidi->lock);
1801
1802 return 0;
1803 }
1804
1805 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1806 {
1807 struct hdspm_midi *hmidi;
1808
1809 snd_hdspm_midi_input_trigger (substream, 0);
1810
1811 hmidi = substream->rmidi->private_data;
1812 spin_lock_irq (&hmidi->lock);
1813 hmidi->input = NULL;
1814 spin_unlock_irq (&hmidi->lock);
1815
1816 return 0;
1817 }
1818
1819 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1820 {
1821 struct hdspm_midi *hmidi;
1822
1823 snd_hdspm_midi_output_trigger (substream, 0);
1824
1825 hmidi = substream->rmidi->private_data;
1826 spin_lock_irq (&hmidi->lock);
1827 hmidi->output = NULL;
1828 spin_unlock_irq (&hmidi->lock);
1829
1830 return 0;
1831 }
1832
1833 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1834 {
1835 .open = snd_hdspm_midi_output_open,
1836 .close = snd_hdspm_midi_output_close,
1837 .trigger = snd_hdspm_midi_output_trigger,
1838 };
1839
1840 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1841 {
1842 .open = snd_hdspm_midi_input_open,
1843 .close = snd_hdspm_midi_input_close,
1844 .trigger = snd_hdspm_midi_input_trigger,
1845 };
1846
1847 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1848 struct hdspm *hdspm, int id)
1849 {
1850 int err;
1851 char buf[32];
1852
1853 hdspm->midi[id].id = id;
1854 hdspm->midi[id].hdspm = hdspm;
1855 spin_lock_init (&hdspm->midi[id].lock);
1856
1857 if (0 == id) {
1858 if (MADIface == hdspm->io_type) {
1859 /* MIDI-over-MADI on HDSPe MADIface */
1860 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1861 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1862 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1863 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1864 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1865 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1866 } else {
1867 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1868 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1869 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1870 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1871 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1872 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1873 }
1874 } else if (1 == id) {
1875 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1876 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1877 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1878 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1879 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1880 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1881 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1882 /* MIDI-over-MADI on HDSPe MADI */
1883 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1884 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1885 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1886 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1887 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1888 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1889 } else if (2 == id) {
1890 /* TCO MTC, read only */
1891 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1892 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1893 hdspm->midi[2].dataOut = -1;
1894 hdspm->midi[2].statusOut = -1;
1895 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1896 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1897 } else if (3 == id) {
1898 /* TCO MTC on HDSPe MADI */
1899 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1900 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1901 hdspm->midi[3].dataOut = -1;
1902 hdspm->midi[3].statusOut = -1;
1903 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1904 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1905 }
1906
1907 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1908 (MADIface == hdspm->io_type)))) {
1909 if ((id == 0) && (MADIface == hdspm->io_type)) {
1910 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1911 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1912 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1913 } else {
1914 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1915 }
1916 err = snd_rawmidi_new(card, buf, id, 1, 1,
1917 &hdspm->midi[id].rmidi);
1918 if (err < 0)
1919 return err;
1920
1921 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1922 card->id, id+1);
1923 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1924
1925 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1926 SNDRV_RAWMIDI_STREAM_OUTPUT,
1927 &snd_hdspm_midi_output);
1928 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1929 SNDRV_RAWMIDI_STREAM_INPUT,
1930 &snd_hdspm_midi_input);
1931
1932 hdspm->midi[id].rmidi->info_flags |=
1933 SNDRV_RAWMIDI_INFO_OUTPUT |
1934 SNDRV_RAWMIDI_INFO_INPUT |
1935 SNDRV_RAWMIDI_INFO_DUPLEX;
1936 } else {
1937 /* TCO MTC, read only */
1938 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1939 err = snd_rawmidi_new(card, buf, id, 1, 1,
1940 &hdspm->midi[id].rmidi);
1941 if (err < 0)
1942 return err;
1943
1944 sprintf(hdspm->midi[id].rmidi->name,
1945 "%s MTC %d", card->id, id+1);
1946 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1947
1948 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1949 SNDRV_RAWMIDI_STREAM_INPUT,
1950 &snd_hdspm_midi_input);
1951
1952 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1953 }
1954
1955 return 0;
1956 }
1957
1958
1959 static void hdspm_midi_tasklet(unsigned long arg)
1960 {
1961 struct hdspm *hdspm = (struct hdspm *)arg;
1962 int i = 0;
1963
1964 while (i < hdspm->midiPorts) {
1965 if (hdspm->midi[i].pending)
1966 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1967
1968 i++;
1969 }
1970 }
1971
1972
1973 /*-----------------------------------------------------------------------------
1974 Status Interface
1975 ----------------------------------------------------------------------------*/
1976
1977 /* get the system sample rate which is set */
1978
1979
1980 /**
1981 * Calculate the real sample rate from the
1982 * current DDS value.
1983 **/
1984 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1985 {
1986 unsigned int period, rate;
1987
1988 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1989 rate = hdspm_calc_dds_value(hdspm, period);
1990
1991 return rate;
1992 }
1993
1994
1995 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1996 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1997 .name = xname, \
1998 .index = xindex, \
1999 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2000 .info = snd_hdspm_info_system_sample_rate, \
2001 .get = snd_hdspm_get_system_sample_rate \
2002 }
2003
2004 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_info *uinfo)
2006 {
2007 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2008 uinfo->count = 1;
2009 uinfo->value.integer.min = 27000;
2010 uinfo->value.integer.max = 207000;
2011 uinfo->value.integer.step = 1;
2012 return 0;
2013 }
2014
2015
2016 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2017 struct snd_ctl_elem_value *
2018 ucontrol)
2019 {
2020 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2021
2022 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2023 return 0;
2024 }
2025
2026
2027 /**
2028 * Returns the WordClock sample rate class for the given card.
2029 **/
2030 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2031 {
2032 int status;
2033
2034 switch (hdspm->io_type) {
2035 case RayDAT:
2036 case AIO:
2037 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2038 return (status >> 16) & 0xF;
2039 break;
2040 default:
2041 break;
2042 }
2043
2044
2045 return 0;
2046 }
2047
2048
2049 /**
2050 * Returns the TCO sample rate class for the given card.
2051 **/
2052 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2053 {
2054 int status;
2055
2056 if (hdspm->tco) {
2057 switch (hdspm->io_type) {
2058 case RayDAT:
2059 case AIO:
2060 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2061 return (status >> 20) & 0xF;
2062 break;
2063 default:
2064 break;
2065 }
2066 }
2067
2068 return 0;
2069 }
2070
2071
2072 /**
2073 * Returns the SYNC_IN sample rate class for the given card.
2074 **/
2075 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2076 {
2077 int status;
2078
2079 if (hdspm->tco) {
2080 switch (hdspm->io_type) {
2081 case RayDAT:
2082 case AIO:
2083 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2084 return (status >> 12) & 0xF;
2085 break;
2086 default:
2087 break;
2088 }
2089 }
2090
2091 return 0;
2092 }
2093
2094
2095 /**
2096 * Returns the sample rate class for input source <idx> for
2097 * 'new style' cards like the AIO and RayDAT.
2098 **/
2099 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2100 {
2101 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2102
2103 return (status >> (idx*4)) & 0xF;
2104 }
2105
2106
2107
2108 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2109 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2110 .name = xname, \
2111 .private_value = xindex, \
2112 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2113 .info = snd_hdspm_info_autosync_sample_rate, \
2114 .get = snd_hdspm_get_autosync_sample_rate \
2115 }
2116
2117
2118 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2119 struct snd_ctl_elem_info *uinfo)
2120 {
2121 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2122 uinfo->count = 1;
2123 uinfo->value.enumerated.items = 10;
2124
2125 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2126 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2127 strcpy(uinfo->value.enumerated.name,
2128 texts_freq[uinfo->value.enumerated.item]);
2129 return 0;
2130 }
2131
2132
2133 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2134 struct snd_ctl_elem_value *
2135 ucontrol)
2136 {
2137 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2138
2139 switch (hdspm->io_type) {
2140 case RayDAT:
2141 switch (kcontrol->private_value) {
2142 case 0:
2143 ucontrol->value.enumerated.item[0] =
2144 hdspm_get_wc_sample_rate(hdspm);
2145 break;
2146 case 7:
2147 ucontrol->value.enumerated.item[0] =
2148 hdspm_get_tco_sample_rate(hdspm);
2149 break;
2150 case 8:
2151 ucontrol->value.enumerated.item[0] =
2152 hdspm_get_sync_in_sample_rate(hdspm);
2153 break;
2154 default:
2155 ucontrol->value.enumerated.item[0] =
2156 hdspm_get_s1_sample_rate(hdspm,
2157 kcontrol->private_value-1);
2158 }
2159
2160 case AIO:
2161 switch (kcontrol->private_value) {
2162 case 0: /* WC */
2163 ucontrol->value.enumerated.item[0] =
2164 hdspm_get_wc_sample_rate(hdspm);
2165 break;
2166 case 4: /* TCO */
2167 ucontrol->value.enumerated.item[0] =
2168 hdspm_get_tco_sample_rate(hdspm);
2169 break;
2170 case 5: /* SYNC_IN */
2171 ucontrol->value.enumerated.item[0] =
2172 hdspm_get_sync_in_sample_rate(hdspm);
2173 break;
2174 default:
2175 ucontrol->value.enumerated.item[0] =
2176 hdspm_get_s1_sample_rate(hdspm,
2177 ucontrol->id.index-1);
2178 }
2179
2180 case AES32:
2181
2182 switch (kcontrol->private_value) {
2183 case 0: /* WC */
2184 ucontrol->value.enumerated.item[0] =
2185 hdspm_get_wc_sample_rate(hdspm);
2186 break;
2187 case 9: /* TCO */
2188 ucontrol->value.enumerated.item[0] =
2189 hdspm_get_tco_sample_rate(hdspm);
2190 break;
2191 case 10: /* SYNC_IN */
2192 ucontrol->value.enumerated.item[0] =
2193 hdspm_get_sync_in_sample_rate(hdspm);
2194 break;
2195 default: /* AES1 to AES8 */
2196 ucontrol->value.enumerated.item[0] =
2197 hdspm_get_s1_sample_rate(hdspm,
2198 kcontrol->private_value-1);
2199 break;
2200
2201 }
2202 default:
2203 break;
2204 }
2205
2206 return 0;
2207 }
2208
2209
2210 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2211 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2212 .name = xname, \
2213 .index = xindex, \
2214 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2215 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2216 .info = snd_hdspm_info_system_clock_mode, \
2217 .get = snd_hdspm_get_system_clock_mode, \
2218 .put = snd_hdspm_put_system_clock_mode, \
2219 }
2220
2221
2222 /**
2223 * Returns the system clock mode for the given card.
2224 * @returns 0 - master, 1 - slave
2225 **/
2226 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2227 {
2228 switch (hdspm->io_type) {
2229 case AIO:
2230 case RayDAT:
2231 if (hdspm->settings_register & HDSPM_c0Master)
2232 return 0;
2233 break;
2234
2235 default:
2236 if (hdspm->control_register & HDSPM_ClockModeMaster)
2237 return 0;
2238 }
2239
2240 return 1;
2241 }
2242
2243
2244 /**
2245 * Sets the system clock mode.
2246 * @param mode 0 - master, 1 - slave
2247 **/
2248 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2249 {
2250 switch (hdspm->io_type) {
2251 case AIO:
2252 case RayDAT:
2253 if (0 == mode)
2254 hdspm->settings_register |= HDSPM_c0Master;
2255 else
2256 hdspm->settings_register &= ~HDSPM_c0Master;
2257
2258 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2259 break;
2260
2261 default:
2262 if (0 == mode)
2263 hdspm->control_register |= HDSPM_ClockModeMaster;
2264 else
2265 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2266
2267 hdspm_write(hdspm, HDSPM_controlRegister,
2268 hdspm->control_register);
2269 }
2270 }
2271
2272
2273 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_info *uinfo)
2275 {
2276 static char *texts[] = { "Master", "AutoSync" };
2277
2278 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2279 uinfo->count = 1;
2280 uinfo->value.enumerated.items = 2;
2281 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2282 uinfo->value.enumerated.item =
2283 uinfo->value.enumerated.items - 1;
2284 strcpy(uinfo->value.enumerated.name,
2285 texts[uinfo->value.enumerated.item]);
2286 return 0;
2287 }
2288
2289 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2290 struct snd_ctl_elem_value *ucontrol)
2291 {
2292 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2293
2294 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2295 return 0;
2296 }
2297
2298 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2299 struct snd_ctl_elem_value *ucontrol)
2300 {
2301 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2302 int val;
2303
2304 if (!snd_hdspm_use_is_exclusive(hdspm))
2305 return -EBUSY;
2306
2307 val = ucontrol->value.enumerated.item[0];
2308 if (val < 0)
2309 val = 0;
2310 else if (val > 1)
2311 val = 1;
2312
2313 hdspm_set_system_clock_mode(hdspm, val);
2314
2315 return 0;
2316 }
2317
2318
2319 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2320 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2321 .name = xname, \
2322 .index = xindex, \
2323 .info = snd_hdspm_info_clock_source, \
2324 .get = snd_hdspm_get_clock_source, \
2325 .put = snd_hdspm_put_clock_source \
2326 }
2327
2328
2329 static int hdspm_clock_source(struct hdspm * hdspm)
2330 {
2331 switch (hdspm->system_sample_rate) {
2332 case 32000: return 0;
2333 case 44100: return 1;
2334 case 48000: return 2;
2335 case 64000: return 3;
2336 case 88200: return 4;
2337 case 96000: return 5;
2338 case 128000: return 6;
2339 case 176400: return 7;
2340 case 192000: return 8;
2341 }
2342
2343 return -1;
2344 }
2345
2346 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2347 {
2348 int rate;
2349 switch (mode) {
2350 case 0:
2351 rate = 32000; break;
2352 case 1:
2353 rate = 44100; break;
2354 case 2:
2355 rate = 48000; break;
2356 case 3:
2357 rate = 64000; break;
2358 case 4:
2359 rate = 88200; break;
2360 case 5:
2361 rate = 96000; break;
2362 case 6:
2363 rate = 128000; break;
2364 case 7:
2365 rate = 176400; break;
2366 case 8:
2367 rate = 192000; break;
2368 default:
2369 rate = 48000;
2370 }
2371 hdspm_set_rate(hdspm, rate, 1);
2372 return 0;
2373 }
2374
2375 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2376 struct snd_ctl_elem_info *uinfo)
2377 {
2378 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2379 uinfo->count = 1;
2380 uinfo->value.enumerated.items = 9;
2381
2382 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2383 uinfo->value.enumerated.item =
2384 uinfo->value.enumerated.items - 1;
2385
2386 strcpy(uinfo->value.enumerated.name,
2387 texts_freq[uinfo->value.enumerated.item+1]);
2388
2389 return 0;
2390 }
2391
2392 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2393 struct snd_ctl_elem_value *ucontrol)
2394 {
2395 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2396
2397 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2398 return 0;
2399 }
2400
2401 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2402 struct snd_ctl_elem_value *ucontrol)
2403 {
2404 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2405 int change;
2406 int val;
2407
2408 if (!snd_hdspm_use_is_exclusive(hdspm))
2409 return -EBUSY;
2410 val = ucontrol->value.enumerated.item[0];
2411 if (val < 0)
2412 val = 0;
2413 if (val > 9)
2414 val = 9;
2415 spin_lock_irq(&hdspm->lock);
2416 if (val != hdspm_clock_source(hdspm))
2417 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2418 else
2419 change = 0;
2420 spin_unlock_irq(&hdspm->lock);
2421 return change;
2422 }
2423
2424
2425 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2426 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2427 .name = xname, \
2428 .index = xindex, \
2429 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2430 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2431 .info = snd_hdspm_info_pref_sync_ref, \
2432 .get = snd_hdspm_get_pref_sync_ref, \
2433 .put = snd_hdspm_put_pref_sync_ref \
2434 }
2435
2436
2437 /**
2438 * Returns the current preferred sync reference setting.
2439 * The semantics of the return value are depending on the
2440 * card, please see the comments for clarification.
2441 **/
2442 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2443 {
2444 switch (hdspm->io_type) {
2445 case AES32:
2446 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2447 case 0: return 0; /* WC */
2448 case HDSPM_SyncRef0: return 1; /* AES 1 */
2449 case HDSPM_SyncRef1: return 2; /* AES 2 */
2450 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2451 case HDSPM_SyncRef2: return 4; /* AES 4 */
2452 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2453 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2454 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2455 return 7; /* AES 7 */
2456 case HDSPM_SyncRef3: return 8; /* AES 8 */
2457 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2458 }
2459 break;
2460
2461 case MADI:
2462 case MADIface:
2463 if (hdspm->tco) {
2464 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2465 case 0: return 0; /* WC */
2466 case HDSPM_SyncRef0: return 1; /* MADI */
2467 case HDSPM_SyncRef1: return 2; /* TCO */
2468 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2469 return 3; /* SYNC_IN */
2470 }
2471 } else {
2472 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2473 case 0: return 0; /* WC */
2474 case HDSPM_SyncRef0: return 1; /* MADI */
2475 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2476 return 2; /* SYNC_IN */
2477 }
2478 }
2479 break;
2480
2481 case RayDAT:
2482 if (hdspm->tco) {
2483 switch ((hdspm->settings_register &
2484 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2485 case 0: return 0; /* WC */
2486 case 3: return 1; /* ADAT 1 */
2487 case 4: return 2; /* ADAT 2 */
2488 case 5: return 3; /* ADAT 3 */
2489 case 6: return 4; /* ADAT 4 */
2490 case 1: return 5; /* AES */
2491 case 2: return 6; /* SPDIF */
2492 case 9: return 7; /* TCO */
2493 case 10: return 8; /* SYNC_IN */
2494 }
2495 } else {
2496 switch ((hdspm->settings_register &
2497 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2498 case 0: return 0; /* WC */
2499 case 3: return 1; /* ADAT 1 */
2500 case 4: return 2; /* ADAT 2 */
2501 case 5: return 3; /* ADAT 3 */
2502 case 6: return 4; /* ADAT 4 */
2503 case 1: return 5; /* AES */
2504 case 2: return 6; /* SPDIF */
2505 case 10: return 7; /* SYNC_IN */
2506 }
2507 }
2508
2509 break;
2510
2511 case AIO:
2512 if (hdspm->tco) {
2513 switch ((hdspm->settings_register &
2514 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2515 case 0: return 0; /* WC */
2516 case 3: return 1; /* ADAT */
2517 case 1: return 2; /* AES */
2518 case 2: return 3; /* SPDIF */
2519 case 9: return 4; /* TCO */
2520 case 10: return 5; /* SYNC_IN */
2521 }
2522 } else {
2523 switch ((hdspm->settings_register &
2524 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2525 case 0: return 0; /* WC */
2526 case 3: return 1; /* ADAT */
2527 case 1: return 2; /* AES */
2528 case 2: return 3; /* SPDIF */
2529 case 10: return 4; /* SYNC_IN */
2530 }
2531 }
2532
2533 break;
2534 }
2535
2536 return -1;
2537 }
2538
2539
2540 /**
2541 * Set the preferred sync reference to <pref>. The semantics
2542 * of <pref> are depending on the card type, see the comments
2543 * for clarification.
2544 **/
2545 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2546 {
2547 int p = 0;
2548
2549 switch (hdspm->io_type) {
2550 case AES32:
2551 hdspm->control_register &= ~HDSPM_SyncRefMask;
2552 switch (pref) {
2553 case 0: /* WC */
2554 break;
2555 case 1: /* AES 1 */
2556 hdspm->control_register |= HDSPM_SyncRef0;
2557 break;
2558 case 2: /* AES 2 */
2559 hdspm->control_register |= HDSPM_SyncRef1;
2560 break;
2561 case 3: /* AES 3 */
2562 hdspm->control_register |=
2563 HDSPM_SyncRef1+HDSPM_SyncRef0;
2564 break;
2565 case 4: /* AES 4 */
2566 hdspm->control_register |= HDSPM_SyncRef2;
2567 break;
2568 case 5: /* AES 5 */
2569 hdspm->control_register |=
2570 HDSPM_SyncRef2+HDSPM_SyncRef0;
2571 break;
2572 case 6: /* AES 6 */
2573 hdspm->control_register |=
2574 HDSPM_SyncRef2+HDSPM_SyncRef1;
2575 break;
2576 case 7: /* AES 7 */
2577 hdspm->control_register |=
2578 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2579 break;
2580 case 8: /* AES 8 */
2581 hdspm->control_register |= HDSPM_SyncRef3;
2582 break;
2583 case 9: /* TCO */
2584 hdspm->control_register |=
2585 HDSPM_SyncRef3+HDSPM_SyncRef0;
2586 break;
2587 default:
2588 return -1;
2589 }
2590
2591 break;
2592
2593 case MADI:
2594 case MADIface:
2595 hdspm->control_register &= ~HDSPM_SyncRefMask;
2596 if (hdspm->tco) {
2597 switch (pref) {
2598 case 0: /* WC */
2599 break;
2600 case 1: /* MADI */
2601 hdspm->control_register |= HDSPM_SyncRef0;
2602 break;
2603 case 2: /* TCO */
2604 hdspm->control_register |= HDSPM_SyncRef1;
2605 break;
2606 case 3: /* SYNC_IN */
2607 hdspm->control_register |=
2608 HDSPM_SyncRef0+HDSPM_SyncRef1;
2609 break;
2610 default:
2611 return -1;
2612 }
2613 } else {
2614 switch (pref) {
2615 case 0: /* WC */
2616 break;
2617 case 1: /* MADI */
2618 hdspm->control_register |= HDSPM_SyncRef0;
2619 break;
2620 case 2: /* SYNC_IN */
2621 hdspm->control_register |=
2622 HDSPM_SyncRef0+HDSPM_SyncRef1;
2623 break;
2624 default:
2625 return -1;
2626 }
2627 }
2628
2629 break;
2630
2631 case RayDAT:
2632 if (hdspm->tco) {
2633 switch (pref) {
2634 case 0: p = 0; break; /* WC */
2635 case 1: p = 3; break; /* ADAT 1 */
2636 case 2: p = 4; break; /* ADAT 2 */
2637 case 3: p = 5; break; /* ADAT 3 */
2638 case 4: p = 6; break; /* ADAT 4 */
2639 case 5: p = 1; break; /* AES */
2640 case 6: p = 2; break; /* SPDIF */
2641 case 7: p = 9; break; /* TCO */
2642 case 8: p = 10; break; /* SYNC_IN */
2643 default: return -1;
2644 }
2645 } else {
2646 switch (pref) {
2647 case 0: p = 0; break; /* WC */
2648 case 1: p = 3; break; /* ADAT 1 */
2649 case 2: p = 4; break; /* ADAT 2 */
2650 case 3: p = 5; break; /* ADAT 3 */
2651 case 4: p = 6; break; /* ADAT 4 */
2652 case 5: p = 1; break; /* AES */
2653 case 6: p = 2; break; /* SPDIF */
2654 case 7: p = 10; break; /* SYNC_IN */
2655 default: return -1;
2656 }
2657 }
2658 break;
2659
2660 case AIO:
2661 if (hdspm->tco) {
2662 switch (pref) {
2663 case 0: p = 0; break; /* WC */
2664 case 1: p = 3; break; /* ADAT */
2665 case 2: p = 1; break; /* AES */
2666 case 3: p = 2; break; /* SPDIF */
2667 case 4: p = 9; break; /* TCO */
2668 case 5: p = 10; break; /* SYNC_IN */
2669 default: return -1;
2670 }
2671 } else {
2672 switch (pref) {
2673 case 0: p = 0; break; /* WC */
2674 case 1: p = 3; break; /* ADAT */
2675 case 2: p = 1; break; /* AES */
2676 case 3: p = 2; break; /* SPDIF */
2677 case 4: p = 10; break; /* SYNC_IN */
2678 default: return -1;
2679 }
2680 }
2681 break;
2682 }
2683
2684 switch (hdspm->io_type) {
2685 case RayDAT:
2686 case AIO:
2687 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2688 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2689 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2690 break;
2691
2692 case MADI:
2693 case MADIface:
2694 case AES32:
2695 hdspm_write(hdspm, HDSPM_controlRegister,
2696 hdspm->control_register);
2697 }
2698
2699 return 0;
2700 }
2701
2702
2703 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2704 struct snd_ctl_elem_info *uinfo)
2705 {
2706 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2707
2708 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2709 uinfo->count = 1;
2710 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2711
2712 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2713 uinfo->value.enumerated.item =
2714 uinfo->value.enumerated.items - 1;
2715
2716 strcpy(uinfo->value.enumerated.name,
2717 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2718
2719 return 0;
2720 }
2721
2722 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2723 struct snd_ctl_elem_value *ucontrol)
2724 {
2725 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2726 int psf = hdspm_pref_sync_ref(hdspm);
2727
2728 if (psf >= 0) {
2729 ucontrol->value.enumerated.item[0] = psf;
2730 return 0;
2731 }
2732
2733 return -1;
2734 }
2735
2736 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2737 struct snd_ctl_elem_value *ucontrol)
2738 {
2739 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2740 int val, change = 0;
2741
2742 if (!snd_hdspm_use_is_exclusive(hdspm))
2743 return -EBUSY;
2744
2745 val = ucontrol->value.enumerated.item[0];
2746
2747 if (val < 0)
2748 val = 0;
2749 else if (val >= hdspm->texts_autosync_items)
2750 val = hdspm->texts_autosync_items-1;
2751
2752 spin_lock_irq(&hdspm->lock);
2753 if (val != hdspm_pref_sync_ref(hdspm))
2754 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2755
2756 spin_unlock_irq(&hdspm->lock);
2757 return change;
2758 }
2759
2760
2761 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2763 .name = xname, \
2764 .index = xindex, \
2765 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2766 .info = snd_hdspm_info_autosync_ref, \
2767 .get = snd_hdspm_get_autosync_ref, \
2768 }
2769
2770 static int hdspm_autosync_ref(struct hdspm *hdspm)
2771 {
2772 if (AES32 == hdspm->io_type) {
2773 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2774 unsigned int syncref =
2775 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2776 if (syncref == 0)
2777 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2778 if (syncref <= 8)
2779 return syncref;
2780 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2781 } else if (MADI == hdspm->io_type) {
2782 /* This looks at the autosync selected sync reference */
2783 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2784
2785 switch (status2 & HDSPM_SelSyncRefMask) {
2786 case HDSPM_SelSyncRef_WORD:
2787 return HDSPM_AUTOSYNC_FROM_WORD;
2788 case HDSPM_SelSyncRef_MADI:
2789 return HDSPM_AUTOSYNC_FROM_MADI;
2790 case HDSPM_SelSyncRef_TCO:
2791 return HDSPM_AUTOSYNC_FROM_TCO;
2792 case HDSPM_SelSyncRef_SyncIn:
2793 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2794 case HDSPM_SelSyncRef_NVALID:
2795 return HDSPM_AUTOSYNC_FROM_NONE;
2796 default:
2797 return 0;
2798 }
2799
2800 }
2801 return 0;
2802 }
2803
2804
2805 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2806 struct snd_ctl_elem_info *uinfo)
2807 {
2808 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2809
2810 if (AES32 == hdspm->io_type) {
2811 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2812 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2813
2814 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2815 uinfo->count = 1;
2816 uinfo->value.enumerated.items = 10;
2817 if (uinfo->value.enumerated.item >=
2818 uinfo->value.enumerated.items)
2819 uinfo->value.enumerated.item =
2820 uinfo->value.enumerated.items - 1;
2821 strcpy(uinfo->value.enumerated.name,
2822 texts[uinfo->value.enumerated.item]);
2823 } else if (MADI == hdspm->io_type) {
2824 static char *texts[] = {"Word Clock", "MADI", "TCO",
2825 "Sync In", "None" };
2826
2827 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2828 uinfo->count = 1;
2829 uinfo->value.enumerated.items = 5;
2830 if (uinfo->value.enumerated.item >=
2831 uinfo->value.enumerated.items)
2832 uinfo->value.enumerated.item =
2833 uinfo->value.enumerated.items - 1;
2834 strcpy(uinfo->value.enumerated.name,
2835 texts[uinfo->value.enumerated.item]);
2836 }
2837 return 0;
2838 }
2839
2840 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2841 struct snd_ctl_elem_value *ucontrol)
2842 {
2843 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2844
2845 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2846 return 0;
2847 }
2848
2849
2850 #define HDSPM_LINE_OUT(xname, xindex) \
2851 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2852 .name = xname, \
2853 .index = xindex, \
2854 .info = snd_hdspm_info_line_out, \
2855 .get = snd_hdspm_get_line_out, \
2856 .put = snd_hdspm_put_line_out \
2857 }
2858
2859 static int hdspm_line_out(struct hdspm * hdspm)
2860 {
2861 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2862 }
2863
2864
2865 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2866 {
2867 if (out)
2868 hdspm->control_register |= HDSPM_LineOut;
2869 else
2870 hdspm->control_register &= ~HDSPM_LineOut;
2871 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2872
2873 return 0;
2874 }
2875
2876 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2877
2878 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2879 struct snd_ctl_elem_value *ucontrol)
2880 {
2881 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2882
2883 spin_lock_irq(&hdspm->lock);
2884 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2885 spin_unlock_irq(&hdspm->lock);
2886 return 0;
2887 }
2888
2889 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2890 struct snd_ctl_elem_value *ucontrol)
2891 {
2892 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2893 int change;
2894 unsigned int val;
2895
2896 if (!snd_hdspm_use_is_exclusive(hdspm))
2897 return -EBUSY;
2898 val = ucontrol->value.integer.value[0] & 1;
2899 spin_lock_irq(&hdspm->lock);
2900 change = (int) val != hdspm_line_out(hdspm);
2901 hdspm_set_line_output(hdspm, val);
2902 spin_unlock_irq(&hdspm->lock);
2903 return change;
2904 }
2905
2906
2907 #define HDSPM_TX_64(xname, xindex) \
2908 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2909 .name = xname, \
2910 .index = xindex, \
2911 .info = snd_hdspm_info_tx_64, \
2912 .get = snd_hdspm_get_tx_64, \
2913 .put = snd_hdspm_put_tx_64 \
2914 }
2915
2916 static int hdspm_tx_64(struct hdspm * hdspm)
2917 {
2918 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2919 }
2920
2921 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2922 {
2923 if (out)
2924 hdspm->control_register |= HDSPM_TX_64ch;
2925 else
2926 hdspm->control_register &= ~HDSPM_TX_64ch;
2927 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2928
2929 return 0;
2930 }
2931
2932 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2933
2934 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2935 struct snd_ctl_elem_value *ucontrol)
2936 {
2937 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2938
2939 spin_lock_irq(&hdspm->lock);
2940 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2941 spin_unlock_irq(&hdspm->lock);
2942 return 0;
2943 }
2944
2945 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2946 struct snd_ctl_elem_value *ucontrol)
2947 {
2948 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2949 int change;
2950 unsigned int val;
2951
2952 if (!snd_hdspm_use_is_exclusive(hdspm))
2953 return -EBUSY;
2954 val = ucontrol->value.integer.value[0] & 1;
2955 spin_lock_irq(&hdspm->lock);
2956 change = (int) val != hdspm_tx_64(hdspm);
2957 hdspm_set_tx_64(hdspm, val);
2958 spin_unlock_irq(&hdspm->lock);
2959 return change;
2960 }
2961
2962
2963 #define HDSPM_C_TMS(xname, xindex) \
2964 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2965 .name = xname, \
2966 .index = xindex, \
2967 .info = snd_hdspm_info_c_tms, \
2968 .get = snd_hdspm_get_c_tms, \
2969 .put = snd_hdspm_put_c_tms \
2970 }
2971
2972 static int hdspm_c_tms(struct hdspm * hdspm)
2973 {
2974 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2975 }
2976
2977 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2978 {
2979 if (out)
2980 hdspm->control_register |= HDSPM_clr_tms;
2981 else
2982 hdspm->control_register &= ~HDSPM_clr_tms;
2983 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2984
2985 return 0;
2986 }
2987
2988 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2989
2990 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2991 struct snd_ctl_elem_value *ucontrol)
2992 {
2993 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2994
2995 spin_lock_irq(&hdspm->lock);
2996 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2997 spin_unlock_irq(&hdspm->lock);
2998 return 0;
2999 }
3000
3001 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3002 struct snd_ctl_elem_value *ucontrol)
3003 {
3004 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3005 int change;
3006 unsigned int val;
3007
3008 if (!snd_hdspm_use_is_exclusive(hdspm))
3009 return -EBUSY;
3010 val = ucontrol->value.integer.value[0] & 1;
3011 spin_lock_irq(&hdspm->lock);
3012 change = (int) val != hdspm_c_tms(hdspm);
3013 hdspm_set_c_tms(hdspm, val);
3014 spin_unlock_irq(&hdspm->lock);
3015 return change;
3016 }
3017
3018
3019 #define HDSPM_SAFE_MODE(xname, xindex) \
3020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3021 .name = xname, \
3022 .index = xindex, \
3023 .info = snd_hdspm_info_safe_mode, \
3024 .get = snd_hdspm_get_safe_mode, \
3025 .put = snd_hdspm_put_safe_mode \
3026 }
3027
3028 static int hdspm_safe_mode(struct hdspm * hdspm)
3029 {
3030 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3031 }
3032
3033 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3034 {
3035 if (out)
3036 hdspm->control_register |= HDSPM_AutoInp;
3037 else
3038 hdspm->control_register &= ~HDSPM_AutoInp;
3039 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3040
3041 return 0;
3042 }
3043
3044 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3045
3046 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3047 struct snd_ctl_elem_value *ucontrol)
3048 {
3049 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3050
3051 spin_lock_irq(&hdspm->lock);
3052 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3053 spin_unlock_irq(&hdspm->lock);
3054 return 0;
3055 }
3056
3057 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3058 struct snd_ctl_elem_value *ucontrol)
3059 {
3060 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3061 int change;
3062 unsigned int val;
3063
3064 if (!snd_hdspm_use_is_exclusive(hdspm))
3065 return -EBUSY;
3066 val = ucontrol->value.integer.value[0] & 1;
3067 spin_lock_irq(&hdspm->lock);
3068 change = (int) val != hdspm_safe_mode(hdspm);
3069 hdspm_set_safe_mode(hdspm, val);
3070 spin_unlock_irq(&hdspm->lock);
3071 return change;
3072 }
3073
3074
3075 #define HDSPM_EMPHASIS(xname, xindex) \
3076 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3077 .name = xname, \
3078 .index = xindex, \
3079 .info = snd_hdspm_info_emphasis, \
3080 .get = snd_hdspm_get_emphasis, \
3081 .put = snd_hdspm_put_emphasis \
3082 }
3083
3084 static int hdspm_emphasis(struct hdspm * hdspm)
3085 {
3086 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3087 }
3088
3089 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3090 {
3091 if (emp)
3092 hdspm->control_register |= HDSPM_Emphasis;
3093 else
3094 hdspm->control_register &= ~HDSPM_Emphasis;
3095 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3096
3097 return 0;
3098 }
3099
3100 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3101
3102 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3103 struct snd_ctl_elem_value *ucontrol)
3104 {
3105 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3106
3107 spin_lock_irq(&hdspm->lock);
3108 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3109 spin_unlock_irq(&hdspm->lock);
3110 return 0;
3111 }
3112
3113 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3114 struct snd_ctl_elem_value *ucontrol)
3115 {
3116 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3117 int change;
3118 unsigned int val;
3119
3120 if (!snd_hdspm_use_is_exclusive(hdspm))
3121 return -EBUSY;
3122 val = ucontrol->value.integer.value[0] & 1;
3123 spin_lock_irq(&hdspm->lock);
3124 change = (int) val != hdspm_emphasis(hdspm);
3125 hdspm_set_emphasis(hdspm, val);
3126 spin_unlock_irq(&hdspm->lock);
3127 return change;
3128 }
3129
3130
3131 #define HDSPM_DOLBY(xname, xindex) \
3132 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3133 .name = xname, \
3134 .index = xindex, \
3135 .info = snd_hdspm_info_dolby, \
3136 .get = snd_hdspm_get_dolby, \
3137 .put = snd_hdspm_put_dolby \
3138 }
3139
3140 static int hdspm_dolby(struct hdspm * hdspm)
3141 {
3142 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3143 }
3144
3145 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3146 {
3147 if (dol)
3148 hdspm->control_register |= HDSPM_Dolby;
3149 else
3150 hdspm->control_register &= ~HDSPM_Dolby;
3151 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3152
3153 return 0;
3154 }
3155
3156 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3157
3158 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3159 struct snd_ctl_elem_value *ucontrol)
3160 {
3161 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3162
3163 spin_lock_irq(&hdspm->lock);
3164 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3165 spin_unlock_irq(&hdspm->lock);
3166 return 0;
3167 }
3168
3169 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3170 struct snd_ctl_elem_value *ucontrol)
3171 {
3172 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3173 int change;
3174 unsigned int val;
3175
3176 if (!snd_hdspm_use_is_exclusive(hdspm))
3177 return -EBUSY;
3178 val = ucontrol->value.integer.value[0] & 1;
3179 spin_lock_irq(&hdspm->lock);
3180 change = (int) val != hdspm_dolby(hdspm);
3181 hdspm_set_dolby(hdspm, val);
3182 spin_unlock_irq(&hdspm->lock);
3183 return change;
3184 }
3185
3186
3187 #define HDSPM_PROFESSIONAL(xname, xindex) \
3188 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3189 .name = xname, \
3190 .index = xindex, \
3191 .info = snd_hdspm_info_professional, \
3192 .get = snd_hdspm_get_professional, \
3193 .put = snd_hdspm_put_professional \
3194 }
3195
3196 static int hdspm_professional(struct hdspm * hdspm)
3197 {
3198 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3199 }
3200
3201 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3202 {
3203 if (dol)
3204 hdspm->control_register |= HDSPM_Professional;
3205 else
3206 hdspm->control_register &= ~HDSPM_Professional;
3207 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3208
3209 return 0;
3210 }
3211
3212 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3213
3214 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3215 struct snd_ctl_elem_value *ucontrol)
3216 {
3217 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3218
3219 spin_lock_irq(&hdspm->lock);
3220 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3221 spin_unlock_irq(&hdspm->lock);
3222 return 0;
3223 }
3224
3225 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3226 struct snd_ctl_elem_value *ucontrol)
3227 {
3228 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3229 int change;
3230 unsigned int val;
3231
3232 if (!snd_hdspm_use_is_exclusive(hdspm))
3233 return -EBUSY;
3234 val = ucontrol->value.integer.value[0] & 1;
3235 spin_lock_irq(&hdspm->lock);
3236 change = (int) val != hdspm_professional(hdspm);
3237 hdspm_set_professional(hdspm, val);
3238 spin_unlock_irq(&hdspm->lock);
3239 return change;
3240 }
3241
3242 #define HDSPM_INPUT_SELECT(xname, xindex) \
3243 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3244 .name = xname, \
3245 .index = xindex, \
3246 .info = snd_hdspm_info_input_select, \
3247 .get = snd_hdspm_get_input_select, \
3248 .put = snd_hdspm_put_input_select \
3249 }
3250
3251 static int hdspm_input_select(struct hdspm * hdspm)
3252 {
3253 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3254 }
3255
3256 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3257 {
3258 if (out)
3259 hdspm->control_register |= HDSPM_InputSelect0;
3260 else
3261 hdspm->control_register &= ~HDSPM_InputSelect0;
3262 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3263
3264 return 0;
3265 }
3266
3267 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3268 struct snd_ctl_elem_info *uinfo)
3269 {
3270 static char *texts[] = { "optical", "coaxial" };
3271
3272 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3273 uinfo->count = 1;
3274 uinfo->value.enumerated.items = 2;
3275
3276 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3277 uinfo->value.enumerated.item =
3278 uinfo->value.enumerated.items - 1;
3279 strcpy(uinfo->value.enumerated.name,
3280 texts[uinfo->value.enumerated.item]);
3281
3282 return 0;
3283 }
3284
3285 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3286 struct snd_ctl_elem_value *ucontrol)
3287 {
3288 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3289
3290 spin_lock_irq(&hdspm->lock);
3291 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3292 spin_unlock_irq(&hdspm->lock);
3293 return 0;
3294 }
3295
3296 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3297 struct snd_ctl_elem_value *ucontrol)
3298 {
3299 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3300 int change;
3301 unsigned int val;
3302
3303 if (!snd_hdspm_use_is_exclusive(hdspm))
3304 return -EBUSY;
3305 val = ucontrol->value.integer.value[0] & 1;
3306 spin_lock_irq(&hdspm->lock);
3307 change = (int) val != hdspm_input_select(hdspm);
3308 hdspm_set_input_select(hdspm, val);
3309 spin_unlock_irq(&hdspm->lock);
3310 return change;
3311 }
3312
3313
3314 #define HDSPM_DS_WIRE(xname, xindex) \
3315 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3316 .name = xname, \
3317 .index = xindex, \
3318 .info = snd_hdspm_info_ds_wire, \
3319 .get = snd_hdspm_get_ds_wire, \
3320 .put = snd_hdspm_put_ds_wire \
3321 }
3322
3323 static int hdspm_ds_wire(struct hdspm * hdspm)
3324 {
3325 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3326 }
3327
3328 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3329 {
3330 if (ds)
3331 hdspm->control_register |= HDSPM_DS_DoubleWire;
3332 else
3333 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3334 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3335
3336 return 0;
3337 }
3338
3339 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3340 struct snd_ctl_elem_info *uinfo)
3341 {
3342 static char *texts[] = { "Single", "Double" };
3343
3344 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3345 uinfo->count = 1;
3346 uinfo->value.enumerated.items = 2;
3347
3348 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3349 uinfo->value.enumerated.item =
3350 uinfo->value.enumerated.items - 1;
3351 strcpy(uinfo->value.enumerated.name,
3352 texts[uinfo->value.enumerated.item]);
3353
3354 return 0;
3355 }
3356
3357 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3358 struct snd_ctl_elem_value *ucontrol)
3359 {
3360 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3361
3362 spin_lock_irq(&hdspm->lock);
3363 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3364 spin_unlock_irq(&hdspm->lock);
3365 return 0;
3366 }
3367
3368 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3369 struct snd_ctl_elem_value *ucontrol)
3370 {
3371 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3372 int change;
3373 unsigned int val;
3374
3375 if (!snd_hdspm_use_is_exclusive(hdspm))
3376 return -EBUSY;
3377 val = ucontrol->value.integer.value[0] & 1;
3378 spin_lock_irq(&hdspm->lock);
3379 change = (int) val != hdspm_ds_wire(hdspm);
3380 hdspm_set_ds_wire(hdspm, val);
3381 spin_unlock_irq(&hdspm->lock);
3382 return change;
3383 }
3384
3385
3386 #define HDSPM_QS_WIRE(xname, xindex) \
3387 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3388 .name = xname, \
3389 .index = xindex, \
3390 .info = snd_hdspm_info_qs_wire, \
3391 .get = snd_hdspm_get_qs_wire, \
3392 .put = snd_hdspm_put_qs_wire \
3393 }
3394
3395 static int hdspm_qs_wire(struct hdspm * hdspm)
3396 {
3397 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3398 return 1;
3399 if (hdspm->control_register & HDSPM_QS_QuadWire)
3400 return 2;
3401 return 0;
3402 }
3403
3404 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3405 {
3406 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3407 switch (mode) {
3408 case 0:
3409 break;
3410 case 1:
3411 hdspm->control_register |= HDSPM_QS_DoubleWire;
3412 break;
3413 case 2:
3414 hdspm->control_register |= HDSPM_QS_QuadWire;
3415 break;
3416 }
3417 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3418
3419 return 0;
3420 }
3421
3422 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3423 struct snd_ctl_elem_info *uinfo)
3424 {
3425 static char *texts[] = { "Single", "Double", "Quad" };
3426
3427 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3428 uinfo->count = 1;
3429 uinfo->value.enumerated.items = 3;
3430
3431 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3432 uinfo->value.enumerated.item =
3433 uinfo->value.enumerated.items - 1;
3434 strcpy(uinfo->value.enumerated.name,
3435 texts[uinfo->value.enumerated.item]);
3436
3437 return 0;
3438 }
3439
3440 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3441 struct snd_ctl_elem_value *ucontrol)
3442 {
3443 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3444
3445 spin_lock_irq(&hdspm->lock);
3446 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3447 spin_unlock_irq(&hdspm->lock);
3448 return 0;
3449 }
3450
3451 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3452 struct snd_ctl_elem_value *ucontrol)
3453 {
3454 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3455 int change;
3456 int val;
3457
3458 if (!snd_hdspm_use_is_exclusive(hdspm))
3459 return -EBUSY;
3460 val = ucontrol->value.integer.value[0];
3461 if (val < 0)
3462 val = 0;
3463 if (val > 2)
3464 val = 2;
3465 spin_lock_irq(&hdspm->lock);
3466 change = val != hdspm_qs_wire(hdspm);
3467 hdspm_set_qs_wire(hdspm, val);
3468 spin_unlock_irq(&hdspm->lock);
3469 return change;
3470 }
3471
3472 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3473 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3474 .name = xname, \
3475 .index = xindex, \
3476 .info = snd_hdspm_info_madi_speedmode, \
3477 .get = snd_hdspm_get_madi_speedmode, \
3478 .put = snd_hdspm_put_madi_speedmode \
3479 }
3480
3481 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3482 {
3483 if (hdspm->control_register & HDSPM_QuadSpeed)
3484 return 2;
3485 if (hdspm->control_register & HDSPM_DoubleSpeed)
3486 return 1;
3487 return 0;
3488 }
3489
3490 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3491 {
3492 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3493 switch (mode) {
3494 case 0:
3495 break;
3496 case 1:
3497 hdspm->control_register |= HDSPM_DoubleSpeed;
3498 break;
3499 case 2:
3500 hdspm->control_register |= HDSPM_QuadSpeed;
3501 break;
3502 }
3503 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3504
3505 return 0;
3506 }
3507
3508 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3509 struct snd_ctl_elem_info *uinfo)
3510 {
3511 static char *texts[] = { "Single", "Double", "Quad" };
3512
3513 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3514 uinfo->count = 1;
3515 uinfo->value.enumerated.items = 3;
3516
3517 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3518 uinfo->value.enumerated.item =
3519 uinfo->value.enumerated.items - 1;
3520 strcpy(uinfo->value.enumerated.name,
3521 texts[uinfo->value.enumerated.item]);
3522
3523 return 0;
3524 }
3525
3526 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3527 struct snd_ctl_elem_value *ucontrol)
3528 {
3529 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3530
3531 spin_lock_irq(&hdspm->lock);
3532 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3533 spin_unlock_irq(&hdspm->lock);
3534 return 0;
3535 }
3536
3537 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3538 struct snd_ctl_elem_value *ucontrol)
3539 {
3540 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3541 int change;
3542 int val;
3543
3544 if (!snd_hdspm_use_is_exclusive(hdspm))
3545 return -EBUSY;
3546 val = ucontrol->value.integer.value[0];
3547 if (val < 0)
3548 val = 0;
3549 if (val > 2)
3550 val = 2;
3551 spin_lock_irq(&hdspm->lock);
3552 change = val != hdspm_madi_speedmode(hdspm);
3553 hdspm_set_madi_speedmode(hdspm, val);
3554 spin_unlock_irq(&hdspm->lock);
3555 return change;
3556 }
3557
3558 #define HDSPM_MIXER(xname, xindex) \
3559 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3560 .name = xname, \
3561 .index = xindex, \
3562 .device = 0, \
3563 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3564 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3565 .info = snd_hdspm_info_mixer, \
3566 .get = snd_hdspm_get_mixer, \
3567 .put = snd_hdspm_put_mixer \
3568 }
3569
3570 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3571 struct snd_ctl_elem_info *uinfo)
3572 {
3573 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3574 uinfo->count = 3;
3575 uinfo->value.integer.min = 0;
3576 uinfo->value.integer.max = 65535;
3577 uinfo->value.integer.step = 1;
3578 return 0;
3579 }
3580
3581 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3582 struct snd_ctl_elem_value *ucontrol)
3583 {
3584 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3585 int source;
3586 int destination;
3587
3588 source = ucontrol->value.integer.value[0];
3589 if (source < 0)
3590 source = 0;
3591 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3592 source = 2 * HDSPM_MAX_CHANNELS - 1;
3593
3594 destination = ucontrol->value.integer.value[1];
3595 if (destination < 0)
3596 destination = 0;
3597 else if (destination >= HDSPM_MAX_CHANNELS)
3598 destination = HDSPM_MAX_CHANNELS - 1;
3599
3600 spin_lock_irq(&hdspm->lock);
3601 if (source >= HDSPM_MAX_CHANNELS)
3602 ucontrol->value.integer.value[2] =
3603 hdspm_read_pb_gain(hdspm, destination,
3604 source - HDSPM_MAX_CHANNELS);
3605 else
3606 ucontrol->value.integer.value[2] =
3607 hdspm_read_in_gain(hdspm, destination, source);
3608
3609 spin_unlock_irq(&hdspm->lock);
3610
3611 return 0;
3612 }
3613
3614 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3615 struct snd_ctl_elem_value *ucontrol)
3616 {
3617 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3618 int change;
3619 int source;
3620 int destination;
3621 int gain;
3622
3623 if (!snd_hdspm_use_is_exclusive(hdspm))
3624 return -EBUSY;
3625
3626 source = ucontrol->value.integer.value[0];
3627 destination = ucontrol->value.integer.value[1];
3628
3629 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3630 return -1;
3631 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3632 return -1;
3633
3634 gain = ucontrol->value.integer.value[2];
3635
3636 spin_lock_irq(&hdspm->lock);
3637
3638 if (source >= HDSPM_MAX_CHANNELS)
3639 change = gain != hdspm_read_pb_gain(hdspm, destination,
3640 source -
3641 HDSPM_MAX_CHANNELS);
3642 else
3643 change = gain != hdspm_read_in_gain(hdspm, destination,
3644 source);
3645
3646 if (change) {
3647 if (source >= HDSPM_MAX_CHANNELS)
3648 hdspm_write_pb_gain(hdspm, destination,
3649 source - HDSPM_MAX_CHANNELS,
3650 gain);
3651 else
3652 hdspm_write_in_gain(hdspm, destination, source,
3653 gain);
3654 }
3655 spin_unlock_irq(&hdspm->lock);
3656
3657 return change;
3658 }
3659
3660 /* The simple mixer control(s) provide gain control for the
3661 basic 1:1 mappings of playback streams to output
3662 streams.
3663 */
3664
3665 #define HDSPM_PLAYBACK_MIXER \
3666 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3667 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3668 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3669 .info = snd_hdspm_info_playback_mixer, \
3670 .get = snd_hdspm_get_playback_mixer, \
3671 .put = snd_hdspm_put_playback_mixer \
3672 }
3673
3674 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3675 struct snd_ctl_elem_info *uinfo)
3676 {
3677 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3678 uinfo->count = 1;
3679 uinfo->value.integer.min = 0;
3680 uinfo->value.integer.max = 64;
3681 uinfo->value.integer.step = 1;
3682 return 0;
3683 }
3684
3685 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3686 struct snd_ctl_elem_value *ucontrol)
3687 {
3688 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3689 int channel;
3690
3691 channel = ucontrol->id.index - 1;
3692
3693 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3694 return -EINVAL;
3695
3696 spin_lock_irq(&hdspm->lock);
3697 ucontrol->value.integer.value[0] =
3698 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3699 spin_unlock_irq(&hdspm->lock);
3700
3701 return 0;
3702 }
3703
3704 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3705 struct snd_ctl_elem_value *ucontrol)
3706 {
3707 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3708 int change;
3709 int channel;
3710 int gain;
3711
3712 if (!snd_hdspm_use_is_exclusive(hdspm))
3713 return -EBUSY;
3714
3715 channel = ucontrol->id.index - 1;
3716
3717 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3718 return -EINVAL;
3719
3720 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3721
3722 spin_lock_irq(&hdspm->lock);
3723 change =
3724 gain != hdspm_read_pb_gain(hdspm, channel,
3725 channel);
3726 if (change)
3727 hdspm_write_pb_gain(hdspm, channel, channel,
3728 gain);
3729 spin_unlock_irq(&hdspm->lock);
3730 return change;
3731 }
3732
3733 #define HDSPM_SYNC_CHECK(xname, xindex) \
3734 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3735 .name = xname, \
3736 .private_value = xindex, \
3737 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3738 .info = snd_hdspm_info_sync_check, \
3739 .get = snd_hdspm_get_sync_check \
3740 }
3741
3742
3743 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3744 struct snd_ctl_elem_info *uinfo)
3745 {
3746 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3747 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3748 uinfo->count = 1;
3749 uinfo->value.enumerated.items = 4;
3750 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3751 uinfo->value.enumerated.item =
3752 uinfo->value.enumerated.items - 1;
3753 strcpy(uinfo->value.enumerated.name,
3754 texts[uinfo->value.enumerated.item]);
3755 return 0;
3756 }
3757
3758 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3759 {
3760 int status, status2;
3761
3762 switch (hdspm->io_type) {
3763 case AES32:
3764 status = hdspm_read(hdspm, HDSPM_statusRegister);
3765 if (status & HDSPM_wcSync)
3766 return 2;
3767 else if (status & HDSPM_wcLock)
3768 return 1;
3769 return 0;
3770 break;
3771
3772 case MADI:
3773 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3774 if (status2 & HDSPM_wcLock) {
3775 if (status2 & HDSPM_wcSync)
3776 return 2;
3777 else
3778 return 1;
3779 }
3780 return 0;
3781 break;
3782
3783 case RayDAT:
3784 case AIO:
3785 status = hdspm_read(hdspm, HDSPM_statusRegister);
3786
3787 if (status & 0x2000000)
3788 return 2;
3789 else if (status & 0x1000000)
3790 return 1;
3791 return 0;
3792
3793 break;
3794
3795 case MADIface:
3796 break;
3797 }
3798
3799
3800 return 3;
3801 }
3802
3803
3804 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3805 {
3806 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3807 if (status & HDSPM_madiLock) {
3808 if (status & HDSPM_madiSync)
3809 return 2;
3810 else
3811 return 1;
3812 }
3813 return 0;
3814 }
3815
3816
3817 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3818 {
3819 int status, lock, sync;
3820
3821 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3822
3823 lock = (status & (0x1<<idx)) ? 1 : 0;
3824 sync = (status & (0x100<<idx)) ? 1 : 0;
3825
3826 if (lock && sync)
3827 return 2;
3828 else if (lock)
3829 return 1;
3830 return 0;
3831 }
3832
3833
3834 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3835 {
3836 int status, lock = 0, sync = 0;
3837
3838 switch (hdspm->io_type) {
3839 case RayDAT:
3840 case AIO:
3841 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3842 lock = (status & 0x400) ? 1 : 0;
3843 sync = (status & 0x800) ? 1 : 0;
3844 break;
3845
3846 case MADI:
3847 case AES32:
3848 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3849 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3850 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3851 break;
3852
3853 case MADIface:
3854 break;
3855 }
3856
3857 if (lock && sync)
3858 return 2;
3859 else if (lock)
3860 return 1;
3861
3862 return 0;
3863 }
3864
3865 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3866 {
3867 int status2, lock, sync;
3868 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3869
3870 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3871 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3872
3873 if (sync)
3874 return 2;
3875 else if (lock)
3876 return 1;
3877 return 0;
3878 }
3879
3880
3881 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3882 {
3883 int status;
3884
3885 if (hdspm->tco) {
3886 switch (hdspm->io_type) {
3887 case MADI:
3888 case AES32:
3889 status = hdspm_read(hdspm, HDSPM_statusRegister);
3890 if (status & HDSPM_tcoLock) {
3891 if (status & HDSPM_tcoSync)
3892 return 2;
3893 else
3894 return 1;
3895 }
3896 return 0;
3897
3898 break;
3899
3900 case RayDAT:
3901 case AIO:
3902 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3903
3904 if (status & 0x8000000)
3905 return 2; /* Sync */
3906 if (status & 0x4000000)
3907 return 1; /* Lock */
3908 return 0; /* No signal */
3909 break;
3910
3911 default:
3912 break;
3913 }
3914 }
3915
3916 return 3; /* N/A */
3917 }
3918
3919
3920 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3921 struct snd_ctl_elem_value *ucontrol)
3922 {
3923 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3924 int val = -1;
3925
3926 switch (hdspm->io_type) {
3927 case RayDAT:
3928 switch (kcontrol->private_value) {
3929 case 0: /* WC */
3930 val = hdspm_wc_sync_check(hdspm); break;
3931 case 7: /* TCO */
3932 val = hdspm_tco_sync_check(hdspm); break;
3933 case 8: /* SYNC IN */
3934 val = hdspm_sync_in_sync_check(hdspm); break;
3935 default:
3936 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3937 }
3938
3939 case AIO:
3940 switch (kcontrol->private_value) {
3941 case 0: /* WC */
3942 val = hdspm_wc_sync_check(hdspm); break;
3943 case 4: /* TCO */
3944 val = hdspm_tco_sync_check(hdspm); break;
3945 case 5: /* SYNC IN */
3946 val = hdspm_sync_in_sync_check(hdspm); break;
3947 default:
3948 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3949 }
3950
3951 case MADI:
3952 switch (kcontrol->private_value) {
3953 case 0: /* WC */
3954 val = hdspm_wc_sync_check(hdspm); break;
3955 case 1: /* MADI */
3956 val = hdspm_madi_sync_check(hdspm); break;
3957 case 2: /* TCO */
3958 val = hdspm_tco_sync_check(hdspm); break;
3959 case 3: /* SYNC_IN */
3960 val = hdspm_sync_in_sync_check(hdspm); break;
3961 }
3962
3963 case MADIface:
3964 val = hdspm_madi_sync_check(hdspm); /* MADI */
3965 break;
3966
3967 case AES32:
3968 switch (kcontrol->private_value) {
3969 case 0: /* WC */
3970 val = hdspm_wc_sync_check(hdspm); break;
3971 case 9: /* TCO */
3972 val = hdspm_tco_sync_check(hdspm); break;
3973 case 10 /* SYNC IN */:
3974 val = hdspm_sync_in_sync_check(hdspm); break;
3975 default: /* AES1 to AES8 */
3976 val = hdspm_aes_sync_check(hdspm,
3977 kcontrol->private_value-1);
3978 }
3979
3980 }
3981
3982 if (-1 == val)
3983 val = 3;
3984
3985 ucontrol->value.enumerated.item[0] = val;
3986 return 0;
3987 }
3988
3989
3990
3991 /**
3992 * TCO controls
3993 **/
3994 static void hdspm_tco_write(struct hdspm *hdspm)
3995 {
3996 unsigned int tc[4] = { 0, 0, 0, 0};
3997
3998 switch (hdspm->tco->input) {
3999 case 0:
4000 tc[2] |= HDSPM_TCO2_set_input_MSB;
4001 break;
4002 case 1:
4003 tc[2] |= HDSPM_TCO2_set_input_LSB;
4004 break;
4005 default:
4006 break;
4007 }
4008
4009 switch (hdspm->tco->framerate) {
4010 case 1:
4011 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4012 break;
4013 case 2:
4014 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4015 break;
4016 case 3:
4017 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4018 HDSPM_TCO1_set_drop_frame_flag;
4019 break;
4020 case 4:
4021 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4022 HDSPM_TCO1_LTC_Format_MSB;
4023 break;
4024 case 5:
4025 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4026 HDSPM_TCO1_LTC_Format_MSB +
4027 HDSPM_TCO1_set_drop_frame_flag;
4028 break;
4029 default:
4030 break;
4031 }
4032
4033 switch (hdspm->tco->wordclock) {
4034 case 1:
4035 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4036 break;
4037 case 2:
4038 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4039 break;
4040 default:
4041 break;
4042 }
4043
4044 switch (hdspm->tco->samplerate) {
4045 case 1:
4046 tc[2] |= HDSPM_TCO2_set_freq;
4047 break;
4048 case 2:
4049 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4050 break;
4051 default:
4052 break;
4053 }
4054
4055 switch (hdspm->tco->pull) {
4056 case 1:
4057 tc[2] |= HDSPM_TCO2_set_pull_up;
4058 break;
4059 case 2:
4060 tc[2] |= HDSPM_TCO2_set_pull_down;
4061 break;
4062 case 3:
4063 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4064 break;
4065 case 4:
4066 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4067 break;
4068 default:
4069 break;
4070 }
4071
4072 if (1 == hdspm->tco->term) {
4073 tc[2] |= HDSPM_TCO2_set_term_75R;
4074 }
4075
4076 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4077 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4078 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4079 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4080 }
4081
4082
4083 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4084 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4085 .name = xname, \
4086 .index = xindex, \
4087 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4088 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4089 .info = snd_hdspm_info_tco_sample_rate, \
4090 .get = snd_hdspm_get_tco_sample_rate, \
4091 .put = snd_hdspm_put_tco_sample_rate \
4092 }
4093
4094 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4095 struct snd_ctl_elem_info *uinfo)
4096 {
4097 static char *texts[] = { "44.1 kHz", "48 kHz" };
4098 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4099 uinfo->count = 1;
4100 uinfo->value.enumerated.items = 2;
4101
4102 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4103 uinfo->value.enumerated.item =
4104 uinfo->value.enumerated.items - 1;
4105
4106 strcpy(uinfo->value.enumerated.name,
4107 texts[uinfo->value.enumerated.item]);
4108
4109 return 0;
4110 }
4111
4112 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4113 struct snd_ctl_elem_value *ucontrol)
4114 {
4115 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4116
4117 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4118
4119 return 0;
4120 }
4121
4122 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4123 struct snd_ctl_elem_value *ucontrol)
4124 {
4125 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4126
4127 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4128 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4129
4130 hdspm_tco_write(hdspm);
4131
4132 return 1;
4133 }
4134
4135 return 0;
4136 }
4137
4138
4139 #define HDSPM_TCO_PULL(xname, xindex) \
4140 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4141 .name = xname, \
4142 .index = xindex, \
4143 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4144 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4145 .info = snd_hdspm_info_tco_pull, \
4146 .get = snd_hdspm_get_tco_pull, \
4147 .put = snd_hdspm_put_tco_pull \
4148 }
4149
4150 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4151 struct snd_ctl_elem_info *uinfo)
4152 {
4153 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4154 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4155 uinfo->count = 1;
4156 uinfo->value.enumerated.items = 5;
4157
4158 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4159 uinfo->value.enumerated.item =
4160 uinfo->value.enumerated.items - 1;
4161
4162 strcpy(uinfo->value.enumerated.name,
4163 texts[uinfo->value.enumerated.item]);
4164
4165 return 0;
4166 }
4167
4168 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4169 struct snd_ctl_elem_value *ucontrol)
4170 {
4171 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4172
4173 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4174
4175 return 0;
4176 }
4177
4178 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4179 struct snd_ctl_elem_value *ucontrol)
4180 {
4181 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4182
4183 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4184 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4185
4186 hdspm_tco_write(hdspm);
4187
4188 return 1;
4189 }
4190
4191 return 0;
4192 }
4193
4194 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4195 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4196 .name = xname, \
4197 .index = xindex, \
4198 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4199 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4200 .info = snd_hdspm_info_tco_wck_conversion, \
4201 .get = snd_hdspm_get_tco_wck_conversion, \
4202 .put = snd_hdspm_put_tco_wck_conversion \
4203 }
4204
4205 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4206 struct snd_ctl_elem_info *uinfo)
4207 {
4208 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4209 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4210 uinfo->count = 1;
4211 uinfo->value.enumerated.items = 3;
4212
4213 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4214 uinfo->value.enumerated.item =
4215 uinfo->value.enumerated.items - 1;
4216
4217 strcpy(uinfo->value.enumerated.name,
4218 texts[uinfo->value.enumerated.item]);
4219
4220 return 0;
4221 }
4222
4223 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4224 struct snd_ctl_elem_value *ucontrol)
4225 {
4226 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4227
4228 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4229
4230 return 0;
4231 }
4232
4233 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4234 struct snd_ctl_elem_value *ucontrol)
4235 {
4236 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4237
4238 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4239 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4240
4241 hdspm_tco_write(hdspm);
4242
4243 return 1;
4244 }
4245
4246 return 0;
4247 }
4248
4249
4250 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4251 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4252 .name = xname, \
4253 .index = xindex, \
4254 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4255 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4256 .info = snd_hdspm_info_tco_frame_rate, \
4257 .get = snd_hdspm_get_tco_frame_rate, \
4258 .put = snd_hdspm_put_tco_frame_rate \
4259 }
4260
4261 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4262 struct snd_ctl_elem_info *uinfo)
4263 {
4264 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4265 "29.97 dfps", "30 fps", "30 dfps" };
4266 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4267 uinfo->count = 1;
4268 uinfo->value.enumerated.items = 6;
4269
4270 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4271 uinfo->value.enumerated.item =
4272 uinfo->value.enumerated.items - 1;
4273
4274 strcpy(uinfo->value.enumerated.name,
4275 texts[uinfo->value.enumerated.item]);
4276
4277 return 0;
4278 }
4279
4280 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4281 struct snd_ctl_elem_value *ucontrol)
4282 {
4283 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4284
4285 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4286
4287 return 0;
4288 }
4289
4290 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4291 struct snd_ctl_elem_value *ucontrol)
4292 {
4293 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4294
4295 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4296 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4297
4298 hdspm_tco_write(hdspm);
4299
4300 return 1;
4301 }
4302
4303 return 0;
4304 }
4305
4306
4307 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4308 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4309 .name = xname, \
4310 .index = xindex, \
4311 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4312 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4313 .info = snd_hdspm_info_tco_sync_source, \
4314 .get = snd_hdspm_get_tco_sync_source, \
4315 .put = snd_hdspm_put_tco_sync_source \
4316 }
4317
4318 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4319 struct snd_ctl_elem_info *uinfo)
4320 {
4321 static char *texts[] = { "LTC", "Video", "WCK" };
4322 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4323 uinfo->count = 1;
4324 uinfo->value.enumerated.items = 3;
4325
4326 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4327 uinfo->value.enumerated.item =
4328 uinfo->value.enumerated.items - 1;
4329
4330 strcpy(uinfo->value.enumerated.name,
4331 texts[uinfo->value.enumerated.item]);
4332
4333 return 0;
4334 }
4335
4336 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4337 struct snd_ctl_elem_value *ucontrol)
4338 {
4339 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4340
4341 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4342
4343 return 0;
4344 }
4345
4346 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4347 struct snd_ctl_elem_value *ucontrol)
4348 {
4349 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4350
4351 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4352 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4353
4354 hdspm_tco_write(hdspm);
4355
4356 return 1;
4357 }
4358
4359 return 0;
4360 }
4361
4362
4363 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4364 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4365 .name = xname, \
4366 .index = xindex, \
4367 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4368 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4369 .info = snd_hdspm_info_tco_word_term, \
4370 .get = snd_hdspm_get_tco_word_term, \
4371 .put = snd_hdspm_put_tco_word_term \
4372 }
4373
4374 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4375 struct snd_ctl_elem_info *uinfo)
4376 {
4377 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4378 uinfo->count = 1;
4379 uinfo->value.integer.min = 0;
4380 uinfo->value.integer.max = 1;
4381
4382 return 0;
4383 }
4384
4385
4386 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4387 struct snd_ctl_elem_value *ucontrol)
4388 {
4389 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4390
4391 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4392
4393 return 0;
4394 }
4395
4396
4397 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4398 struct snd_ctl_elem_value *ucontrol)
4399 {
4400 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401
4402 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4403 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4404
4405 hdspm_tco_write(hdspm);
4406
4407 return 1;
4408 }
4409
4410 return 0;
4411 }
4412
4413
4414
4415
4416 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4417 HDSPM_MIXER("Mixer", 0),
4418 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4419 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4420 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4421 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4422 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4423 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4424 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4425 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4426 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4427 HDSPM_LINE_OUT("Line Out", 0),
4428 HDSPM_TX_64("TX 64 channels mode", 0),
4429 HDSPM_C_TMS("Clear Track Marker", 0),
4430 HDSPM_SAFE_MODE("Safe Mode", 0),
4431 HDSPM_INPUT_SELECT("Input Select", 0),
4432 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4433 };
4434
4435
4436 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4437 HDSPM_MIXER("Mixer", 0),
4438 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4439 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4440 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4441 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4442 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4443 HDSPM_TX_64("TX 64 channels mode", 0),
4444 HDSPM_C_TMS("Clear Track Marker", 0),
4445 HDSPM_SAFE_MODE("Safe Mode", 0),
4446 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4447 };
4448
4449 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4450 HDSPM_MIXER("Mixer", 0),
4451 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4452 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4453 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4454 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4455 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4456 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4457 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4458 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4459 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4460 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4461 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4462 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4463 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4464 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4465 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4466 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4467 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4468 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4469
4470 /*
4471 HDSPM_INPUT_SELECT("Input Select", 0),
4472 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4473 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4474 HDSPM_SPDIF_IN("SPDIF In", 0);
4475 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4476 HDSPM_INPUT_LEVEL("Input Level", 0);
4477 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4478 HDSPM_PHONES("Phones", 0);
4479 */
4480 };
4481
4482 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4483 HDSPM_MIXER("Mixer", 0),
4484 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4485 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4486 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4487 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4488 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4489 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4490 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4491 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4492 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4493 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4494 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4495 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4496 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4497 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4498 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4499 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4500 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4501 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4502 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4503 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4504 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4505 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4506 };
4507
4508 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4509 HDSPM_MIXER("Mixer", 0),
4510 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4511 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4512 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4513 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4514 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4515 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4516 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4517 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4518 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4519 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4520 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4521 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4522 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4523 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4524 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4525 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4526 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4527 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4528 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4529 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4530 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4531 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4532 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4533 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4534 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4535 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4536 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4537 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4538 HDSPM_LINE_OUT("Line Out", 0),
4539 HDSPM_EMPHASIS("Emphasis", 0),
4540 HDSPM_DOLBY("Non Audio", 0),
4541 HDSPM_PROFESSIONAL("Professional", 0),
4542 HDSPM_C_TMS("Clear Track Marker", 0),
4543 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4544 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4545 };
4546
4547
4548
4549 /* Control elements for the optional TCO module */
4550 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4551 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4552 HDSPM_TCO_PULL("TCO Pull", 0),
4553 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4554 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4555 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4556 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4557 };
4558
4559
4560 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4561
4562
4563 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4564 {
4565 int i;
4566
4567 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4568 if (hdspm->system_sample_rate > 48000) {
4569 hdspm->playback_mixer_ctls[i]->vd[0].access =
4570 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4571 SNDRV_CTL_ELEM_ACCESS_READ |
4572 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4573 } else {
4574 hdspm->playback_mixer_ctls[i]->vd[0].access =
4575 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4576 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4577 }
4578 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4579 SNDRV_CTL_EVENT_MASK_INFO,
4580 &hdspm->playback_mixer_ctls[i]->id);
4581 }
4582
4583 return 0;
4584 }
4585
4586
4587 static int snd_hdspm_create_controls(struct snd_card *card,
4588 struct hdspm *hdspm)
4589 {
4590 unsigned int idx, limit;
4591 int err;
4592 struct snd_kcontrol *kctl;
4593 struct snd_kcontrol_new *list = NULL;
4594
4595 switch (hdspm->io_type) {
4596 case MADI:
4597 list = snd_hdspm_controls_madi;
4598 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4599 break;
4600 case MADIface:
4601 list = snd_hdspm_controls_madiface;
4602 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4603 break;
4604 case AIO:
4605 list = snd_hdspm_controls_aio;
4606 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4607 break;
4608 case RayDAT:
4609 list = snd_hdspm_controls_raydat;
4610 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4611 break;
4612 case AES32:
4613 list = snd_hdspm_controls_aes32;
4614 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4615 break;
4616 }
4617
4618 if (NULL != list) {
4619 for (idx = 0; idx < limit; idx++) {
4620 err = snd_ctl_add(card,
4621 snd_ctl_new1(&list[idx], hdspm));
4622 if (err < 0)
4623 return err;
4624 }
4625 }
4626
4627
4628 /* create simple 1:1 playback mixer controls */
4629 snd_hdspm_playback_mixer.name = "Chn";
4630 if (hdspm->system_sample_rate >= 128000) {
4631 limit = hdspm->qs_out_channels;
4632 } else if (hdspm->system_sample_rate >= 64000) {
4633 limit = hdspm->ds_out_channels;
4634 } else {
4635 limit = hdspm->ss_out_channels;
4636 }
4637 for (idx = 0; idx < limit; ++idx) {
4638 snd_hdspm_playback_mixer.index = idx + 1;
4639 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4640 err = snd_ctl_add(card, kctl);
4641 if (err < 0)
4642 return err;
4643 hdspm->playback_mixer_ctls[idx] = kctl;
4644 }
4645
4646
4647 if (hdspm->tco) {
4648 /* add tco control elements */
4649 list = snd_hdspm_controls_tco;
4650 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4651 for (idx = 0; idx < limit; idx++) {
4652 err = snd_ctl_add(card,
4653 snd_ctl_new1(&list[idx], hdspm));
4654 if (err < 0)
4655 return err;
4656 }
4657 }
4658
4659 return 0;
4660 }
4661
4662 /*------------------------------------------------------------
4663 /proc interface
4664 ------------------------------------------------------------*/
4665
4666 static void
4667 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4668 struct snd_info_buffer *buffer)
4669 {
4670 struct hdspm *hdspm = entry->private_data;
4671 unsigned int status, status2, control, freq;
4672
4673 char *pref_sync_ref;
4674 char *autosync_ref;
4675 char *system_clock_mode;
4676 char *insel;
4677 int x, x2;
4678
4679 /* TCO stuff */
4680 int a, ltc, frames, seconds, minutes, hours;
4681 unsigned int period;
4682 u64 freq_const = 0;
4683 u32 rate;
4684
4685 status = hdspm_read(hdspm, HDSPM_statusRegister);
4686 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4687 control = hdspm->control_register;
4688 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4689
4690 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4691 hdspm->card_name, hdspm->card->number + 1,
4692 hdspm->firmware_rev,
4693 (status2 & HDSPM_version0) |
4694 (status2 & HDSPM_version1) | (status2 &
4695 HDSPM_version2));
4696
4697 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4698 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4699 hdspm->serial);
4700
4701 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4702 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4703
4704 snd_iprintf(buffer, "--- System ---\n");
4705
4706 snd_iprintf(buffer,
4707 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4708 status & HDSPM_audioIRQPending,
4709 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4710 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4711 hdspm->irq_count);
4712 snd_iprintf(buffer,
4713 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4714 "estimated= %ld (bytes)\n",
4715 ((status & HDSPM_BufferID) ? 1 : 0),
4716 (status & HDSPM_BufferPositionMask),
4717 (status & HDSPM_BufferPositionMask) %
4718 (2 * (int)hdspm->period_bytes),
4719 ((status & HDSPM_BufferPositionMask) - 64) %
4720 (2 * (int)hdspm->period_bytes),
4721 (long) hdspm_hw_pointer(hdspm) * 4);
4722
4723 snd_iprintf(buffer,
4724 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4725 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4726 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4727 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4728 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4729 snd_iprintf(buffer,
4730 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4731 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4732 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4733 snd_iprintf(buffer,
4734 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4735 "status2=0x%x\n",
4736 hdspm->control_register, hdspm->control2_register,
4737 status, status2);
4738 if (status & HDSPM_tco_detect) {
4739 snd_iprintf(buffer, "TCO module detected.\n");
4740 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4741 if (a & HDSPM_TCO1_LTC_Input_valid) {
4742 snd_iprintf(buffer, " LTC valid, ");
4743 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4744 HDSPM_TCO1_LTC_Format_MSB)) {
4745 case 0:
4746 snd_iprintf(buffer, "24 fps, ");
4747 break;
4748 case HDSPM_TCO1_LTC_Format_LSB:
4749 snd_iprintf(buffer, "25 fps, ");
4750 break;
4751 case HDSPM_TCO1_LTC_Format_MSB:
4752 snd_iprintf(buffer, "29.97 fps, ");
4753 break;
4754 default:
4755 snd_iprintf(buffer, "30 fps, ");
4756 break;
4757 }
4758 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4759 snd_iprintf(buffer, "drop frame\n");
4760 } else {
4761 snd_iprintf(buffer, "full frame\n");
4762 }
4763 } else {
4764 snd_iprintf(buffer, " no LTC\n");
4765 }
4766 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4767 snd_iprintf(buffer, " Video: NTSC\n");
4768 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4769 snd_iprintf(buffer, " Video: PAL\n");
4770 } else {
4771 snd_iprintf(buffer, " No video\n");
4772 }
4773 if (a & HDSPM_TCO1_TCO_lock) {
4774 snd_iprintf(buffer, " Sync: lock\n");
4775 } else {
4776 snd_iprintf(buffer, " Sync: no lock\n");
4777 }
4778
4779 switch (hdspm->io_type) {
4780 case MADI:
4781 case AES32:
4782 freq_const = 110069313433624ULL;
4783 break;
4784 case RayDAT:
4785 case AIO:
4786 freq_const = 104857600000000ULL;
4787 break;
4788 case MADIface:
4789 break; /* no TCO possible */
4790 }
4791
4792 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4793 snd_iprintf(buffer, " period: %u\n", period);
4794
4795
4796 /* rate = freq_const/period; */
4797 rate = div_u64(freq_const, period);
4798
4799 if (control & HDSPM_QuadSpeed) {
4800 rate *= 4;
4801 } else if (control & HDSPM_DoubleSpeed) {
4802 rate *= 2;
4803 }
4804
4805 snd_iprintf(buffer, " Frequency: %u Hz\n",
4806 (unsigned int) rate);
4807
4808 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4809 frames = ltc & 0xF;
4810 ltc >>= 4;
4811 frames += (ltc & 0x3) * 10;
4812 ltc >>= 4;
4813 seconds = ltc & 0xF;
4814 ltc >>= 4;
4815 seconds += (ltc & 0x7) * 10;
4816 ltc >>= 4;
4817 minutes = ltc & 0xF;
4818 ltc >>= 4;
4819 minutes += (ltc & 0x7) * 10;
4820 ltc >>= 4;
4821 hours = ltc & 0xF;
4822 ltc >>= 4;
4823 hours += (ltc & 0x3) * 10;
4824 snd_iprintf(buffer,
4825 " LTC In: %02d:%02d:%02d:%02d\n",
4826 hours, minutes, seconds, frames);
4827
4828 } else {
4829 snd_iprintf(buffer, "No TCO module detected.\n");
4830 }
4831
4832 snd_iprintf(buffer, "--- Settings ---\n");
4833
4834 x = hdspm_get_latency(hdspm);
4835
4836 snd_iprintf(buffer,
4837 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4838 x, (unsigned long) hdspm->period_bytes);
4839
4840 snd_iprintf(buffer, "Line out: %s\n",
4841 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4842
4843 switch (hdspm->control_register & HDSPM_InputMask) {
4844 case HDSPM_InputOptical:
4845 insel = "Optical";
4846 break;
4847 case HDSPM_InputCoaxial:
4848 insel = "Coaxial";
4849 break;
4850 default:
4851 insel = "Unkown";
4852 }
4853
4854 snd_iprintf(buffer,
4855 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4856 "Auto Input %s\n",
4857 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4858 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4859 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4860
4861
4862 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4863 system_clock_mode = "AutoSync";
4864 else
4865 system_clock_mode = "Master";
4866 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4867
4868 switch (hdspm_pref_sync_ref(hdspm)) {
4869 case HDSPM_SYNC_FROM_WORD:
4870 pref_sync_ref = "Word Clock";
4871 break;
4872 case HDSPM_SYNC_FROM_MADI:
4873 pref_sync_ref = "MADI Sync";
4874 break;
4875 case HDSPM_SYNC_FROM_TCO:
4876 pref_sync_ref = "TCO";
4877 break;
4878 case HDSPM_SYNC_FROM_SYNC_IN:
4879 pref_sync_ref = "Sync In";
4880 break;
4881 default:
4882 pref_sync_ref = "XXXX Clock";
4883 break;
4884 }
4885 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4886 pref_sync_ref);
4887
4888 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4889 hdspm->system_sample_rate);
4890
4891
4892 snd_iprintf(buffer, "--- Status:\n");
4893
4894 x = status & HDSPM_madiSync;
4895 x2 = status2 & HDSPM_wcSync;
4896
4897 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4898 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4899 "NoLock",
4900 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4901 "NoLock");
4902
4903 switch (hdspm_autosync_ref(hdspm)) {
4904 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4905 autosync_ref = "Sync In";
4906 break;
4907 case HDSPM_AUTOSYNC_FROM_TCO:
4908 autosync_ref = "TCO";
4909 break;
4910 case HDSPM_AUTOSYNC_FROM_WORD:
4911 autosync_ref = "Word Clock";
4912 break;
4913 case HDSPM_AUTOSYNC_FROM_MADI:
4914 autosync_ref = "MADI Sync";
4915 break;
4916 case HDSPM_AUTOSYNC_FROM_NONE:
4917 autosync_ref = "Input not valid";
4918 break;
4919 default:
4920 autosync_ref = "---";
4921 break;
4922 }
4923 snd_iprintf(buffer,
4924 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4925 autosync_ref, hdspm_external_sample_rate(hdspm),
4926 (status & HDSPM_madiFreqMask) >> 22,
4927 (status2 & HDSPM_wcFreqMask) >> 5);
4928
4929 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4930 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4931 (status & HDSPM_RX_64ch) ? "64 channels" :
4932 "56 channels");
4933
4934 snd_iprintf(buffer, "\n");
4935 }
4936
4937 static void
4938 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4939 struct snd_info_buffer *buffer)
4940 {
4941 struct hdspm *hdspm = entry->private_data;
4942 unsigned int status;
4943 unsigned int status2;
4944 unsigned int timecode;
4945 int pref_syncref;
4946 char *autosync_ref;
4947 int x;
4948
4949 status = hdspm_read(hdspm, HDSPM_statusRegister);
4950 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4951 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4952
4953 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4954 hdspm->card_name, hdspm->card->number + 1,
4955 hdspm->firmware_rev);
4956
4957 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4958 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4959
4960 snd_iprintf(buffer, "--- System ---\n");
4961
4962 snd_iprintf(buffer,
4963 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4964 status & HDSPM_audioIRQPending,
4965 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4966 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4967 hdspm->irq_count);
4968 snd_iprintf(buffer,
4969 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4970 "estimated= %ld (bytes)\n",
4971 ((status & HDSPM_BufferID) ? 1 : 0),
4972 (status & HDSPM_BufferPositionMask),
4973 (status & HDSPM_BufferPositionMask) %
4974 (2 * (int)hdspm->period_bytes),
4975 ((status & HDSPM_BufferPositionMask) - 64) %
4976 (2 * (int)hdspm->period_bytes),
4977 (long) hdspm_hw_pointer(hdspm) * 4);
4978
4979 snd_iprintf(buffer,
4980 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4981 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4982 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4983 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4984 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4985 snd_iprintf(buffer,
4986 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4987 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4988 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4989 snd_iprintf(buffer,
4990 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4991 "status2=0x%x\n",
4992 hdspm->control_register, hdspm->control2_register,
4993 status, status2);
4994
4995 snd_iprintf(buffer, "--- Settings ---\n");
4996
4997 x = hdspm_get_latency(hdspm);
4998
4999 snd_iprintf(buffer,
5000 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5001 x, (unsigned long) hdspm->period_bytes);
5002
5003 snd_iprintf(buffer, "Line out: %s\n",
5004 (hdspm->
5005 control_register & HDSPM_LineOut) ? "on " : "off");
5006
5007 snd_iprintf(buffer,
5008 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5009 (hdspm->
5010 control_register & HDSPM_clr_tms) ? "on" : "off",
5011 (hdspm->
5012 control_register & HDSPM_Emphasis) ? "on" : "off",
5013 (hdspm->
5014 control_register & HDSPM_Dolby) ? "on" : "off");
5015
5016
5017 pref_syncref = hdspm_pref_sync_ref(hdspm);
5018 if (pref_syncref == 0)
5019 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5020 else
5021 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5022 pref_syncref);
5023
5024 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5025 hdspm->system_sample_rate);
5026
5027 snd_iprintf(buffer, "Double speed: %s\n",
5028 hdspm->control_register & HDSPM_DS_DoubleWire?
5029 "Double wire" : "Single wire");
5030 snd_iprintf(buffer, "Quad speed: %s\n",
5031 hdspm->control_register & HDSPM_QS_DoubleWire?
5032 "Double wire" :
5033 hdspm->control_register & HDSPM_QS_QuadWire?
5034 "Quad wire" : "Single wire");
5035
5036 snd_iprintf(buffer, "--- Status:\n");
5037
5038 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5039 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
5040 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5041
5042 for (x = 0; x < 8; x++) {
5043 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5044 x+1,
5045 (status2 & (HDSPM_LockAES >> x)) ?
5046 "Sync " : "No Lock",
5047 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5048 }
5049
5050 switch (hdspm_autosync_ref(hdspm)) {
5051 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5052 autosync_ref = "None"; break;
5053 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5054 autosync_ref = "Word Clock"; break;
5055 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5056 autosync_ref = "AES1"; break;
5057 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5058 autosync_ref = "AES2"; break;
5059 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5060 autosync_ref = "AES3"; break;
5061 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5062 autosync_ref = "AES4"; break;
5063 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5064 autosync_ref = "AES5"; break;
5065 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5066 autosync_ref = "AES6"; break;
5067 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5068 autosync_ref = "AES7"; break;
5069 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5070 autosync_ref = "AES8"; break;
5071 default:
5072 autosync_ref = "---"; break;
5073 }
5074 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5075
5076 snd_iprintf(buffer, "\n");
5077 }
5078
5079 static void
5080 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5081 struct snd_info_buffer *buffer)
5082 {
5083 struct hdspm *hdspm = entry->private_data;
5084 unsigned int status1, status2, status3, control, i;
5085 unsigned int lock, sync;
5086
5087 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5088 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5089 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5090
5091 control = hdspm->control_register;
5092
5093 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5094 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5095 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5096
5097
5098 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5099
5100 snd_iprintf(buffer, "Clock mode : %s\n",
5101 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5102 snd_iprintf(buffer, "System frequency: %d Hz\n",
5103 hdspm_get_system_sample_rate(hdspm));
5104
5105 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5106
5107 lock = 0x1;
5108 sync = 0x100;
5109
5110 for (i = 0; i < 8; i++) {
5111 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5112 i,
5113 (status1 & lock) ? 1 : 0,
5114 (status1 & sync) ? 1 : 0,
5115 texts_freq[(status2 >> (i * 4)) & 0xF]);
5116
5117 lock = lock<<1;
5118 sync = sync<<1;
5119 }
5120
5121 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5122 (status1 & 0x1000000) ? 1 : 0,
5123 (status1 & 0x2000000) ? 1 : 0,
5124 texts_freq[(status1 >> 16) & 0xF]);
5125
5126 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5127 (status1 & 0x4000000) ? 1 : 0,
5128 (status1 & 0x8000000) ? 1 : 0,
5129 texts_freq[(status1 >> 20) & 0xF]);
5130
5131 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5132 (status3 & 0x400) ? 1 : 0,
5133 (status3 & 0x800) ? 1 : 0,
5134 texts_freq[(status2 >> 12) & 0xF]);
5135
5136 }
5137
5138 #ifdef CONFIG_SND_DEBUG
5139 static void
5140 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5141 struct snd_info_buffer *buffer)
5142 {
5143 struct hdspm *hdspm = entry->private_data;
5144
5145 int j,i;
5146
5147 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5148 snd_iprintf(buffer, "0x%08X: ", i);
5149 for (j = 0; j < 16; j += 4)
5150 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5151 snd_iprintf(buffer, "\n");
5152 }
5153 }
5154 #endif
5155
5156
5157 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5158 struct snd_info_buffer *buffer)
5159 {
5160 struct hdspm *hdspm = entry->private_data;
5161 int i;
5162
5163 snd_iprintf(buffer, "# generated by hdspm\n");
5164
5165 for (i = 0; i < hdspm->max_channels_in; i++) {
5166 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5167 }
5168 }
5169
5170 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5171 struct snd_info_buffer *buffer)
5172 {
5173 struct hdspm *hdspm = entry->private_data;
5174 int i;
5175
5176 snd_iprintf(buffer, "# generated by hdspm\n");
5177
5178 for (i = 0; i < hdspm->max_channels_out; i++) {
5179 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5180 }
5181 }
5182
5183
5184 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5185 {
5186 struct snd_info_entry *entry;
5187
5188 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5189 switch (hdspm->io_type) {
5190 case AES32:
5191 snd_info_set_text_ops(entry, hdspm,
5192 snd_hdspm_proc_read_aes32);
5193 break;
5194 case MADI:
5195 snd_info_set_text_ops(entry, hdspm,
5196 snd_hdspm_proc_read_madi);
5197 break;
5198 case MADIface:
5199 /* snd_info_set_text_ops(entry, hdspm,
5200 snd_hdspm_proc_read_madiface); */
5201 break;
5202 case RayDAT:
5203 snd_info_set_text_ops(entry, hdspm,
5204 snd_hdspm_proc_read_raydat);
5205 break;
5206 case AIO:
5207 break;
5208 }
5209 }
5210
5211 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5212 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5213 }
5214
5215 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5216 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5217 }
5218
5219 #ifdef CONFIG_SND_DEBUG
5220 /* debug file to read all hdspm registers */
5221 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5222 snd_info_set_text_ops(entry, hdspm,
5223 snd_hdspm_proc_read_debug);
5224 #endif
5225 }
5226
5227 /*------------------------------------------------------------
5228 hdspm intitialize
5229 ------------------------------------------------------------*/
5230
5231 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5232 {
5233 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5234 hold it (e.g. during module initialization).
5235 */
5236
5237 /* set defaults: */
5238
5239 hdspm->settings_register = 0;
5240
5241 switch (hdspm->io_type) {
5242 case MADI:
5243 case MADIface:
5244 hdspm->control_register =
5245 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5246 break;
5247
5248 case RayDAT:
5249 case AIO:
5250 hdspm->settings_register = 0x1 + 0x1000;
5251 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5252 * line_out */
5253 hdspm->control_register =
5254 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5255 break;
5256
5257 case AES32:
5258 hdspm->control_register =
5259 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5260 hdspm_encode_latency(7) | /* latency max=8192samples */
5261 HDSPM_SyncRef0 | /* AES1 is syncclock */
5262 HDSPM_LineOut | /* Analog output in */
5263 HDSPM_Professional; /* Professional mode */
5264 break;
5265 }
5266
5267 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5268
5269 if (AES32 == hdspm->io_type) {
5270 /* No control2 register for AES32 */
5271 #ifdef SNDRV_BIG_ENDIAN
5272 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5273 #else
5274 hdspm->control2_register = 0;
5275 #endif
5276
5277 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5278 }
5279 hdspm_compute_period_size(hdspm);
5280
5281 /* silence everything */
5282
5283 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5284
5285 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5286 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5287 }
5288
5289 /* set a default rate so that the channel map is set up. */
5290 hdspm_set_rate(hdspm, 48000, 1);
5291
5292 return 0;
5293 }
5294
5295
5296 /*------------------------------------------------------------
5297 interrupt
5298 ------------------------------------------------------------*/
5299
5300 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5301 {
5302 struct hdspm *hdspm = (struct hdspm *) dev_id;
5303 unsigned int status;
5304 int i, audio, midi, schedule = 0;
5305 /* cycles_t now; */
5306
5307 status = hdspm_read(hdspm, HDSPM_statusRegister);
5308
5309 audio = status & HDSPM_audioIRQPending;
5310 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5311 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5312
5313 /* now = get_cycles(); */
5314 /**
5315 * LAT_2..LAT_0 period counter (win) counter (mac)
5316 * 6 4096 ~256053425 ~514672358
5317 * 5 2048 ~128024983 ~257373821
5318 * 4 1024 ~64023706 ~128718089
5319 * 3 512 ~32005945 ~64385999
5320 * 2 256 ~16003039 ~32260176
5321 * 1 128 ~7998738 ~16194507
5322 * 0 64 ~3998231 ~8191558
5323 **/
5324 /*
5325 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5326 now-hdspm->last_interrupt, status & 0xFFC0);
5327 hdspm->last_interrupt = now;
5328 */
5329
5330 if (!audio && !midi)
5331 return IRQ_NONE;
5332
5333 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5334 hdspm->irq_count++;
5335
5336
5337 if (audio) {
5338 if (hdspm->capture_substream)
5339 snd_pcm_period_elapsed(hdspm->capture_substream);
5340
5341 if (hdspm->playback_substream)
5342 snd_pcm_period_elapsed(hdspm->playback_substream);
5343 }
5344
5345 if (midi) {
5346 i = 0;
5347 while (i < hdspm->midiPorts) {
5348 if ((hdspm_read(hdspm,
5349 hdspm->midi[i].statusIn) & 0xff) &&
5350 (status & hdspm->midi[i].irq)) {
5351 /* we disable interrupts for this input until
5352 * processing is done
5353 */
5354 hdspm->control_register &= ~hdspm->midi[i].ie;
5355 hdspm_write(hdspm, HDSPM_controlRegister,
5356 hdspm->control_register);
5357 hdspm->midi[i].pending = 1;
5358 schedule = 1;
5359 }
5360
5361 i++;
5362 }
5363
5364 if (schedule)
5365 tasklet_hi_schedule(&hdspm->midi_tasklet);
5366 }
5367
5368 return IRQ_HANDLED;
5369 }
5370
5371 /*------------------------------------------------------------
5372 pcm interface
5373 ------------------------------------------------------------*/
5374
5375
5376 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5377 *substream)
5378 {
5379 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5380 return hdspm_hw_pointer(hdspm);
5381 }
5382
5383
5384 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5385 {
5386 struct snd_pcm_runtime *runtime = substream->runtime;
5387 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5388 struct snd_pcm_substream *other;
5389
5390 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5391 other = hdspm->capture_substream;
5392 else
5393 other = hdspm->playback_substream;
5394
5395 if (hdspm->running)
5396 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5397 else
5398 runtime->status->hw_ptr = 0;
5399 if (other) {
5400 struct snd_pcm_substream *s;
5401 struct snd_pcm_runtime *oruntime = other->runtime;
5402 snd_pcm_group_for_each_entry(s, substream) {
5403 if (s == other) {
5404 oruntime->status->hw_ptr =
5405 runtime->status->hw_ptr;
5406 break;
5407 }
5408 }
5409 }
5410 return 0;
5411 }
5412
5413 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5414 struct snd_pcm_hw_params *params)
5415 {
5416 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5417 int err;
5418 int i;
5419 pid_t this_pid;
5420 pid_t other_pid;
5421
5422 spin_lock_irq(&hdspm->lock);
5423
5424 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5425 this_pid = hdspm->playback_pid;
5426 other_pid = hdspm->capture_pid;
5427 } else {
5428 this_pid = hdspm->capture_pid;
5429 other_pid = hdspm->playback_pid;
5430 }
5431
5432 if (other_pid > 0 && this_pid != other_pid) {
5433
5434 /* The other stream is open, and not by the same
5435 task as this one. Make sure that the parameters
5436 that matter are the same.
5437 */
5438
5439 if (params_rate(params) != hdspm->system_sample_rate) {
5440 spin_unlock_irq(&hdspm->lock);
5441 _snd_pcm_hw_param_setempty(params,
5442 SNDRV_PCM_HW_PARAM_RATE);
5443 return -EBUSY;
5444 }
5445
5446 if (params_period_size(params) != hdspm->period_bytes / 4) {
5447 spin_unlock_irq(&hdspm->lock);
5448 _snd_pcm_hw_param_setempty(params,
5449 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5450 return -EBUSY;
5451 }
5452
5453 }
5454 /* We're fine. */
5455 spin_unlock_irq(&hdspm->lock);
5456
5457 /* how to make sure that the rate matches an externally-set one ? */
5458
5459 spin_lock_irq(&hdspm->lock);
5460 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5461 if (err < 0) {
5462 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5463 spin_unlock_irq(&hdspm->lock);
5464 _snd_pcm_hw_param_setempty(params,
5465 SNDRV_PCM_HW_PARAM_RATE);
5466 return err;
5467 }
5468 spin_unlock_irq(&hdspm->lock);
5469
5470 err = hdspm_set_interrupt_interval(hdspm,
5471 params_period_size(params));
5472 if (err < 0) {
5473 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5474 _snd_pcm_hw_param_setempty(params,
5475 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5476 return err;
5477 }
5478
5479 /* Memory allocation, takashi's method, dont know if we should
5480 * spinlock
5481 */
5482 /* malloc all buffer even if not enabled to get sure */
5483 /* Update for MADI rev 204: we need to allocate for all channels,
5484 * otherwise it doesn't work at 96kHz */
5485
5486 err =
5487 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5488 if (err < 0) {
5489 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5490 return err;
5491 }
5492
5493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5494
5495 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5496 params_channels(params));
5497
5498 for (i = 0; i < params_channels(params); ++i)
5499 snd_hdspm_enable_out(hdspm, i, 1);
5500
5501 hdspm->playback_buffer =
5502 (unsigned char *) substream->runtime->dma_area;
5503 snd_printdd("Allocated sample buffer for playback at %p\n",
5504 hdspm->playback_buffer);
5505 } else {
5506 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5507 params_channels(params));
5508
5509 for (i = 0; i < params_channels(params); ++i)
5510 snd_hdspm_enable_in(hdspm, i, 1);
5511
5512 hdspm->capture_buffer =
5513 (unsigned char *) substream->runtime->dma_area;
5514 snd_printdd("Allocated sample buffer for capture at %p\n",
5515 hdspm->capture_buffer);
5516 }
5517
5518 /*
5519 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5520 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5521 "playback" : "capture",
5522 snd_pcm_sgbuf_get_addr(substream, 0));
5523 */
5524 /*
5525 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5526 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5527 "playback" : "capture",
5528 params_rate(params), params_channels(params),
5529 params_buffer_size(params));
5530 */
5531
5532
5533 /* Switch to native float format if requested */
5534 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5535 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5536 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5537
5538 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5539 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5540 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5541 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5542
5543 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5544 }
5545 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5546
5547 return 0;
5548 }
5549
5550 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5551 {
5552 int i;
5553 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5554
5555 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5556
5557 /* params_channels(params) should be enough,
5558 but to get sure in case of error */
5559 for (i = 0; i < hdspm->max_channels_out; ++i)
5560 snd_hdspm_enable_out(hdspm, i, 0);
5561
5562 hdspm->playback_buffer = NULL;
5563 } else {
5564 for (i = 0; i < hdspm->max_channels_in; ++i)
5565 snd_hdspm_enable_in(hdspm, i, 0);
5566
5567 hdspm->capture_buffer = NULL;
5568
5569 }
5570
5571 snd_pcm_lib_free_pages(substream);
5572
5573 return 0;
5574 }
5575
5576
5577 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5578 struct snd_pcm_channel_info *info)
5579 {
5580 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5581
5582 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5583 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5584 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5585 return -EINVAL;
5586 }
5587
5588 if (hdspm->channel_map_out[info->channel] < 0) {
5589 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5590 return -EINVAL;
5591 }
5592
5593 info->offset = hdspm->channel_map_out[info->channel] *
5594 HDSPM_CHANNEL_BUFFER_BYTES;
5595 } else {
5596 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5597 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5598 return -EINVAL;
5599 }
5600
5601 if (hdspm->channel_map_in[info->channel] < 0) {
5602 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5603 return -EINVAL;
5604 }
5605
5606 info->offset = hdspm->channel_map_in[info->channel] *
5607 HDSPM_CHANNEL_BUFFER_BYTES;
5608 }
5609
5610 info->first = 0;
5611 info->step = 32;
5612 return 0;
5613 }
5614
5615
5616 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5617 unsigned int cmd, void *arg)
5618 {
5619 switch (cmd) {
5620 case SNDRV_PCM_IOCTL1_RESET:
5621 return snd_hdspm_reset(substream);
5622
5623 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5624 {
5625 struct snd_pcm_channel_info *info = arg;
5626 return snd_hdspm_channel_info(substream, info);
5627 }
5628 default:
5629 break;
5630 }
5631
5632 return snd_pcm_lib_ioctl(substream, cmd, arg);
5633 }
5634
5635 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5636 {
5637 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5638 struct snd_pcm_substream *other;
5639 int running;
5640
5641 spin_lock(&hdspm->lock);
5642 running = hdspm->running;
5643 switch (cmd) {
5644 case SNDRV_PCM_TRIGGER_START:
5645 running |= 1 << substream->stream;
5646 break;
5647 case SNDRV_PCM_TRIGGER_STOP:
5648 running &= ~(1 << substream->stream);
5649 break;
5650 default:
5651 snd_BUG();
5652 spin_unlock(&hdspm->lock);
5653 return -EINVAL;
5654 }
5655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5656 other = hdspm->capture_substream;
5657 else
5658 other = hdspm->playback_substream;
5659
5660 if (other) {
5661 struct snd_pcm_substream *s;
5662 snd_pcm_group_for_each_entry(s, substream) {
5663 if (s == other) {
5664 snd_pcm_trigger_done(s, substream);
5665 if (cmd == SNDRV_PCM_TRIGGER_START)
5666 running |= 1 << s->stream;
5667 else
5668 running &= ~(1 << s->stream);
5669 goto _ok;
5670 }
5671 }
5672 if (cmd == SNDRV_PCM_TRIGGER_START) {
5673 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5674 && substream->stream ==
5675 SNDRV_PCM_STREAM_CAPTURE)
5676 hdspm_silence_playback(hdspm);
5677 } else {
5678 if (running &&
5679 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5680 hdspm_silence_playback(hdspm);
5681 }
5682 } else {
5683 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5684 hdspm_silence_playback(hdspm);
5685 }
5686 _ok:
5687 snd_pcm_trigger_done(substream, substream);
5688 if (!hdspm->running && running)
5689 hdspm_start_audio(hdspm);
5690 else if (hdspm->running && !running)
5691 hdspm_stop_audio(hdspm);
5692 hdspm->running = running;
5693 spin_unlock(&hdspm->lock);
5694
5695 return 0;
5696 }
5697
5698 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5699 {
5700 return 0;
5701 }
5702
5703 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5704 .info = (SNDRV_PCM_INFO_MMAP |
5705 SNDRV_PCM_INFO_MMAP_VALID |
5706 SNDRV_PCM_INFO_NONINTERLEAVED |
5707 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5708 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5709 .rates = (SNDRV_PCM_RATE_32000 |
5710 SNDRV_PCM_RATE_44100 |
5711 SNDRV_PCM_RATE_48000 |
5712 SNDRV_PCM_RATE_64000 |
5713 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5714 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5715 .rate_min = 32000,
5716 .rate_max = 192000,
5717 .channels_min = 1,
5718 .channels_max = HDSPM_MAX_CHANNELS,
5719 .buffer_bytes_max =
5720 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5721 .period_bytes_min = (32 * 4),
5722 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5723 .periods_min = 2,
5724 .periods_max = 512,
5725 .fifo_size = 0
5726 };
5727
5728 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5729 .info = (SNDRV_PCM_INFO_MMAP |
5730 SNDRV_PCM_INFO_MMAP_VALID |
5731 SNDRV_PCM_INFO_NONINTERLEAVED |
5732 SNDRV_PCM_INFO_SYNC_START),
5733 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5734 .rates = (SNDRV_PCM_RATE_32000 |
5735 SNDRV_PCM_RATE_44100 |
5736 SNDRV_PCM_RATE_48000 |
5737 SNDRV_PCM_RATE_64000 |
5738 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5739 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5740 .rate_min = 32000,
5741 .rate_max = 192000,
5742 .channels_min = 1,
5743 .channels_max = HDSPM_MAX_CHANNELS,
5744 .buffer_bytes_max =
5745 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5746 .period_bytes_min = (32 * 4),
5747 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5748 .periods_min = 2,
5749 .periods_max = 512,
5750 .fifo_size = 0
5751 };
5752
5753 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5754 struct snd_pcm_hw_rule *rule)
5755 {
5756 struct hdspm *hdspm = rule->private;
5757 struct snd_interval *c =
5758 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5759 struct snd_interval *r =
5760 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5761
5762 if (r->min > 96000 && r->max <= 192000) {
5763 struct snd_interval t = {
5764 .min = hdspm->qs_in_channels,
5765 .max = hdspm->qs_in_channels,
5766 .integer = 1,
5767 };
5768 return snd_interval_refine(c, &t);
5769 } else if (r->min > 48000 && r->max <= 96000) {
5770 struct snd_interval t = {
5771 .min = hdspm->ds_in_channels,
5772 .max = hdspm->ds_in_channels,
5773 .integer = 1,
5774 };
5775 return snd_interval_refine(c, &t);
5776 } else if (r->max < 64000) {
5777 struct snd_interval t = {
5778 .min = hdspm->ss_in_channels,
5779 .max = hdspm->ss_in_channels,
5780 .integer = 1,
5781 };
5782 return snd_interval_refine(c, &t);
5783 }
5784
5785 return 0;
5786 }
5787
5788 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5789 struct snd_pcm_hw_rule * rule)
5790 {
5791 struct hdspm *hdspm = rule->private;
5792 struct snd_interval *c =
5793 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5794 struct snd_interval *r =
5795 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5796
5797 if (r->min > 96000 && r->max <= 192000) {
5798 struct snd_interval t = {
5799 .min = hdspm->qs_out_channels,
5800 .max = hdspm->qs_out_channels,
5801 .integer = 1,
5802 };
5803 return snd_interval_refine(c, &t);
5804 } else if (r->min > 48000 && r->max <= 96000) {
5805 struct snd_interval t = {
5806 .min = hdspm->ds_out_channels,
5807 .max = hdspm->ds_out_channels,
5808 .integer = 1,
5809 };
5810 return snd_interval_refine(c, &t);
5811 } else if (r->max < 64000) {
5812 struct snd_interval t = {
5813 .min = hdspm->ss_out_channels,
5814 .max = hdspm->ss_out_channels,
5815 .integer = 1,
5816 };
5817 return snd_interval_refine(c, &t);
5818 } else {
5819 }
5820 return 0;
5821 }
5822
5823 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5824 struct snd_pcm_hw_rule * rule)
5825 {
5826 struct hdspm *hdspm = rule->private;
5827 struct snd_interval *c =
5828 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5829 struct snd_interval *r =
5830 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5831
5832 if (c->min >= hdspm->ss_in_channels) {
5833 struct snd_interval t = {
5834 .min = 32000,
5835 .max = 48000,
5836 .integer = 1,
5837 };
5838 return snd_interval_refine(r, &t);
5839 } else if (c->max <= hdspm->qs_in_channels) {
5840 struct snd_interval t = {
5841 .min = 128000,
5842 .max = 192000,
5843 .integer = 1,
5844 };
5845 return snd_interval_refine(r, &t);
5846 } else if (c->max <= hdspm->ds_in_channels) {
5847 struct snd_interval t = {
5848 .min = 64000,
5849 .max = 96000,
5850 .integer = 1,
5851 };
5852 return snd_interval_refine(r, &t);
5853 }
5854
5855 return 0;
5856 }
5857 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5858 struct snd_pcm_hw_rule *rule)
5859 {
5860 struct hdspm *hdspm = rule->private;
5861 struct snd_interval *c =
5862 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5863 struct snd_interval *r =
5864 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5865
5866 if (c->min >= hdspm->ss_out_channels) {
5867 struct snd_interval t = {
5868 .min = 32000,
5869 .max = 48000,
5870 .integer = 1,
5871 };
5872 return snd_interval_refine(r, &t);
5873 } else if (c->max <= hdspm->qs_out_channels) {
5874 struct snd_interval t = {
5875 .min = 128000,
5876 .max = 192000,
5877 .integer = 1,
5878 };
5879 return snd_interval_refine(r, &t);
5880 } else if (c->max <= hdspm->ds_out_channels) {
5881 struct snd_interval t = {
5882 .min = 64000,
5883 .max = 96000,
5884 .integer = 1,
5885 };
5886 return snd_interval_refine(r, &t);
5887 }
5888
5889 return 0;
5890 }
5891
5892 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5893 struct snd_pcm_hw_rule *rule)
5894 {
5895 unsigned int list[3];
5896 struct hdspm *hdspm = rule->private;
5897 struct snd_interval *c = hw_param_interval(params,
5898 SNDRV_PCM_HW_PARAM_CHANNELS);
5899
5900 list[0] = hdspm->qs_in_channels;
5901 list[1] = hdspm->ds_in_channels;
5902 list[2] = hdspm->ss_in_channels;
5903 return snd_interval_list(c, 3, list, 0);
5904 }
5905
5906 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5907 struct snd_pcm_hw_rule *rule)
5908 {
5909 unsigned int list[3];
5910 struct hdspm *hdspm = rule->private;
5911 struct snd_interval *c = hw_param_interval(params,
5912 SNDRV_PCM_HW_PARAM_CHANNELS);
5913
5914 list[0] = hdspm->qs_out_channels;
5915 list[1] = hdspm->ds_out_channels;
5916 list[2] = hdspm->ss_out_channels;
5917 return snd_interval_list(c, 3, list, 0);
5918 }
5919
5920
5921 static unsigned int hdspm_aes32_sample_rates[] = {
5922 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5923 };
5924
5925 static struct snd_pcm_hw_constraint_list
5926 hdspm_hw_constraints_aes32_sample_rates = {
5927 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5928 .list = hdspm_aes32_sample_rates,
5929 .mask = 0
5930 };
5931
5932 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5933 {
5934 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5935 struct snd_pcm_runtime *runtime = substream->runtime;
5936
5937 spin_lock_irq(&hdspm->lock);
5938
5939 snd_pcm_set_sync(substream);
5940
5941
5942 runtime->hw = snd_hdspm_playback_subinfo;
5943
5944 if (hdspm->capture_substream == NULL)
5945 hdspm_stop_audio(hdspm);
5946
5947 hdspm->playback_pid = current->pid;
5948 hdspm->playback_substream = substream;
5949
5950 spin_unlock_irq(&hdspm->lock);
5951
5952 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5953 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5954
5955 switch (hdspm->io_type) {
5956 case AIO:
5957 case RayDAT:
5958 snd_pcm_hw_constraint_minmax(runtime,
5959 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5960 32, 4096);
5961 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5962 snd_pcm_hw_constraint_minmax(runtime,
5963 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5964 16384, 16384);
5965 break;
5966
5967 default:
5968 snd_pcm_hw_constraint_minmax(runtime,
5969 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5970 64, 8192);
5971 break;
5972 }
5973
5974 if (AES32 == hdspm->io_type) {
5975 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
5976 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5977 &hdspm_hw_constraints_aes32_sample_rates);
5978 } else {
5979 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5980 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5981 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5982 }
5983
5984 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5985 snd_hdspm_hw_rule_out_channels, hdspm,
5986 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5987
5988 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5989 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5990 SNDRV_PCM_HW_PARAM_RATE, -1);
5991
5992 return 0;
5993 }
5994
5995 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5996 {
5997 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5998
5999 spin_lock_irq(&hdspm->lock);
6000
6001 hdspm->playback_pid = -1;
6002 hdspm->playback_substream = NULL;
6003
6004 spin_unlock_irq(&hdspm->lock);
6005
6006 return 0;
6007 }
6008
6009
6010 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6011 {
6012 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6013 struct snd_pcm_runtime *runtime = substream->runtime;
6014
6015 spin_lock_irq(&hdspm->lock);
6016 snd_pcm_set_sync(substream);
6017 runtime->hw = snd_hdspm_capture_subinfo;
6018
6019 if (hdspm->playback_substream == NULL)
6020 hdspm_stop_audio(hdspm);
6021
6022 hdspm->capture_pid = current->pid;
6023 hdspm->capture_substream = substream;
6024
6025 spin_unlock_irq(&hdspm->lock);
6026
6027 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6028 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6029
6030 switch (hdspm->io_type) {
6031 case AIO:
6032 case RayDAT:
6033 snd_pcm_hw_constraint_minmax(runtime,
6034 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6035 32, 4096);
6036 snd_pcm_hw_constraint_minmax(runtime,
6037 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6038 16384, 16384);
6039 break;
6040
6041 default:
6042 snd_pcm_hw_constraint_minmax(runtime,
6043 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6044 64, 8192);
6045 break;
6046 }
6047
6048 if (AES32 == hdspm->io_type) {
6049 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6050 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6051 &hdspm_hw_constraints_aes32_sample_rates);
6052 } else {
6053 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6054 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6055 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6056 }
6057
6058 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6059 snd_hdspm_hw_rule_in_channels, hdspm,
6060 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6061
6062 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6063 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6064 SNDRV_PCM_HW_PARAM_RATE, -1);
6065
6066 return 0;
6067 }
6068
6069 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6070 {
6071 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6072
6073 spin_lock_irq(&hdspm->lock);
6074
6075 hdspm->capture_pid = -1;
6076 hdspm->capture_substream = NULL;
6077
6078 spin_unlock_irq(&hdspm->lock);
6079 return 0;
6080 }
6081
6082 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6083 {
6084 /* we have nothing to initialize but the call is required */
6085 return 0;
6086 }
6087
6088 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6089 {
6090 u32 val = readl(src);
6091 return copy_to_user(dest, &val, 4);
6092 }
6093
6094 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6095 unsigned int cmd, unsigned long arg)
6096 {
6097 void __user *argp = (void __user *)arg;
6098 struct hdspm *hdspm = hw->private_data;
6099 struct hdspm_mixer_ioctl mixer;
6100 struct hdspm_config info;
6101 struct hdspm_status status;
6102 struct hdspm_version hdspm_version;
6103 struct hdspm_peak_rms *levels;
6104 struct hdspm_ltc ltc;
6105 unsigned int statusregister;
6106 long unsigned int s;
6107 int i = 0;
6108
6109 switch (cmd) {
6110
6111 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6112 levels = &hdspm->peak_rms;
6113 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6114 levels->input_peaks[i] =
6115 readl(hdspm->iobase +
6116 HDSPM_MADI_INPUT_PEAK + i*4);
6117 levels->playback_peaks[i] =
6118 readl(hdspm->iobase +
6119 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6120 levels->output_peaks[i] =
6121 readl(hdspm->iobase +
6122 HDSPM_MADI_OUTPUT_PEAK + i*4);
6123
6124 levels->input_rms[i] =
6125 ((uint64_t) readl(hdspm->iobase +
6126 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6127 (uint64_t) readl(hdspm->iobase +
6128 HDSPM_MADI_INPUT_RMS_L + i*4);
6129 levels->playback_rms[i] =
6130 ((uint64_t)readl(hdspm->iobase +
6131 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6132 (uint64_t)readl(hdspm->iobase +
6133 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6134 levels->output_rms[i] =
6135 ((uint64_t)readl(hdspm->iobase +
6136 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6137 (uint64_t)readl(hdspm->iobase +
6138 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6139 }
6140
6141 if (hdspm->system_sample_rate > 96000) {
6142 levels->speed = qs;
6143 } else if (hdspm->system_sample_rate > 48000) {
6144 levels->speed = ds;
6145 } else {
6146 levels->speed = ss;
6147 }
6148 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6149
6150 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6151 if (0 != s) {
6152 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6153 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6154 */
6155 return -EFAULT;
6156 }
6157 break;
6158
6159 case SNDRV_HDSPM_IOCTL_GET_LTC:
6160 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6161 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6162 if (i & HDSPM_TCO1_LTC_Input_valid) {
6163 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6164 HDSPM_TCO1_LTC_Format_MSB)) {
6165 case 0:
6166 ltc.format = fps_24;
6167 break;
6168 case HDSPM_TCO1_LTC_Format_LSB:
6169 ltc.format = fps_25;
6170 break;
6171 case HDSPM_TCO1_LTC_Format_MSB:
6172 ltc.format = fps_2997;
6173 break;
6174 default:
6175 ltc.format = 30;
6176 break;
6177 }
6178 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6179 ltc.frame = drop_frame;
6180 } else {
6181 ltc.frame = full_frame;
6182 }
6183 } else {
6184 ltc.format = format_invalid;
6185 ltc.frame = frame_invalid;
6186 }
6187 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6188 ltc.input_format = ntsc;
6189 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6190 ltc.input_format = pal;
6191 } else {
6192 ltc.input_format = no_video;
6193 }
6194
6195 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6196 if (0 != s) {
6197 /*
6198 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6199 return -EFAULT;
6200 }
6201
6202 break;
6203
6204 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6205
6206 memset(&info, 0, sizeof(info));
6207 spin_lock_irq(&hdspm->lock);
6208 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6209 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6210
6211 info.system_sample_rate = hdspm->system_sample_rate;
6212 info.autosync_sample_rate =
6213 hdspm_external_sample_rate(hdspm);
6214 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6215 info.clock_source = hdspm_clock_source(hdspm);
6216 info.autosync_ref = hdspm_autosync_ref(hdspm);
6217 info.line_out = hdspm_line_out(hdspm);
6218 info.passthru = 0;
6219 spin_unlock_irq(&hdspm->lock);
6220 if (copy_to_user(argp, &info, sizeof(info)))
6221 return -EFAULT;
6222 break;
6223
6224 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6225 memset(&status, 0, sizeof(status));
6226
6227 status.card_type = hdspm->io_type;
6228
6229 status.autosync_source = hdspm_autosync_ref(hdspm);
6230
6231 status.card_clock = 110069313433624ULL;
6232 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6233
6234 switch (hdspm->io_type) {
6235 case MADI:
6236 case MADIface:
6237 status.card_specific.madi.sync_wc =
6238 hdspm_wc_sync_check(hdspm);
6239 status.card_specific.madi.sync_madi =
6240 hdspm_madi_sync_check(hdspm);
6241 status.card_specific.madi.sync_tco =
6242 hdspm_tco_sync_check(hdspm);
6243 status.card_specific.madi.sync_in =
6244 hdspm_sync_in_sync_check(hdspm);
6245
6246 statusregister =
6247 hdspm_read(hdspm, HDSPM_statusRegister);
6248 status.card_specific.madi.madi_input =
6249 (statusregister & HDSPM_AB_int) ? 1 : 0;
6250 status.card_specific.madi.channel_format =
6251 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6252 /* TODO: Mac driver sets it when f_s>48kHz */
6253 status.card_specific.madi.frame_format = 0;
6254
6255 default:
6256 break;
6257 }
6258
6259 if (copy_to_user(argp, &status, sizeof(status)))
6260 return -EFAULT;
6261
6262
6263 break;
6264
6265 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6266 memset(&hdspm_version, 0, sizeof(hdspm_version));
6267
6268 hdspm_version.card_type = hdspm->io_type;
6269 strncpy(hdspm_version.cardname, hdspm->card_name,
6270 sizeof(hdspm_version.cardname));
6271 hdspm_version.serial = hdspm->serial;
6272 hdspm_version.firmware_rev = hdspm->firmware_rev;
6273 hdspm_version.addons = 0;
6274 if (hdspm->tco)
6275 hdspm_version.addons |= HDSPM_ADDON_TCO;
6276
6277 if (copy_to_user(argp, &hdspm_version,
6278 sizeof(hdspm_version)))
6279 return -EFAULT;
6280 break;
6281
6282 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6283 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6284 return -EFAULT;
6285 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6286 sizeof(struct hdspm_mixer)))
6287 return -EFAULT;
6288 break;
6289
6290 default:
6291 return -EINVAL;
6292 }
6293 return 0;
6294 }
6295
6296 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6297 .open = snd_hdspm_playback_open,
6298 .close = snd_hdspm_playback_release,
6299 .ioctl = snd_hdspm_ioctl,
6300 .hw_params = snd_hdspm_hw_params,
6301 .hw_free = snd_hdspm_hw_free,
6302 .prepare = snd_hdspm_prepare,
6303 .trigger = snd_hdspm_trigger,
6304 .pointer = snd_hdspm_hw_pointer,
6305 .page = snd_pcm_sgbuf_ops_page,
6306 };
6307
6308 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6309 .open = snd_hdspm_capture_open,
6310 .close = snd_hdspm_capture_release,
6311 .ioctl = snd_hdspm_ioctl,
6312 .hw_params = snd_hdspm_hw_params,
6313 .hw_free = snd_hdspm_hw_free,
6314 .prepare = snd_hdspm_prepare,
6315 .trigger = snd_hdspm_trigger,
6316 .pointer = snd_hdspm_hw_pointer,
6317 .page = snd_pcm_sgbuf_ops_page,
6318 };
6319
6320 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6321 struct hdspm * hdspm)
6322 {
6323 struct snd_hwdep *hw;
6324 int err;
6325
6326 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6327 if (err < 0)
6328 return err;
6329
6330 hdspm->hwdep = hw;
6331 hw->private_data = hdspm;
6332 strcpy(hw->name, "HDSPM hwdep interface");
6333
6334 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6335 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6336 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6337 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6338
6339 return 0;
6340 }
6341
6342
6343 /*------------------------------------------------------------
6344 memory interface
6345 ------------------------------------------------------------*/
6346 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6347 {
6348 int err;
6349 struct snd_pcm *pcm;
6350 size_t wanted;
6351
6352 pcm = hdspm->pcm;
6353
6354 wanted = HDSPM_DMA_AREA_BYTES;
6355
6356 err =
6357 snd_pcm_lib_preallocate_pages_for_all(pcm,
6358 SNDRV_DMA_TYPE_DEV_SG,
6359 snd_dma_pci_data(hdspm->pci),
6360 wanted,
6361 wanted);
6362 if (err < 0) {
6363 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6364
6365 return err;
6366 } else
6367 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6368
6369 return 0;
6370 }
6371
6372
6373 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6374 struct snd_pcm_substream *substream,
6375 unsigned int reg, int channels)
6376 {
6377 int i;
6378
6379 /* continuous memory segment */
6380 for (i = 0; i < (channels * 16); i++)
6381 hdspm_write(hdspm, reg + 4 * i,
6382 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6383 }
6384
6385
6386 /* ------------- ALSA Devices ---------------------------- */
6387 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6388 struct hdspm *hdspm)
6389 {
6390 struct snd_pcm *pcm;
6391 int err;
6392
6393 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6394 if (err < 0)
6395 return err;
6396
6397 hdspm->pcm = pcm;
6398 pcm->private_data = hdspm;
6399 strcpy(pcm->name, hdspm->card_name);
6400
6401 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6402 &snd_hdspm_playback_ops);
6403 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6404 &snd_hdspm_capture_ops);
6405
6406 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6407
6408 err = snd_hdspm_preallocate_memory(hdspm);
6409 if (err < 0)
6410 return err;
6411
6412 return 0;
6413 }
6414
6415 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6416 {
6417 int i;
6418
6419 for (i = 0; i < hdspm->midiPorts; i++)
6420 snd_hdspm_flush_midi_input(hdspm, i);
6421 }
6422
6423 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6424 struct hdspm * hdspm)
6425 {
6426 int err, i;
6427
6428 snd_printdd("Create card...\n");
6429 err = snd_hdspm_create_pcm(card, hdspm);
6430 if (err < 0)
6431 return err;
6432
6433 i = 0;
6434 while (i < hdspm->midiPorts) {
6435 err = snd_hdspm_create_midi(card, hdspm, i);
6436 if (err < 0) {
6437 return err;
6438 }
6439 i++;
6440 }
6441
6442 err = snd_hdspm_create_controls(card, hdspm);
6443 if (err < 0)
6444 return err;
6445
6446 err = snd_hdspm_create_hwdep(card, hdspm);
6447 if (err < 0)
6448 return err;
6449
6450 snd_printdd("proc init...\n");
6451 snd_hdspm_proc_init(hdspm);
6452
6453 hdspm->system_sample_rate = -1;
6454 hdspm->last_external_sample_rate = -1;
6455 hdspm->last_internal_sample_rate = -1;
6456 hdspm->playback_pid = -1;
6457 hdspm->capture_pid = -1;
6458 hdspm->capture_substream = NULL;
6459 hdspm->playback_substream = NULL;
6460
6461 snd_printdd("Set defaults...\n");
6462 err = snd_hdspm_set_defaults(hdspm);
6463 if (err < 0)
6464 return err;
6465
6466 snd_printdd("Update mixer controls...\n");
6467 hdspm_update_simple_mixer_controls(hdspm);
6468
6469 snd_printdd("Initializeing complete ???\n");
6470
6471 err = snd_card_register(card);
6472 if (err < 0) {
6473 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6474 return err;
6475 }
6476
6477 snd_printdd("... yes now\n");
6478
6479 return 0;
6480 }
6481
6482 static int __devinit snd_hdspm_create(struct snd_card *card,
6483 struct hdspm *hdspm) {
6484
6485 struct pci_dev *pci = hdspm->pci;
6486 int err;
6487 unsigned long io_extent;
6488
6489 hdspm->irq = -1;
6490 hdspm->card = card;
6491
6492 spin_lock_init(&hdspm->lock);
6493
6494 pci_read_config_word(hdspm->pci,
6495 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6496
6497 strcpy(card->mixername, "Xilinx FPGA");
6498 strcpy(card->driver, "HDSPM");
6499
6500 switch (hdspm->firmware_rev) {
6501 case HDSPM_RAYDAT_REV:
6502 hdspm->io_type = RayDAT;
6503 hdspm->card_name = "RME RayDAT";
6504 hdspm->midiPorts = 2;
6505 break;
6506 case HDSPM_AIO_REV:
6507 hdspm->io_type = AIO;
6508 hdspm->card_name = "RME AIO";
6509 hdspm->midiPorts = 1;
6510 break;
6511 case HDSPM_MADIFACE_REV:
6512 hdspm->io_type = MADIface;
6513 hdspm->card_name = "RME MADIface";
6514 hdspm->midiPorts = 1;
6515 break;
6516 default:
6517 if ((hdspm->firmware_rev == 0xf0) ||
6518 ((hdspm->firmware_rev >= 0xe6) &&
6519 (hdspm->firmware_rev <= 0xea))) {
6520 hdspm->io_type = AES32;
6521 hdspm->card_name = "RME AES32";
6522 hdspm->midiPorts = 2;
6523 } else if ((hdspm->firmware_rev == 0xd2) ||
6524 ((hdspm->firmware_rev >= 0xc8) &&
6525 (hdspm->firmware_rev <= 0xcf))) {
6526 hdspm->io_type = MADI;
6527 hdspm->card_name = "RME MADI";
6528 hdspm->midiPorts = 3;
6529 } else {
6530 snd_printk(KERN_ERR
6531 "HDSPM: unknown firmware revision %x\n",
6532 hdspm->firmware_rev);
6533 return -ENODEV;
6534 }
6535 }
6536
6537 err = pci_enable_device(pci);
6538 if (err < 0)
6539 return err;
6540
6541 pci_set_master(hdspm->pci);
6542
6543 err = pci_request_regions(pci, "hdspm");
6544 if (err < 0)
6545 return err;
6546
6547 hdspm->port = pci_resource_start(pci, 0);
6548 io_extent = pci_resource_len(pci, 0);
6549
6550 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6551 hdspm->port, hdspm->port + io_extent - 1);
6552
6553 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6554 if (!hdspm->iobase) {
6555 snd_printk(KERN_ERR "HDSPM: "
6556 "unable to remap region 0x%lx-0x%lx\n",
6557 hdspm->port, hdspm->port + io_extent - 1);
6558 return -EBUSY;
6559 }
6560 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6561 (unsigned long)hdspm->iobase, hdspm->port,
6562 hdspm->port + io_extent - 1);
6563
6564 if (request_irq(pci->irq, snd_hdspm_interrupt,
6565 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6566 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6567 return -EBUSY;
6568 }
6569
6570 snd_printdd("use IRQ %d\n", pci->irq);
6571
6572 hdspm->irq = pci->irq;
6573
6574 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6575 sizeof(struct hdspm_mixer));
6576 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6577 if (!hdspm->mixer) {
6578 snd_printk(KERN_ERR "HDSPM: "
6579 "unable to kmalloc Mixer memory of %d Bytes\n",
6580 (int)sizeof(struct hdspm_mixer));
6581 return err;
6582 }
6583
6584 hdspm->port_names_in = NULL;
6585 hdspm->port_names_out = NULL;
6586
6587 switch (hdspm->io_type) {
6588 case AES32:
6589 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6590 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6591 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6592
6593 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6594 channel_map_aes32;
6595 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6596 channel_map_aes32;
6597 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6598 channel_map_aes32;
6599 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6600 texts_ports_aes32;
6601 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6602 texts_ports_aes32;
6603 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6604 texts_ports_aes32;
6605
6606 hdspm->max_channels_out = hdspm->max_channels_in =
6607 AES32_CHANNELS;
6608 hdspm->port_names_in = hdspm->port_names_out =
6609 texts_ports_aes32;
6610 hdspm->channel_map_in = hdspm->channel_map_out =
6611 channel_map_aes32;
6612
6613 break;
6614
6615 case MADI:
6616 case MADIface:
6617 hdspm->ss_in_channels = hdspm->ss_out_channels =
6618 MADI_SS_CHANNELS;
6619 hdspm->ds_in_channels = hdspm->ds_out_channels =
6620 MADI_DS_CHANNELS;
6621 hdspm->qs_in_channels = hdspm->qs_out_channels =
6622 MADI_QS_CHANNELS;
6623
6624 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6625 channel_map_unity_ss;
6626 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6627 channel_map_unity_ss;
6628 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6629 channel_map_unity_ss;
6630
6631 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6632 texts_ports_madi;
6633 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6634 texts_ports_madi;
6635 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6636 texts_ports_madi;
6637 break;
6638
6639 case AIO:
6640 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6641 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6642 }
6643
6644 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6645 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6646 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6647 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6648 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6649 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6650
6651 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6652 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6653 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6654
6655 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6656 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6657 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6658
6659 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6660 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6661 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6662 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6663 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6664 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6665
6666 break;
6667
6668 case RayDAT:
6669 hdspm->ss_in_channels = hdspm->ss_out_channels =
6670 RAYDAT_SS_CHANNELS;
6671 hdspm->ds_in_channels = hdspm->ds_out_channels =
6672 RAYDAT_DS_CHANNELS;
6673 hdspm->qs_in_channels = hdspm->qs_out_channels =
6674 RAYDAT_QS_CHANNELS;
6675
6676 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6677 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6678
6679 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6680 channel_map_raydat_ss;
6681 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6682 channel_map_raydat_ds;
6683 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6684 channel_map_raydat_qs;
6685 hdspm->channel_map_in = hdspm->channel_map_out =
6686 channel_map_raydat_ss;
6687
6688 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6689 texts_ports_raydat_ss;
6690 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6691 texts_ports_raydat_ds;
6692 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6693 texts_ports_raydat_qs;
6694
6695
6696 break;
6697
6698 }
6699
6700 /* TCO detection */
6701 switch (hdspm->io_type) {
6702 case AIO:
6703 case RayDAT:
6704 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6705 HDSPM_s2_tco_detect) {
6706 hdspm->midiPorts++;
6707 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6708 GFP_KERNEL);
6709 if (NULL != hdspm->tco) {
6710 hdspm_tco_write(hdspm);
6711 }
6712 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6713 } else {
6714 hdspm->tco = NULL;
6715 }
6716 break;
6717
6718 case MADI:
6719 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6720 hdspm->midiPorts++;
6721 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6722 GFP_KERNEL);
6723 if (NULL != hdspm->tco) {
6724 hdspm_tco_write(hdspm);
6725 }
6726 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6727 } else {
6728 hdspm->tco = NULL;
6729 }
6730 break;
6731
6732 default:
6733 hdspm->tco = NULL;
6734 }
6735
6736 /* texts */
6737 switch (hdspm->io_type) {
6738 case AES32:
6739 if (hdspm->tco) {
6740 hdspm->texts_autosync = texts_autosync_aes_tco;
6741 hdspm->texts_autosync_items = 10;
6742 } else {
6743 hdspm->texts_autosync = texts_autosync_aes;
6744 hdspm->texts_autosync_items = 9;
6745 }
6746 break;
6747
6748 case MADI:
6749 if (hdspm->tco) {
6750 hdspm->texts_autosync = texts_autosync_madi_tco;
6751 hdspm->texts_autosync_items = 4;
6752 } else {
6753 hdspm->texts_autosync = texts_autosync_madi;
6754 hdspm->texts_autosync_items = 3;
6755 }
6756 break;
6757
6758 case MADIface:
6759
6760 break;
6761
6762 case RayDAT:
6763 if (hdspm->tco) {
6764 hdspm->texts_autosync = texts_autosync_raydat_tco;
6765 hdspm->texts_autosync_items = 9;
6766 } else {
6767 hdspm->texts_autosync = texts_autosync_raydat;
6768 hdspm->texts_autosync_items = 8;
6769 }
6770 break;
6771
6772 case AIO:
6773 if (hdspm->tco) {
6774 hdspm->texts_autosync = texts_autosync_aio_tco;
6775 hdspm->texts_autosync_items = 6;
6776 } else {
6777 hdspm->texts_autosync = texts_autosync_aio;
6778 hdspm->texts_autosync_items = 5;
6779 }
6780 break;
6781
6782 }
6783
6784 tasklet_init(&hdspm->midi_tasklet,
6785 hdspm_midi_tasklet, (unsigned long) hdspm);
6786
6787
6788 if (hdspm->io_type != MADIface) {
6789 hdspm->serial = (hdspm_read(hdspm,
6790 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6791 /* id contains either a user-provided value or the default
6792 * NULL. If it's the default, we're safe to
6793 * fill card->id with the serial number.
6794 *
6795 * If the serial number is 0xFFFFFF, then we're dealing with
6796 * an old PCI revision that comes without a sane number. In
6797 * this case, we don't set card->id to avoid collisions
6798 * when running with multiple cards.
6799 */
6800 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6801 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6802 snd_card_set_id(card, card->id);
6803 }
6804 }
6805
6806 snd_printdd("create alsa devices.\n");
6807 err = snd_hdspm_create_alsa_devices(card, hdspm);
6808 if (err < 0)
6809 return err;
6810
6811 snd_hdspm_initialize_midi_flush(hdspm);
6812
6813 return 0;
6814 }
6815
6816
6817 static int snd_hdspm_free(struct hdspm * hdspm)
6818 {
6819
6820 if (hdspm->port) {
6821
6822 /* stop th audio, and cancel all interrupts */
6823 hdspm->control_register &=
6824 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6825 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6826 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6827 hdspm_write(hdspm, HDSPM_controlRegister,
6828 hdspm->control_register);
6829 }
6830
6831 if (hdspm->irq >= 0)
6832 free_irq(hdspm->irq, (void *) hdspm);
6833
6834 kfree(hdspm->mixer);
6835
6836 if (hdspm->iobase)
6837 iounmap(hdspm->iobase);
6838
6839 if (hdspm->port)
6840 pci_release_regions(hdspm->pci);
6841
6842 pci_disable_device(hdspm->pci);
6843 return 0;
6844 }
6845
6846
6847 static void snd_hdspm_card_free(struct snd_card *card)
6848 {
6849 struct hdspm *hdspm = card->private_data;
6850
6851 if (hdspm)
6852 snd_hdspm_free(hdspm);
6853 }
6854
6855
6856 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6857 const struct pci_device_id *pci_id)
6858 {
6859 static int dev;
6860 struct hdspm *hdspm;
6861 struct snd_card *card;
6862 int err;
6863
6864 if (dev >= SNDRV_CARDS)
6865 return -ENODEV;
6866 if (!enable[dev]) {
6867 dev++;
6868 return -ENOENT;
6869 }
6870
6871 err = snd_card_create(index[dev], id[dev],
6872 THIS_MODULE, sizeof(struct hdspm), &card);
6873 if (err < 0)
6874 return err;
6875
6876 hdspm = card->private_data;
6877 card->private_free = snd_hdspm_card_free;
6878 hdspm->dev = dev;
6879 hdspm->pci = pci;
6880
6881 snd_card_set_dev(card, &pci->dev);
6882
6883 err = snd_hdspm_create(card, hdspm);
6884 if (err < 0) {
6885 snd_card_free(card);
6886 return err;
6887 }
6888
6889 if (hdspm->io_type != MADIface) {
6890 sprintf(card->shortname, "%s_%x",
6891 hdspm->card_name,
6892 hdspm->serial);
6893 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6894 hdspm->card_name,
6895 hdspm->serial,
6896 hdspm->port, hdspm->irq);
6897 } else {
6898 sprintf(card->shortname, "%s", hdspm->card_name);
6899 sprintf(card->longname, "%s at 0x%lx, irq %d",
6900 hdspm->card_name, hdspm->port, hdspm->irq);
6901 }
6902
6903 err = snd_card_register(card);
6904 if (err < 0) {
6905 snd_card_free(card);
6906 return err;
6907 }
6908
6909 pci_set_drvdata(pci, card);
6910
6911 dev++;
6912 return 0;
6913 }
6914
6915 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6916 {
6917 snd_card_free(pci_get_drvdata(pci));
6918 pci_set_drvdata(pci, NULL);
6919 }
6920
6921 static struct pci_driver driver = {
6922 .name = KBUILD_MODNAME,
6923 .id_table = snd_hdspm_ids,
6924 .probe = snd_hdspm_probe,
6925 .remove = __devexit_p(snd_hdspm_remove),
6926 };
6927
6928
6929 static int __init alsa_card_hdspm_init(void)
6930 {
6931 return pci_register_driver(&driver);
6932 }
6933
6934 static void __exit alsa_card_hdspm_exit(void)
6935 {
6936 pci_unregister_driver(&driver);
6937 }
6938
6939 module_init(alsa_card_hdspm_init)
6940 module_exit(alsa_card_hdspm_exit)
Linux with added FPC-III support