arch/mips/alchemy/devboards/pb1500/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/gpio.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30
  31 #include <asm/mach-au1x00/au1000.h>
  32 #include <asm/mach-db1x00/bcsr.h>
  33
  34 #include <prom.h>
  35
  36 const char *get_system_type(void)
  37 {
  38         return "Alchemy Pb1500";
  39 }
  40
  41 void __init board_setup(void)
  42 {
  43         u32 pin_func;
  44         u32 sys_freqctrl, sys_clksrc;
  45
  46         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  47                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  48
  49         sys_clksrc = sys_freqctrl = pin_func = 0;
  50         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  51         au_writel(8, SYS_AUXPLL);
  52         alchemy_gpio1_input_enable();
  53         udelay(100);
  54
  55         /* GPIO201 is input for PCMCIA card detect */
  56         /* GPIO203 is input for PCMCIA interrupt request */
  57         alchemy_gpio_direction_input(201);
  58         alchemy_gpio_direction_input(203);
  59
  60 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  61
  62         /* Zero and disable FREQ2 */
  63         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  64         sys_freqctrl &= ~0xFFF00000;
  65         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  66
  67         /* zero and disable USBH/USBD clocks */
  68         sys_clksrc = au_readl(SYS_CLKSRC);
  69         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  70                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  71         au_writel(sys_clksrc, SYS_CLKSRC);
  72
  73         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  74         sys_freqctrl &= ~0xFFF00000;
  75
  76         sys_clksrc = au_readl(SYS_CLKSRC);
  77         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  78                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  79
  80         /* FREQ2 = aux/2 = 48 MHz */
  81         sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
  82         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  83
  84         /*
  85          * Route 48MHz FREQ2 into USB Host and/or Device
  86          */
  87         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  88         au_writel(sys_clksrc, SYS_CLKSRC);
  89
  90         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
  91         /* 2nd USB port is USB host */
  92         pin_func |= SYS_PF_USB;
  93         au_writel(pin_func, SYS_PINFUNC);
  94 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
  95
  96 #ifdef CONFIG_PCI
  97         {
  98                 void __iomem *base =
  99                                 (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
 100                 /* Setup PCI bus controller */
 101                 __raw_writel(0x00003fff, base + PCI_REG_CMEM);
 102                 __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
 103                 __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
 104                 __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
 105                 __raw_writel(0x00003c04, base + PCI_REG_PARAM);
 106                 __raw_writel(0x00000008, base + PCI_REG_MBAR);
 107                 wmb();
 108         }
 109 #endif
 110
 111         /* Enable sys bus clock divider when IDLE state or no bus activity. */
 112         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 113
 114         /* Enable the RTC if not already enabled */
 115         if (!(au_readl(0xac000028) & 0x20)) {
 116                 printk(KERN_INFO "enabling clock ...\n");
 117                 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
 118         }
 119         /* Put the clock in BCD mode */
 120         if (au_readl(0xac00002c) & 0x4) { /* reg B */
 121                 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
 122                 au_sync();
 123         }
 124 }
 125
 126 static int __init pb1500_init_irq(void)
 127 {
 128         irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
 129         irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
 130         irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
 131         irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
 132         irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
 133         irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
 134         irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
 135         irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 136
 137         return 0;
 138 }
 139 arch_initcall(pb1500_init_irq);