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1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
7 Will Deacon <will.deacon@arm.com>
8 Peter Zijlstra <peterz@infradead.org>
10 ==========
11 DISCLAIMER
12 ==========
14 This document is not a specification; it is intentionally (for the sake of
15 brevity) and unintentionally (due to being human) incomplete. This document is
16 meant as a guide to using the various memory barriers provided by Linux, but
17 in case of any doubt (and there are many) please ask. Some doubts may be
18 resolved by referring to the formal memory consistency model and related
19 documentation at tools/memory-model/. Nevertheless, even this memory
20 model should be viewed as the collective opinion of its maintainers rather
21 than as an infallible oracle.
23 To repeat, this document is not a specification of what Linux expects from
24 hardware.
26 The purpose of this document is twofold:
28 (1) to specify the minimum functionality that one can rely on for any
29 particular barrier, and
31 (2) to provide a guide as to how to use the barriers that are available.
33 Note that an architecture can provide more than the minimum requirement
34 for any particular barrier, but if the architecture provides less than
35 that, that architecture is incorrect.
37 Note also that it is possible that a barrier may be a no-op for an
38 architecture because the way that arch works renders an explicit barrier
39 unnecessary in that case.
42 ========
43 CONTENTS
44 ========
46 (*) Abstract memory access model.
48 - Device operations.
49 - Guarantees.
51 (*) What are memory barriers?
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Data dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
59 - Read memory barriers vs load speculation.
60 - Multicopy atomicity.
62 (*) Explicit kernel barriers.
64 - Compiler barrier.
65 - CPU memory barriers.
66 - MMIO write barrier.
68 (*) Implicit kernel memory barriers.
70 - Lock acquisition functions.
71 - Interrupt disabling functions.
72 - Sleep and wake-up functions.
73 - Miscellaneous functions.
75 (*) Inter-CPU acquiring barrier effects.
77 - Acquires vs memory accesses.
78 - Acquires vs I/O accesses.
80 (*) Where are memory barriers needed?
82 - Interprocessor interaction.
83 - Atomic operations.
84 - Accessing devices.
85 - Interrupts.
87 (*) Kernel I/O barrier effects.
89 (*) Assumed minimum execution ordering model.
91 (*) The effects of the cpu cache.
93 - Cache coherency.
94 - Cache coherency vs DMA.
95 - Cache coherency vs MMIO.
97 (*) The things CPUs get up to.
99 - And then there's the Alpha.
100 - Virtual Machine Guests.
102 (*) Example uses.
104 - Circular buffers.
106 (*) References.
109 ============================
110 ABSTRACT MEMORY ACCESS MODEL
111 ============================
113 Consider the following abstract model of the system:
115 : :
116 : :
117 : :
118 +-------+ : +--------+ : +-------+
119 | | : | | : | |
120 | | : | | : | |
121 | CPU 1 |<----->| Memory |<----->| CPU 2 |
122 | | : | | : | |
123 | | : | | : | |
124 +-------+ : +--------+ : +-------+
125 ^ : ^ : ^
126 | : | : |
127 | : | : |
128 | : v : |
129 | : +--------+ : |
130 | : | | : |
131 | : | | : |
132 +---------->| Device |<----------+
133 : | | :
134 : | | :
135 : +--------+ :
136 : :
138 Each CPU executes a program that generates memory access operations. In the
139 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
140 perform the memory operations in any order it likes, provided program causality
141 appears to be maintained. Similarly, the compiler may also arrange the
142 instructions it emits in any order it likes, provided it doesn't affect the
143 apparent operation of the program.
145 So in the above diagram, the effects of the memory operations performed by a
146 CPU are perceived by the rest of the system as the operations cross the
147 interface between the CPU and rest of the system (the dotted lines).
150 For example, consider the following sequence of events:
152 CPU 1 CPU 2
153 =============== ===============
154 { A == 1; B == 2 }
155 A = 3; x = B;
156 B = 4; y = A;
158 The set of accesses as seen by the memory system in the middle can be arranged
159 in 24 different combinations:
161 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
162 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
163 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
164 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
165 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
166 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
167 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
168 STORE B=4, ...
169 ...
171 and can thus result in four different combinations of values:
173 x == 2, y == 1
174 x == 2, y == 3
175 x == 4, y == 1
176 x == 4, y == 3
179 Furthermore, the stores committed by a CPU to the memory system may not be
180 perceived by the loads made by another CPU in the same order as the stores were
181 committed.
184 As a further example, consider this sequence of events:
186 CPU 1 CPU 2
187 =============== ===============
188 { A == 1, B == 2, C == 3, P == &A, Q == &C }
189 B = 4; Q = P;
190 P = &B D = *Q;
192 There is an obvious data dependency here, as the value loaded into D depends on
193 the address retrieved from P by CPU 2. At the end of the sequence, any of the
194 following results are possible:
196 (Q == &A) and (D == 1)
197 (Q == &B) and (D == 2)
198 (Q == &B) and (D == 4)
200 Note that CPU 2 will never try and load C into D because the CPU will load P
201 into Q before issuing the load of *Q.
204 DEVICE OPERATIONS
205 -----------------
207 Some devices present their control interfaces as collections of memory
208 locations, but the order in which the control registers are accessed is very
209 important. For instance, imagine an ethernet card with a set of internal
210 registers that are accessed through an address port register (A) and a data
211 port register (D). To read internal register 5, the following code might then
212 be used:
214 *A = 5;
215 x = *D;
217 but this might show up as either of the following two sequences:
219 STORE *A = 5, x = LOAD *D
220 x = LOAD *D, STORE *A = 5
222 the second of which will almost certainly result in a malfunction, since it set
223 the address _after_ attempting to read the register.
226 GUARANTEES
227 ----------
229 There are some minimal guarantees that may be expected of a CPU:
231 (*) On any given CPU, dependent memory accesses will be issued in order, with
232 respect to itself. This means that for:
234 Q = READ_ONCE(P); D = READ_ONCE(*Q);
236 the CPU will issue the following memory operations:
238 Q = LOAD P, D = LOAD *Q
240 and always in that order. However, on DEC Alpha, READ_ONCE() also
241 emits a memory-barrier instruction, so that a DEC Alpha CPU will
242 instead issue the following memory operations:
244 Q = LOAD P, MEMORY_BARRIER, D = LOAD *Q, MEMORY_BARRIER
246 Whether on DEC Alpha or not, the READ_ONCE() also prevents compiler
247 mischief.
249 (*) Overlapping loads and stores within a particular CPU will appear to be
250 ordered within that CPU. This means that for:
252 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
254 the CPU will only issue the following sequence of memory operations:
256 a = LOAD *X, STORE *X = b
258 And for:
260 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
262 the CPU will only issue:
264 STORE *X = c, d = LOAD *X
266 (Loads and stores overlap if they are targeted at overlapping pieces of
267 memory).
269 And there are a number of things that _must_ or _must_not_ be assumed:
271 (*) It _must_not_ be assumed that the compiler will do what you want
272 with memory references that are not protected by READ_ONCE() and
273 WRITE_ONCE(). Without them, the compiler is within its rights to
274 do all sorts of "creative" transformations, which are covered in
275 the COMPILER BARRIER section.
277 (*) It _must_not_ be assumed that independent loads and stores will be issued
278 in the order given. This means that for:
280 X = *A; Y = *B; *D = Z;
282 we may get any of the following sequences:
284 X = LOAD *A, Y = LOAD *B, STORE *D = Z
285 X = LOAD *A, STORE *D = Z, Y = LOAD *B
286 Y = LOAD *B, X = LOAD *A, STORE *D = Z
287 Y = LOAD *B, STORE *D = Z, X = LOAD *A
288 STORE *D = Z, X = LOAD *A, Y = LOAD *B
289 STORE *D = Z, Y = LOAD *B, X = LOAD *A
291 (*) It _must_ be assumed that overlapping memory accesses may be merged or
292 discarded. This means that for:
294 X = *A; Y = *(A + 4);
296 we may get any one of the following sequences:
298 X = LOAD *A; Y = LOAD *(A + 4);
299 Y = LOAD *(A + 4); X = LOAD *A;
300 {X, Y} = LOAD {*A, *(A + 4) };
302 And for:
304 *A = X; *(A + 4) = Y;
306 we may get any of:
308 STORE *A = X; STORE *(A + 4) = Y;
309 STORE *(A + 4) = Y; STORE *A = X;
310 STORE {*A, *(A + 4) } = {X, Y};
312 And there are anti-guarantees:
314 (*) These guarantees do not apply to bitfields, because compilers often
315 generate code to modify these using non-atomic read-modify-write
316 sequences. Do not attempt to use bitfields to synchronize parallel
317 algorithms.
319 (*) Even in cases where bitfields are protected by locks, all fields
320 in a given bitfield must be protected by one lock. If two fields
321 in a given bitfield are protected by different locks, the compiler's
322 non-atomic read-modify-write sequences can cause an update to one
323 field to corrupt the value of an adjacent field.
325 (*) These guarantees apply only to properly aligned and sized scalar
326 variables. "Properly sized" currently means variables that are
327 the same size as "char", "short", "int" and "long". "Properly
328 aligned" means the natural alignment, thus no constraints for
329 "char", two-byte alignment for "short", four-byte alignment for
330 "int", and either four-byte or eight-byte alignment for "long",
331 on 32-bit and 64-bit systems, respectively. Note that these
332 guarantees were introduced into the C11 standard, so beware when
333 using older pre-C11 compilers (for example, gcc 4.6). The portion
334 of the standard containing this guarantee is Section 3.14, which
335 defines "memory location" as follows:
337 memory location
338 either an object of scalar type, or a maximal sequence
339 of adjacent bit-fields all having nonzero width
341 NOTE 1: Two threads of execution can update and access
342 separate memory locations without interfering with
343 each other.
345 NOTE 2: A bit-field and an adjacent non-bit-field member
346 are in separate memory locations. The same applies
347 to two bit-fields, if one is declared inside a nested
348 structure declaration and the other is not, or if the two
349 are separated by a zero-length bit-field declaration,
350 or if they are separated by a non-bit-field member
351 declaration. It is not safe to concurrently update two
352 bit-fields in the same structure if all members declared
353 between them are also bit-fields, no matter what the
354 sizes of those intervening bit-fields happen to be.
357 =========================
358 WHAT ARE MEMORY BARRIERS?
359 =========================
361 As can be seen above, independent memory operations are effectively performed
362 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
363 What is required is some way of intervening to instruct the compiler and the
364 CPU to restrict the order.
366 Memory barriers are such interventions. They impose a perceived partial
367 ordering over the memory operations on either side of the barrier.
369 Such enforcement is important because the CPUs and other devices in a system
370 can use a variety of tricks to improve performance, including reordering,
371 deferral and combination of memory operations; speculative loads; speculative
372 branch prediction and various types of caching. Memory barriers are used to
373 override or suppress these tricks, allowing the code to sanely control the
374 interaction of multiple CPUs and/or devices.
377 VARIETIES OF MEMORY BARRIER
378 ---------------------------
380 Memory barriers come in four basic varieties:
382 (1) Write (or store) memory barriers.
384 A write memory barrier gives a guarantee that all the STORE operations
385 specified before the barrier will appear to happen before all the STORE
386 operations specified after the barrier with respect to the other
387 components of the system.
389 A write barrier is a partial ordering on stores only; it is not required
390 to have any effect on loads.
392 A CPU can be viewed as committing a sequence of store operations to the
393 memory system as time progresses. All stores _before_ a write barrier
394 will occur _before_ all the stores after the write barrier.
396 [!] Note that write barriers should normally be paired with read or data
397 dependency barriers; see the "SMP barrier pairing" subsection.
400 (2) Data dependency barriers.
402 A data dependency barrier is a weaker form of read barrier. In the case
403 where two loads are performed such that the second depends on the result
404 of the first (eg: the first load retrieves the address to which the second
405 load will be directed), a data dependency barrier would be required to
406 make sure that the target of the second load is updated after the address
407 obtained by the first load is accessed.
409 A data dependency barrier is a partial ordering on interdependent loads
410 only; it is not required to have any effect on stores, independent loads
411 or overlapping loads.
413 As mentioned in (1), the other CPUs in the system can be viewed as
414 committing sequences of stores to the memory system that the CPU being
415 considered can then perceive. A data dependency barrier issued by the CPU
416 under consideration guarantees that for any load preceding it, if that
417 load touches one of a sequence of stores from another CPU, then by the
418 time the barrier completes, the effects of all the stores prior to that
419 touched by the load will be perceptible to any loads issued after the data
420 dependency barrier.
422 See the "Examples of memory barrier sequences" subsection for diagrams
423 showing the ordering constraints.
425 [!] Note that the first load really has to have a _data_ dependency and
426 not a control dependency. If the address for the second load is dependent
427 on the first load, but the dependency is through a conditional rather than
428 actually loading the address itself, then it's a _control_ dependency and
429 a full read barrier or better is required. See the "Control dependencies"
430 subsection for more information.
432 [!] Note that data dependency barriers should normally be paired with
433 write barriers; see the "SMP barrier pairing" subsection.
436 (3) Read (or load) memory barriers.
438 A read barrier is a data dependency barrier plus a guarantee that all the
439 LOAD operations specified before the barrier will appear to happen before
440 all the LOAD operations specified after the barrier with respect to the
441 other components of the system.
443 A read barrier is a partial ordering on loads only; it is not required to
444 have any effect on stores.
446 Read memory barriers imply data dependency barriers, and so can substitute
447 for them.
449 [!] Note that read barriers should normally be paired with write barriers;
450 see the "SMP barrier pairing" subsection.
453 (4) General memory barriers.
455 A general memory barrier gives a guarantee that all the LOAD and STORE
456 operations specified before the barrier will appear to happen before all
457 the LOAD and STORE operations specified after the barrier with respect to
458 the other components of the system.
460 A general memory barrier is a partial ordering over both loads and stores.
462 General memory barriers imply both read and write memory barriers, and so
463 can substitute for either.
466 And a couple of implicit varieties:
468 (5) ACQUIRE operations.
470 This acts as a one-way permeable barrier. It guarantees that all memory
471 operations after the ACQUIRE operation will appear to happen after the
472 ACQUIRE operation with respect to the other components of the system.
473 ACQUIRE operations include LOCK operations and both smp_load_acquire()
474 and smp_cond_load_acquire() operations.
476 Memory operations that occur before an ACQUIRE operation may appear to
477 happen after it completes.
479 An ACQUIRE operation should almost always be paired with a RELEASE
480 operation.
483 (6) RELEASE operations.
485 This also acts as a one-way permeable barrier. It guarantees that all
486 memory operations before the RELEASE operation will appear to happen
487 before the RELEASE operation with respect to the other components of the
488 system. RELEASE operations include UNLOCK operations and
489 smp_store_release() operations.
491 Memory operations that occur after a RELEASE operation may appear to
492 happen before it completes.
494 The use of ACQUIRE and RELEASE operations generally precludes the need
495 for other sorts of memory barrier (but note the exceptions mentioned in
496 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
497 pair is -not- guaranteed to act as a full memory barrier. However, after
498 an ACQUIRE on a given variable, all memory accesses preceding any prior
499 RELEASE on that same variable are guaranteed to be visible. In other
500 words, within a given variable's critical section, all accesses of all
501 previous critical sections for that variable are guaranteed to have
502 completed.
504 This means that ACQUIRE acts as a minimal "acquire" operation and
505 RELEASE acts as a minimal "release" operation.
507 A subset of the atomic operations described in atomic_t.txt have ACQUIRE and
508 RELEASE variants in addition to fully-ordered and relaxed (no barrier
509 semantics) definitions. For compound atomics performing both a load and a
510 store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
511 only to the store portion of the operation.
513 Memory barriers are only required where there's a possibility of interaction
514 between two CPUs or between a CPU and a device. If it can be guaranteed that
515 there won't be any such interaction in any particular piece of code, then
516 memory barriers are unnecessary in that piece of code.
519 Note that these are the _minimum_ guarantees. Different architectures may give
520 more substantial guarantees, but they may _not_ be relied upon outside of arch
521 specific code.
524 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
525 ----------------------------------------------
527 There are certain things that the Linux kernel memory barriers do not guarantee:
529 (*) There is no guarantee that any of the memory accesses specified before a
530 memory barrier will be _complete_ by the completion of a memory barrier
531 instruction; the barrier can be considered to draw a line in that CPU's
532 access queue that accesses of the appropriate type may not cross.
534 (*) There is no guarantee that issuing a memory barrier on one CPU will have
535 any direct effect on another CPU or any other hardware in the system. The
536 indirect effect will be the order in which the second CPU sees the effects
537 of the first CPU's accesses occur, but see the next point:
539 (*) There is no guarantee that a CPU will see the correct order of effects
540 from a second CPU's accesses, even _if_ the second CPU uses a memory
541 barrier, unless the first CPU _also_ uses a matching memory barrier (see
542 the subsection on "SMP Barrier Pairing").
544 (*) There is no guarantee that some intervening piece of off-the-CPU
545 hardware[*] will not reorder the memory accesses. CPU cache coherency
546 mechanisms should propagate the indirect effects of a memory barrier
547 between CPUs, but might not do so in order.
549 [*] For information on bus mastering DMA and coherency please read:
551 Documentation/PCI/pci.txt
552 Documentation/DMA-API-HOWTO.txt
553 Documentation/DMA-API.txt
556 DATA DEPENDENCY BARRIERS (HISTORICAL)
557 -------------------------------------
559 As of v4.15 of the Linux kernel, an smp_read_barrier_depends() was
560 added to READ_ONCE(), which means that about the only people who
561 need to pay attention to this section are those working on DEC Alpha
562 architecture-specific code and those working on READ_ONCE() itself.
563 For those who need it, and for those who are interested in the history,
564 here is the story of data-dependency barriers.
566 The usage requirements of data dependency barriers are a little subtle, and
567 it's not always obvious that they're needed. To illustrate, consider the
568 following sequence of events:
570 CPU 1 CPU 2
571 =============== ===============
572 { A == 1, B == 2, C == 3, P == &A, Q == &C }
573 B = 4;
574 <write barrier>
575 WRITE_ONCE(P, &B)
576 Q = READ_ONCE(P);
577 D = *Q;
579 There's a clear data dependency here, and it would seem that by the end of the
580 sequence, Q must be either &A or &B, and that:
582 (Q == &A) implies (D == 1)
583 (Q == &B) implies (D == 4)
585 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
586 leading to the following situation:
588 (Q == &B) and (D == 2) ????
590 Whilst this may seem like a failure of coherency or causality maintenance, it
591 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
592 Alpha).
594 To deal with this, a data dependency barrier or better must be inserted
595 between the address load and the data load:
597 CPU 1 CPU 2
598 =============== ===============
599 { A == 1, B == 2, C == 3, P == &A, Q == &C }
600 B = 4;
601 <write barrier>
602 WRITE_ONCE(P, &B);
603 Q = READ_ONCE(P);
604 <data dependency barrier>
605 D = *Q;
607 This enforces the occurrence of one of the two implications, and prevents the
608 third possibility from arising.
611 [!] Note that this extremely counterintuitive situation arises most easily on
612 machines with split caches, so that, for example, one cache bank processes
613 even-numbered cache lines and the other bank processes odd-numbered cache
614 lines. The pointer P might be stored in an odd-numbered cache line, and the
615 variable B might be stored in an even-numbered cache line. Then, if the
616 even-numbered bank of the reading CPU's cache is extremely busy while the
617 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
618 but the old value of the variable B (2).
621 A data-dependency barrier is not required to order dependent writes
622 because the CPUs that the Linux kernel supports don't do writes
623 until they are certain (1) that the write will actually happen, (2)
624 of the location of the write, and (3) of the value to be written.
625 But please carefully read the "CONTROL DEPENDENCIES" section and the
626 Documentation/RCU/rcu_dereference.txt file: The compiler can and does
627 break dependencies in a great many highly creative ways.
629 CPU 1 CPU 2
630 =============== ===============
631 { A == 1, B == 2, C = 3, P == &A, Q == &C }
632 B = 4;
633 <write barrier>
634 WRITE_ONCE(P, &B);
635 Q = READ_ONCE(P);
636 WRITE_ONCE(*Q, 5);
638 Therefore, no data-dependency barrier is required to order the read into
639 Q with the store into *Q. In other words, this outcome is prohibited,
640 even without a data-dependency barrier:
642 (Q == &B) && (B == 4)
644 Please note that this pattern should be rare. After all, the whole point
645 of dependency ordering is to -prevent- writes to the data structure, along
646 with the expensive cache misses associated with those writes. This pattern
647 can be used to record rare error conditions and the like, and the CPUs'
648 naturally occurring ordering prevents such records from being lost.
651 Note well that the ordering provided by a data dependency is local to
652 the CPU containing it. See the section on "Multicopy atomicity" for
653 more information.
656 The data dependency barrier is very important to the RCU system,
657 for example. See rcu_assign_pointer() and rcu_dereference() in
658 include/linux/rcupdate.h. This permits the current target of an RCU'd
659 pointer to be replaced with a new modified target, without the replacement
660 target appearing to be incompletely initialised.
662 See also the subsection on "Cache Coherency" for a more thorough example.
665 CONTROL DEPENDENCIES
666 --------------------
668 Control dependencies can be a bit tricky because current compilers do
669 not understand them. The purpose of this section is to help you prevent
670 the compiler's ignorance from breaking your code.
672 A load-load control dependency requires a full read memory barrier, not
673 simply a data dependency barrier to make it work correctly. Consider the
674 following bit of code:
676 q = READ_ONCE(a);
677 if (q) {
678 <data dependency barrier> /* BUG: No data dependency!!! */
679 p = READ_ONCE(b);
680 }
682 This will not have the desired effect because there is no actual data
683 dependency, but rather a control dependency that the CPU may short-circuit
684 by attempting to predict the outcome in advance, so that other CPUs see
685 the load from b as having happened before the load from a. In such a
686 case what's actually required is:
688 q = READ_ONCE(a);
689 if (q) {
690 <read barrier>
691 p = READ_ONCE(b);
692 }
694 However, stores are not speculated. This means that ordering -is- provided
695 for load-store control dependencies, as in the following example:
697 q = READ_ONCE(a);
698 if (q) {
699 WRITE_ONCE(b, 1);
700 }
702 Control dependencies pair normally with other types of barriers.
703 That said, please note that neither READ_ONCE() nor WRITE_ONCE()
704 are optional! Without the READ_ONCE(), the compiler might combine the
705 load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
706 the compiler might combine the store to 'b' with other stores to 'b'.
707 Either can result in highly counterintuitive effects on ordering.
709 Worse yet, if the compiler is able to prove (say) that the value of
710 variable 'a' is always non-zero, it would be well within its rights
711 to optimize the original example by eliminating the "if" statement
712 as follows:
714 q = a;
715 b = 1; /* BUG: Compiler and CPU can both reorder!!! */
717 So don't leave out the READ_ONCE().
719 It is tempting to try to enforce ordering on identical stores on both
720 branches of the "if" statement as follows:
722 q = READ_ONCE(a);
723 if (q) {
724 barrier();
725 WRITE_ONCE(b, 1);
726 do_something();
727 } else {
728 barrier();
729 WRITE_ONCE(b, 1);
730 do_something_else();
731 }
733 Unfortunately, current compilers will transform this as follows at high
734 optimization levels:
736 q = READ_ONCE(a);
737 barrier();
738 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */
739 if (q) {
740 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
741 do_something();
742 } else {
743 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
744 do_something_else();
745 }
747 Now there is no conditional between the load from 'a' and the store to
748 'b', which means that the CPU is within its rights to reorder them:
749 The conditional is absolutely required, and must be present in the
750 assembly code even after all compiler optimizations have been applied.
751 Therefore, if you need ordering in this example, you need explicit
752 memory barriers, for example, smp_store_release():
754 q = READ_ONCE(a);
755 if (q) {
756 smp_store_release(&b, 1);
757 do_something();
758 } else {
759 smp_store_release(&b, 1);
760 do_something_else();
761 }
763 In contrast, without explicit memory barriers, two-legged-if control
764 ordering is guaranteed only when the stores differ, for example:
766 q = READ_ONCE(a);
767 if (q) {
768 WRITE_ONCE(b, 1);
769 do_something();
770 } else {
771 WRITE_ONCE(b, 2);
772 do_something_else();
773 }
775 The initial READ_ONCE() is still required to prevent the compiler from
776 proving the value of 'a'.
778 In addition, you need to be careful what you do with the local variable 'q',
779 otherwise the compiler might be able to guess the value and again remove
780 the needed conditional. For example:
782 q = READ_ONCE(a);
783 if (q % MAX) {
784 WRITE_ONCE(b, 1);
785 do_something();
786 } else {
787 WRITE_ONCE(b, 2);
788 do_something_else();
789 }
791 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
792 equal to zero, in which case the compiler is within its rights to
793 transform the above code into the following:
795 q = READ_ONCE(a);
796 WRITE_ONCE(b, 2);
797 do_something_else();
799 Given this transformation, the CPU is not required to respect the ordering
800 between the load from variable 'a' and the store to variable 'b'. It is
801 tempting to add a barrier(), but this does not help. The conditional
802 is gone, and the barrier won't bring it back. Therefore, if you are
803 relying on this ordering, you should make sure that MAX is greater than
804 one, perhaps as follows:
806 q = READ_ONCE(a);
807 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
808 if (q % MAX) {
809 WRITE_ONCE(b, 1);
810 do_something();
811 } else {
812 WRITE_ONCE(b, 2);
813 do_something_else();
814 }
816 Please note once again that the stores to 'b' differ. If they were
817 identical, as noted earlier, the compiler could pull this store outside
818 of the 'if' statement.
820 You must also be careful not to rely too much on boolean short-circuit
821 evaluation. Consider this example:
823 q = READ_ONCE(a);
824 if (q || 1 > 0)
825 WRITE_ONCE(b, 1);
827 Because the first condition cannot fault and the second condition is
828 always true, the compiler can transform this example as following,
829 defeating control dependency:
831 q = READ_ONCE(a);
832 WRITE_ONCE(b, 1);
834 This example underscores the need to ensure that the compiler cannot
835 out-guess your code. More generally, although READ_ONCE() does force
836 the compiler to actually emit code for a given load, it does not force
837 the compiler to use the results.
839 In addition, control dependencies apply only to the then-clause and
840 else-clause of the if-statement in question. In particular, it does
841 not necessarily apply to code following the if-statement:
843 q = READ_ONCE(a);
844 if (q) {
845 WRITE_ONCE(b, 1);
846 } else {
847 WRITE_ONCE(b, 2);
848 }
849 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */
851 It is tempting to argue that there in fact is ordering because the
852 compiler cannot reorder volatile accesses and also cannot reorder
853 the writes to 'b' with the condition. Unfortunately for this line
854 of reasoning, the compiler might compile the two writes to 'b' as
855 conditional-move instructions, as in this fanciful pseudo-assembly
856 language:
858 ld r1,a
859 cmp r1,$0
860 cmov,ne r4,$1
861 cmov,eq r4,$2
862 st r4,b
863 st $1,c
865 A weakly ordered CPU would have no dependency of any sort between the load
866 from 'a' and the store to 'c'. The control dependencies would extend
867 only to the pair of cmov instructions and the store depending on them.
868 In short, control dependencies apply only to the stores in the then-clause
869 and else-clause of the if-statement in question (including functions
870 invoked by those two clauses), not to code following that if-statement.
873 Note well that the ordering provided by a control dependency is local
874 to the CPU containing it. See the section on "Multicopy atomicity"
875 for more information.
878 In summary:
880 (*) Control dependencies can order prior loads against later stores.
881 However, they do -not- guarantee any other sort of ordering:
882 Not prior loads against later loads, nor prior stores against
883 later anything. If you need these other forms of ordering,
884 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
885 later loads, smp_mb().
887 (*) If both legs of the "if" statement begin with identical stores to
888 the same variable, then those stores must be ordered, either by
889 preceding both of them with smp_mb() or by using smp_store_release()
890 to carry out the stores. Please note that it is -not- sufficient
891 to use barrier() at beginning of each leg of the "if" statement
892 because, as shown by the example above, optimizing compilers can
893 destroy the control dependency while respecting the letter of the
894 barrier() law.
896 (*) Control dependencies require at least one run-time conditional
897 between the prior load and the subsequent store, and this
898 conditional must involve the prior load. If the compiler is able
899 to optimize the conditional away, it will have also optimized
900 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
901 can help to preserve the needed conditional.
903 (*) Control dependencies require that the compiler avoid reordering the
904 dependency into nonexistence. Careful use of READ_ONCE() or
905 atomic{,64}_read() can help to preserve your control dependency.
906 Please see the COMPILER BARRIER section for more information.
908 (*) Control dependencies apply only to the then-clause and else-clause
909 of the if-statement containing the control dependency, including
910 any functions that these two clauses call. Control dependencies
911 do -not- apply to code following the if-statement containing the
912 control dependency.
914 (*) Control dependencies pair normally with other types of barriers.
916 (*) Control dependencies do -not- provide multicopy atomicity. If you
917 need all the CPUs to see a given store at the same time, use smp_mb().
919 (*) Compilers do not understand control dependencies. It is therefore
920 your job to ensure that they do not break your code.
923 SMP BARRIER PAIRING
924 -------------------
926 When dealing with CPU-CPU interactions, certain types of memory barrier should
927 always be paired. A lack of appropriate pairing is almost certainly an error.
929 General barriers pair with each other, though they also pair with most
930 other types of barriers, albeit without multicopy atomicity. An acquire
931 barrier pairs with a release barrier, but both may also pair with other
932 barriers, including of course general barriers. A write barrier pairs
933 with a data dependency barrier, a control dependency, an acquire barrier,
934 a release barrier, a read barrier, or a general barrier. Similarly a
935 read barrier, control dependency, or a data dependency barrier pairs
936 with a write barrier, an acquire barrier, a release barrier, or a
937 general barrier:
939 CPU 1 CPU 2
940 =============== ===============
941 WRITE_ONCE(a, 1);
942 <write barrier>
943 WRITE_ONCE(b, 2); x = READ_ONCE(b);
944 <read barrier>
945 y = READ_ONCE(a);
947 Or:
949 CPU 1 CPU 2
950 =============== ===============================
951 a = 1;
952 <write barrier>
953 WRITE_ONCE(b, &a); x = READ_ONCE(b);
954 <data dependency barrier>
955 y = *x;
957 Or even:
959 CPU 1 CPU 2
960 =============== ===============================
961 r1 = READ_ONCE(y);
962 <general barrier>
963 WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
964 <implicit control dependency>
965 WRITE_ONCE(y, 1);
966 }
968 assert(r1 == 0 || r2 == 0);
970 Basically, the read barrier always has to be there, even though it can be of
971 the "weaker" type.
973 [!] Note that the stores before the write barrier would normally be expected to
974 match the loads after the read barrier or the data dependency barrier, and vice
975 versa:
977 CPU 1 CPU 2
978 =================== ===================
979 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
980 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
981 <write barrier> \ <read barrier>
982 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
983 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
986 EXAMPLES OF MEMORY BARRIER SEQUENCES
987 ------------------------------------
989 Firstly, write barriers act as partial orderings on store operations.
990 Consider the following sequence of events:
992 CPU 1
993 =======================
994 STORE A = 1
995 STORE B = 2
996 STORE C = 3
997 <write barrier>
998 STORE D = 4
999 STORE E = 5
1001 This sequence of events is committed to the memory coherence system in an order
1002 that the rest of the system might perceive as the unordered set of { STORE A,
1003 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
1004 }:
1006 +-------+ : :
1007 | | +------+
1008 | |------>| C=3 | } /\
1009 | | : +------+ }----- \ -----> Events perceptible to
1010 | | : | A=1 | } \/ the rest of the system
1011 | | : +------+ }
1012 | CPU 1 | : | B=2 | }
1013 | | +------+ }
1014 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
1015 | | +------+ } requires all stores prior to the
1016 | | : | E=5 | } barrier to be committed before
1017 | | : +------+ } further stores may take place
1018 | |------>| D=4 | }
1019 | | +------+
1020 +-------+ : :
1021 |
1022 | Sequence in which stores are committed to the
1023 | memory system by CPU 1
1024 V
1027 Secondly, data dependency barriers act as partial orderings on data-dependent
1028 loads. Consider the following sequence of events:
1030 CPU 1 CPU 2
1031 ======================= =======================
1032 { B = 7; X = 9; Y = 8; C = &Y }
1033 STORE A = 1
1034 STORE B = 2
1035 <write barrier>
1036 STORE C = &B LOAD X
1037 STORE D = 4 LOAD C (gets &B)
1038 LOAD *C (reads B)
1040 Without intervention, CPU 2 may perceive the events on CPU 1 in some
1041 effectively random order, despite the write barrier issued by CPU 1:
1043 +-------+ : : : :
1044 | | +------+ +-------+ | Sequence of update
1045 | |------>| B=2 |----- --->| Y->8 | | of perception on
1046 | | : +------+ \ +-------+ | CPU 2
1047 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1048 | | +------+ | +-------+
1049 | | wwwwwwwwwwwwwwww | : :
1050 | | +------+ | : :
1051 | | : | C=&B |--- | : : +-------+
1052 | | : +------+ \ | +-------+ | |
1053 | |------>| D=4 | ----------->| C->&B |------>| |
1054 | | +------+ | +-------+ | |
1055 +-------+ : : | : : | |
1056 | : : | |
1057 | : : | CPU 2 |
1058 | +-------+ | |
1059 Apparently incorrect ---> | | B->7 |------>| |
1060 perception of B (!) | +-------+ | |
1061 | : : | |
1062 | +-------+ | |
1063 The load of X holds ---> \ | X->9 |------>| |
1064 up the maintenance \ +-------+ | |
1065 of coherence of B ----->| B->2 | +-------+
1066 +-------+
1067 : :
1070 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1071 (which would be B) coming after the LOAD of C.
1073 If, however, a data dependency barrier were to be placed between the load of C
1074 and the load of *C (ie: B) on CPU 2:
1076 CPU 1 CPU 2
1077 ======================= =======================
1078 { B = 7; X = 9; Y = 8; C = &Y }
1079 STORE A = 1
1080 STORE B = 2
1081 <write barrier>
1082 STORE C = &B LOAD X
1083 STORE D = 4 LOAD C (gets &B)
1084 <data dependency barrier>
1085 LOAD *C (reads B)
1087 then the following will occur:
1089 +-------+ : : : :
1090 | | +------+ +-------+
1091 | |------>| B=2 |----- --->| Y->8 |
1092 | | : +------+ \ +-------+
1093 | CPU 1 | : | A=1 | \ --->| C->&Y |
1094 | | +------+ | +-------+
1095 | | wwwwwwwwwwwwwwww | : :
1096 | | +------+ | : :
1097 | | : | C=&B |--- | : : +-------+
1098 | | : +------+ \ | +-------+ | |
1099 | |------>| D=4 | ----------->| C->&B |------>| |
1100 | | +------+ | +-------+ | |
1101 +-------+ : : | : : | |
1102 | : : | |
1103 | : : | CPU 2 |
1104 | +-------+ | |
1105 | | X->9 |------>| |
1106 | +-------+ | |
1107 Makes sure all effects ---> \ ddddddddddddddddd | |
1108 prior to the store of C \ +-------+ | |
1109 are perceptible to ----->| B->2 |------>| |
1110 subsequent loads +-------+ | |
1111 : : +-------+
1114 And thirdly, a read barrier acts as a partial order on loads. Consider the
1115 following sequence of events:
1117 CPU 1 CPU 2
1118 ======================= =======================
1119 { A = 0, B = 9 }
1120 STORE A=1
1121 <write barrier>
1122 STORE B=2
1123 LOAD B
1124 LOAD A
1126 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1127 some effectively random order, despite the write barrier issued by CPU 1:
1129 +-------+ : : : :
1130 | | +------+ +-------+
1131 | |------>| A=1 |------ --->| A->0 |
1132 | | +------+ \ +-------+
1133 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1134 | | +------+ | +-------+
1135 | |------>| B=2 |--- | : :
1136 | | +------+ \ | : : +-------+
1137 +-------+ : : \ | +-------+ | |
1138 ---------->| B->2 |------>| |
1139 | +-------+ | CPU 2 |
1140 | | A->0 |------>| |
1141 | +-------+ | |
1142 | : : +-------+
1143 \ : :
1144 \ +-------+
1145 ---->| A->1 |
1146 +-------+
1147 : :
1150 If, however, a read barrier were to be placed between the load of B and the
1151 load of A on CPU 2:
1153 CPU 1 CPU 2
1154 ======================= =======================
1155 { A = 0, B = 9 }
1156 STORE A=1
1157 <write barrier>
1158 STORE B=2
1159 LOAD B
1160 <read barrier>
1161 LOAD A
1163 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1164 2:
1166 +-------+ : : : :
1167 | | +------+ +-------+
1168 | |------>| A=1 |------ --->| A->0 |
1169 | | +------+ \ +-------+
1170 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1171 | | +------+ | +-------+
1172 | |------>| B=2 |--- | : :
1173 | | +------+ \ | : : +-------+
1174 +-------+ : : \ | +-------+ | |
1175 ---------->| B->2 |------>| |
1176 | +-------+ | CPU 2 |
1177 | : : | |
1178 | : : | |
1179 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1180 barrier causes all effects \ +-------+ | |
1181 prior to the storage of B ---->| A->1 |------>| |
1182 to be perceptible to CPU 2 +-------+ | |
1183 : : +-------+
1186 To illustrate this more completely, consider what could happen if the code
1187 contained a load of A either side of the read barrier:
1189 CPU 1 CPU 2
1190 ======================= =======================
1191 { A = 0, B = 9 }
1192 STORE A=1
1193 <write barrier>
1194 STORE B=2
1195 LOAD B
1196 LOAD A [first load of A]
1197 <read barrier>
1198 LOAD A [second load of A]
1200 Even though the two loads of A both occur after the load of B, they may both
1201 come up with different values:
1203 +-------+ : : : :
1204 | | +------+ +-------+
1205 | |------>| A=1 |------ --->| A->0 |
1206 | | +------+ \ +-------+
1207 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1208 | | +------+ | +-------+
1209 | |------>| B=2 |--- | : :
1210 | | +------+ \ | : : +-------+
1211 +-------+ : : \ | +-------+ | |
1212 ---------->| B->2 |------>| |
1213 | +-------+ | CPU 2 |
1214 | : : | |
1215 | : : | |
1216 | +-------+ | |
1217 | | A->0 |------>| 1st |
1218 | +-------+ | |
1219 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1220 barrier causes all effects \ +-------+ | |
1221 prior to the storage of B ---->| A->1 |------>| 2nd |
1222 to be perceptible to CPU 2 +-------+ | |
1223 : : +-------+
1226 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1227 before the read barrier completes anyway:
1229 +-------+ : : : :
1230 | | +------+ +-------+
1231 | |------>| A=1 |------ --->| A->0 |
1232 | | +------+ \ +-------+
1233 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1234 | | +------+ | +-------+
1235 | |------>| B=2 |--- | : :
1236 | | +------+ \ | : : +-------+
1237 +-------+ : : \ | +-------+ | |
1238 ---------->| B->2 |------>| |
1239 | +-------+ | CPU 2 |
1240 | : : | |
1241 \ : : | |
1242 \ +-------+ | |
1243 ---->| A->1 |------>| 1st |
1244 +-------+ | |
1245 rrrrrrrrrrrrrrrrr | |
1246 +-------+ | |
1247 | A->1 |------>| 2nd |
1248 +-------+ | |
1249 : : +-------+
1252 The guarantee is that the second load will always come up with A == 1 if the
1253 load of B came up with B == 2. No such guarantee exists for the first load of
1254 A; that may come up with either A == 0 or A == 1.
1257 READ MEMORY BARRIERS VS LOAD SPECULATION
1258 ----------------------------------------
1260 Many CPUs speculate with loads: that is they see that they will need to load an
1261 item from memory, and they find a time where they're not using the bus for any
1262 other loads, and so do the load in advance - even though they haven't actually
1263 got to that point in the instruction execution flow yet. This permits the
1264 actual load instruction to potentially complete immediately because the CPU
1265 already has the value to hand.
1267 It may turn out that the CPU didn't actually need the value - perhaps because a
1268 branch circumvented the load - in which case it can discard the value or just
1269 cache it for later use.
1271 Consider:
1273 CPU 1 CPU 2
1274 ======================= =======================
1275 LOAD B
1276 DIVIDE } Divide instructions generally
1277 DIVIDE } take a long time to perform
1278 LOAD A
1280 Which might appear as this:
1282 : : +-------+
1283 +-------+ | |
1284 --->| B->2 |------>| |
1285 +-------+ | CPU 2 |
1286 : :DIVIDE | |
1287 +-------+ | |
1288 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1289 division speculates on the +-------+ ~ | |
1290 LOAD of A : : ~ | |
1291 : :DIVIDE | |
1292 : : ~ | |
1293 Once the divisions are complete --> : : ~-->| |
1294 the CPU can then perform the : : | |
1295 LOAD with immediate effect : : +-------+
1298 Placing a read barrier or a data dependency barrier just before the second
1299 load:
1301 CPU 1 CPU 2
1302 ======================= =======================
1303 LOAD B
1304 DIVIDE
1305 DIVIDE
1306 <read barrier>
1307 LOAD A
1309 will force any value speculatively obtained to be reconsidered to an extent
1310 dependent on the type of barrier used. If there was no change made to the
1311 speculated memory location, then the speculated value will just be used:
1313 : : +-------+
1314 +-------+ | |
1315 --->| B->2 |------>| |
1316 +-------+ | CPU 2 |
1317 : :DIVIDE | |
1318 +-------+ | |
1319 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1320 division speculates on the +-------+ ~ | |
1321 LOAD of A : : ~ | |
1322 : :DIVIDE | |
1323 : : ~ | |
1324 : : ~ | |
1325 rrrrrrrrrrrrrrrr~ | |
1326 : : ~ | |
1327 : : ~-->| |
1328 : : | |
1329 : : +-------+
1332 but if there was an update or an invalidation from another CPU pending, then
1333 the speculation will be cancelled and the value reloaded:
1335 : : +-------+
1336 +-------+ | |
1337 --->| B->2 |------>| |
1338 +-------+ | CPU 2 |
1339 : :DIVIDE | |
1340 +-------+ | |
1341 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1342 division speculates on the +-------+ ~ | |
1343 LOAD of A : : ~ | |
1344 : :DIVIDE | |
1345 : : ~ | |
1346 : : ~ | |
1347 rrrrrrrrrrrrrrrrr | |
1348 +-------+ | |
1349 The speculation is discarded ---> --->| A->1 |------>| |
1350 and an updated value is +-------+ | |
1351 retrieved : : +-------+
1354 MULTICOPY ATOMICITY
1355 --------------------
1357 Multicopy atomicity is a deeply intuitive notion about ordering that is
1358 not always provided by real computer systems, namely that a given store
1359 becomes visible at the same time to all CPUs, or, alternatively, that all
1360 CPUs agree on the order in which all stores become visible. However,
1361 support of full multicopy atomicity would rule out valuable hardware
1362 optimizations, so a weaker form called ``other multicopy atomicity''
1363 instead guarantees only that a given store becomes visible at the same
1364 time to all -other- CPUs. The remainder of this document discusses this
1365 weaker form, but for brevity will call it simply ``multicopy atomicity''.
1367 The following example demonstrates multicopy atomicity:
1369 CPU 1 CPU 2 CPU 3
1370 ======================= ======================= =======================
1371 { X = 0, Y = 0 }
1372 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1373 <general barrier> <read barrier>
1374 STORE Y=r1 LOAD X
1376 Suppose that CPU 2's load from X returns 1, which it then stores to Y,
1377 and CPU 3's load from Y returns 1. This indicates that CPU 1's store
1378 to X precedes CPU 2's load from X and that CPU 2's store to Y precedes
1379 CPU 3's load from Y. In addition, the memory barriers guarantee that
1380 CPU 2 executes its load before its store, and CPU 3 loads from Y before
1381 it loads from X. The question is then "Can CPU 3's load from X return 0?"
1383 Because CPU 3's load from X in some sense comes after CPU 2's load, it
1384 is natural to expect that CPU 3's load from X must therefore return 1.
1385 This expectation follows from multicopy atomicity: if a load executing
1386 on CPU B follows a load from the same variable executing on CPU A (and
1387 CPU A did not originally store the value which it read), then on
1388 multicopy-atomic systems, CPU B's load must return either the same value
1389 that CPU A's load did or some later value. However, the Linux kernel
1390 does not require systems to be multicopy atomic.
1392 The use of a general memory barrier in the example above compensates
1393 for any lack of multicopy atomicity. In the example, if CPU 2's load
1394 from X returns 1 and CPU 3's load from Y returns 1, then CPU 3's load
1395 from X must indeed also return 1.
1397 However, dependencies, read barriers, and write barriers are not always
1398 able to compensate for non-multicopy atomicity. For example, suppose
1399 that CPU 2's general barrier is removed from the above example, leaving
1400 only the data dependency shown below:
1402 CPU 1 CPU 2 CPU 3
1403 ======================= ======================= =======================
1404 { X = 0, Y = 0 }
1405 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1406 <data dependency> <read barrier>
1407 STORE Y=r1 LOAD X (reads 0)
1409 This substitution allows non-multicopy atomicity to run rampant: in
1410 this example, it is perfectly legal for CPU 2's load from X to return 1,
1411 CPU 3's load from Y to return 1, and its load from X to return 0.
1413 The key point is that although CPU 2's data dependency orders its load
1414 and store, it does not guarantee to order CPU 1's store. Thus, if this
1415 example runs on a non-multicopy-atomic system where CPUs 1 and 2 share a
1416 store buffer or a level of cache, CPU 2 might have early access to CPU 1's
1417 writes. General barriers are therefore required to ensure that all CPUs
1418 agree on the combined order of multiple accesses.
1420 General barriers can compensate not only for non-multicopy atomicity,
1421 but can also generate additional ordering that can ensure that -all-
1422 CPUs will perceive the same order of -all- operations. In contrast, a
1423 chain of release-acquire pairs do not provide this additional ordering,
1424 which means that only those CPUs on the chain are guaranteed to agree
1425 on the combined order of the accesses. For example, switching to C code
1426 in deference to the ghost of Herman Hollerith:
1428 int u, v, x, y, z;
1430 void cpu0(void)
1431 {
1432 r0 = smp_load_acquire(&x);
1433 WRITE_ONCE(u, 1);
1434 smp_store_release(&y, 1);
1435 }
1437 void cpu1(void)
1438 {
1439 r1 = smp_load_acquire(&y);
1440 r4 = READ_ONCE(v);
1441 r5 = READ_ONCE(u);
1442 smp_store_release(&z, 1);
1443 }
1445 void cpu2(void)
1446 {
1447 r2 = smp_load_acquire(&z);
1448 smp_store_release(&x, 1);
1449 }
1451 void cpu3(void)
1452 {
1453 WRITE_ONCE(v, 1);
1454 smp_mb();
1455 r3 = READ_ONCE(u);
1456 }
1458 Because cpu0(), cpu1(), and cpu2() participate in a chain of
1459 smp_store_release()/smp_load_acquire() pairs, the following outcome
1460 is prohibited:
1462 r0 == 1 && r1 == 1 && r2 == 1
1464 Furthermore, because of the release-acquire relationship between cpu0()
1465 and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1466 outcome is prohibited:
1468 r1 == 1 && r5 == 0
1470 However, the ordering provided by a release-acquire chain is local
1471 to the CPUs participating in that chain and does not apply to cpu3(),
1472 at least aside from stores. Therefore, the following outcome is possible:
1474 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1476 As an aside, the following outcome is also possible:
1478 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1480 Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1481 writes in order, CPUs not involved in the release-acquire chain might
1482 well disagree on the order. This disagreement stems from the fact that
1483 the weak memory-barrier instructions used to implement smp_load_acquire()
1484 and smp_store_release() are not required to order prior stores against
1485 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1486 store to u as happening -after- cpu1()'s load from v, even though
1487 both cpu0() and cpu1() agree that these two operations occurred in the
1488 intended order.
1490 However, please keep in mind that smp_load_acquire() is not magic.
1491 In particular, it simply reads from its argument with ordering. It does
1492 -not- ensure that any particular value will be read. Therefore, the
1493 following outcome is possible:
1495 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1497 Note that this outcome can happen even on a mythical sequentially
1498 consistent system where nothing is ever reordered.
1500 To reiterate, if your code requires full ordering of all operations,
1501 use general barriers throughout.
1504 ========================
1505 EXPLICIT KERNEL BARRIERS
1506 ========================
1508 The Linux kernel has a variety of different barriers that act at different
1509 levels:
1511 (*) Compiler barrier.
1513 (*) CPU memory barriers.
1515 (*) MMIO write barrier.
1518 COMPILER BARRIER
1519 ----------------
1521 The Linux kernel has an explicit compiler barrier function that prevents the
1522 compiler from moving the memory accesses either side of it to the other side:
1524 barrier();
1526 This is a general barrier -- there are no read-read or write-write
1527 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1528 thought of as weak forms of barrier() that affect only the specific
1529 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1531 The barrier() function has the following effects:
1533 (*) Prevents the compiler from reordering accesses following the
1534 barrier() to precede any accesses preceding the barrier().
1535 One example use for this property is to ease communication between
1536 interrupt-handler code and the code that was interrupted.
1538 (*) Within a loop, forces the compiler to load the variables used
1539 in that loop's conditional on each pass through that loop.
1541 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1542 optimizations that, while perfectly safe in single-threaded code, can
1543 be fatal in concurrent code. Here are some examples of these sorts
1544 of optimizations:
1546 (*) The compiler is within its rights to reorder loads and stores
1547 to the same variable, and in some cases, the CPU is within its
1548 rights to reorder loads to the same variable. This means that
1549 the following code:
1551 a[0] = x;
1552 a[1] = x;
1554 Might result in an older value of x stored in a[1] than in a[0].
1555 Prevent both the compiler and the CPU from doing this as follows:
1557 a[0] = READ_ONCE(x);
1558 a[1] = READ_ONCE(x);
1560 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1561 accesses from multiple CPUs to a single variable.
1563 (*) The compiler is within its rights to merge successive loads from
1564 the same variable. Such merging can cause the compiler to "optimize"
1565 the following code:
1567 while (tmp = a)
1568 do_something_with(tmp);
1570 into the following code, which, although in some sense legitimate
1571 for single-threaded code, is almost certainly not what the developer
1572 intended:
1574 if (tmp = a)
1575 for (;;)
1576 do_something_with(tmp);
1578 Use READ_ONCE() to prevent the compiler from doing this to you:
1580 while (tmp = READ_ONCE(a))
1581 do_something_with(tmp);
1583 (*) The compiler is within its rights to reload a variable, for example,
1584 in cases where high register pressure prevents the compiler from
1585 keeping all data of interest in registers. The compiler might
1586 therefore optimize the variable 'tmp' out of our previous example:
1588 while (tmp = a)
1589 do_something_with(tmp);
1591 This could result in the following code, which is perfectly safe in
1592 single-threaded code, but can be fatal in concurrent code:
1594 while (a)
1595 do_something_with(a);
1597 For example, the optimized version of this code could result in
1598 passing a zero to do_something_with() in the case where the variable
1599 a was modified by some other CPU between the "while" statement and
1600 the call to do_something_with().
1602 Again, use READ_ONCE() to prevent the compiler from doing this:
1604 while (tmp = READ_ONCE(a))
1605 do_something_with(tmp);
1607 Note that if the compiler runs short of registers, it might save
1608 tmp onto the stack. The overhead of this saving and later restoring
1609 is why compilers reload variables. Doing so is perfectly safe for
1610 single-threaded code, so you need to tell the compiler about cases
1611 where it is not safe.
1613 (*) The compiler is within its rights to omit a load entirely if it knows
1614 what the value will be. For example, if the compiler can prove that
1615 the value of variable 'a' is always zero, it can optimize this code:
1617 while (tmp = a)
1618 do_something_with(tmp);
1620 Into this:
1622 do { } while (0);
1624 This transformation is a win for single-threaded code because it
1625 gets rid of a load and a branch. The problem is that the compiler
1626 will carry out its proof assuming that the current CPU is the only
1627 one updating variable 'a'. If variable 'a' is shared, then the
1628 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1629 compiler that it doesn't know as much as it thinks it does:
1631 while (tmp = READ_ONCE(a))
1632 do_something_with(tmp);
1634 But please note that the compiler is also closely watching what you
1635 do with the value after the READ_ONCE(). For example, suppose you
1636 do the following and MAX is a preprocessor macro with the value 1:
1638 while ((tmp = READ_ONCE(a)) % MAX)
1639 do_something_with(tmp);
1641 Then the compiler knows that the result of the "%" operator applied
1642 to MAX will always be zero, again allowing the compiler to optimize
1643 the code into near-nonexistence. (It will still load from the
1644 variable 'a'.)
1646 (*) Similarly, the compiler is within its rights to omit a store entirely
1647 if it knows that the variable already has the value being stored.
1648 Again, the compiler assumes that the current CPU is the only one
1649 storing into the variable, which can cause the compiler to do the
1650 wrong thing for shared variables. For example, suppose you have
1651 the following:
1653 a = 0;
1654 ... Code that does not store to variable a ...
1655 a = 0;
1657 The compiler sees that the value of variable 'a' is already zero, so
1658 it might well omit the second store. This would come as a fatal
1659 surprise if some other CPU might have stored to variable 'a' in the
1660 meantime.
1662 Use WRITE_ONCE() to prevent the compiler from making this sort of
1663 wrong guess:
1665 WRITE_ONCE(a, 0);
1666 ... Code that does not store to variable a ...
1667 WRITE_ONCE(a, 0);
1669 (*) The compiler is within its rights to reorder memory accesses unless
1670 you tell it not to. For example, consider the following interaction
1671 between process-level code and an interrupt handler:
1673 void process_level(void)
1674 {
1675 msg = get_message();
1676 flag = true;
1677 }
1679 void interrupt_handler(void)
1680 {
1681 if (flag)
1682 process_message(msg);
1683 }
1685 There is nothing to prevent the compiler from transforming
1686 process_level() to the following, in fact, this might well be a
1687 win for single-threaded code:
1689 void process_level(void)
1690 {
1691 flag = true;
1692 msg = get_message();
1693 }
1695 If the interrupt occurs between these two statement, then
1696 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1697 to prevent this as follows:
1699 void process_level(void)
1700 {
1701 WRITE_ONCE(msg, get_message());
1702 WRITE_ONCE(flag, true);
1703 }
1705 void interrupt_handler(void)
1706 {
1707 if (READ_ONCE(flag))
1708 process_message(READ_ONCE(msg));
1709 }
1711 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1712 interrupt_handler() are needed if this interrupt handler can itself
1713 be interrupted by something that also accesses 'flag' and 'msg',
1714 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1715 and WRITE_ONCE() are not needed in interrupt_handler() other than
1716 for documentation purposes. (Note also that nested interrupts
1717 do not typically occur in modern Linux kernels, in fact, if an
1718 interrupt handler returns with interrupts enabled, you will get a
1719 WARN_ONCE() splat.)
1721 You should assume that the compiler can move READ_ONCE() and
1722 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1723 barrier(), or similar primitives.
1725 This effect could also be achieved using barrier(), but READ_ONCE()
1726 and WRITE_ONCE() are more selective: With READ_ONCE() and
1727 WRITE_ONCE(), the compiler need only forget the contents of the
1728 indicated memory locations, while with barrier() the compiler must
1729 discard the value of all memory locations that it has currented
1730 cached in any machine registers. Of course, the compiler must also
1731 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1732 though the CPU of course need not do so.
1734 (*) The compiler is within its rights to invent stores to a variable,
1735 as in the following example:
1737 if (a)
1738 b = a;
1739 else
1740 b = 42;
1742 The compiler might save a branch by optimizing this as follows:
1744 b = 42;
1745 if (a)
1746 b = a;
1748 In single-threaded code, this is not only safe, but also saves
1749 a branch. Unfortunately, in concurrent code, this optimization
1750 could cause some other CPU to see a spurious value of 42 -- even
1751 if variable 'a' was never zero -- when loading variable 'b'.
1752 Use WRITE_ONCE() to prevent this as follows:
1754 if (a)
1755 WRITE_ONCE(b, a);
1756 else
1757 WRITE_ONCE(b, 42);
1759 The compiler can also invent loads. These are usually less
1760 damaging, but they can result in cache-line bouncing and thus in
1761 poor performance and scalability. Use READ_ONCE() to prevent
1762 invented loads.
1764 (*) For aligned memory locations whose size allows them to be accessed
1765 with a single memory-reference instruction, prevents "load tearing"
1766 and "store tearing," in which a single large access is replaced by
1767 multiple smaller accesses. For example, given an architecture having
1768 16-bit store instructions with 7-bit immediate fields, the compiler
1769 might be tempted to use two 16-bit store-immediate instructions to
1770 implement the following 32-bit store:
1772 p = 0x00010002;
1774 Please note that GCC really does use this sort of optimization,
1775 which is not surprising given that it would likely take more
1776 than two instructions to build the constant and then store it.
1777 This optimization can therefore be a win in single-threaded code.
1778 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1779 this optimization in a volatile store. In the absence of such bugs,
1780 use of WRITE_ONCE() prevents store tearing in the following example:
1782 WRITE_ONCE(p, 0x00010002);
1784 Use of packed structures can also result in load and store tearing,
1785 as in this example:
1787 struct __attribute__((__packed__)) foo {
1788 short a;
1789 int b;
1790 short c;
1791 };
1792 struct foo foo1, foo2;
1793 ...
1795 foo2.a = foo1.a;
1796 foo2.b = foo1.b;
1797 foo2.c = foo1.c;
1799 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1800 volatile markings, the compiler would be well within its rights to
1801 implement these three assignment statements as a pair of 32-bit
1802 loads followed by a pair of 32-bit stores. This would result in
1803 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1804 and WRITE_ONCE() again prevent tearing in this example:
1806 foo2.a = foo1.a;
1807 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1808 foo2.c = foo1.c;
1810 All that aside, it is never necessary to use READ_ONCE() and
1811 WRITE_ONCE() on a variable that has been marked volatile. For example,
1812 because 'jiffies' is marked volatile, it is never necessary to
1813 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1814 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1815 its argument is already marked volatile.
1817 Please note that these compiler barriers have no direct effect on the CPU,
1818 which may then reorder things however it wishes.
1821 CPU MEMORY BARRIERS
1822 -------------------
1824 The Linux kernel has eight basic CPU memory barriers:
1826 TYPE MANDATORY SMP CONDITIONAL
1827 =============== ======================= ===========================
1828 GENERAL mb() smp_mb()
1829 WRITE wmb() smp_wmb()
1830 READ rmb() smp_rmb()
1831 DATA DEPENDENCY READ_ONCE()
1834 All memory barriers except the data dependency barriers imply a compiler
1835 barrier. Data dependencies do not impose any additional compiler ordering.
1837 Aside: In the case of data dependencies, the compiler would be expected
1838 to issue the loads in the correct order (eg. `a[b]` would have to load
1839 the value of b before loading a[b]), however there is no guarantee in
1840 the C specification that the compiler may not speculate the value of b
1841 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1842 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1843 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1844 has not yet been reached about these problems, however the READ_ONCE()
1845 macro is a good place to start looking.
1847 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1848 systems because it is assumed that a CPU will appear to be self-consistent,
1849 and will order overlapping accesses correctly with respect to itself.
1850 However, see the subsection on "Virtual Machine Guests" below.
1852 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1853 references to shared memory on SMP systems, though the use of locking instead
1854 is sufficient.
1856 Mandatory barriers should not be used to control SMP effects, since mandatory
1857 barriers impose unnecessary overhead on both SMP and UP systems. They may,
1858 however, be used to control MMIO effects on accesses through relaxed memory I/O
1859 windows. These barriers are required even on non-SMP systems as they affect
1860 the order in which memory operations appear to a device by prohibiting both the
1861 compiler and the CPU from reordering them.
1864 There are some more advanced barrier functions:
1866 (*) smp_store_mb(var, value)
1868 This assigns the value to the variable and then inserts a full memory
1869 barrier after it. It isn't guaranteed to insert anything more than a
1870 compiler barrier in a UP compilation.
1873 (*) smp_mb__before_atomic();
1874 (*) smp_mb__after_atomic();
1876 These are for use with atomic (such as add, subtract, increment and
1877 decrement) functions that don't return a value, especially when used for
1878 reference counting. These functions do not imply memory barriers.
1880 These are also used for atomic bitop functions that do not return a
1881 value (such as set_bit and clear_bit).
1883 As an example, consider a piece of code that marks an object as being dead
1884 and then decrements the object's reference count:
1886 obj->dead = 1;
1887 smp_mb__before_atomic();
1888 atomic_dec(&obj->ref_count);
1890 This makes sure that the death mark on the object is perceived to be set
1891 *before* the reference counter is decremented.
1893 See Documentation/atomic_{t,bitops}.txt for more information.
1896 (*) dma_wmb();
1897 (*) dma_rmb();
1899 These are for use with consistent memory to guarantee the ordering
1900 of writes or reads of shared memory accessible to both the CPU and a
1901 DMA capable device.
1903 For example, consider a device driver that shares memory with a device
1904 and uses a descriptor status value to indicate if the descriptor belongs
1905 to the device or the CPU, and a doorbell to notify it when new
1906 descriptors are available:
1908 if (desc->status != DEVICE_OWN) {
1909 /* do not read data until we own descriptor */
1910 dma_rmb();
1912 /* read/modify data */
1913 read_data = desc->data;
1914 desc->data = write_data;
1916 /* flush modifications before status update */
1917 dma_wmb();
1919 /* assign ownership */
1920 desc->status = DEVICE_OWN;
1922 /* notify device of new descriptors */
1923 writel(DESC_NOTIFY, doorbell);
1924 }
1926 The dma_rmb() allows us guarantee the device has released ownership
1927 before we read the data from the descriptor, and the dma_wmb() allows
1928 us to guarantee the data is written to the descriptor before the device
1929 can see it now has ownership. Note that, when using writel(), a prior
1930 wmb() is not needed to guarantee that the cache coherent memory writes
1931 have completed before writing to the MMIO region. The cheaper
1932 writel_relaxed() does not provide this guarantee and must not be used
1933 here.
1935 See the subsection "Kernel I/O barrier effects" for more information on
1936 relaxed I/O accessors and the Documentation/DMA-API.txt file for more
1937 information on consistent memory.
1940 MMIO WRITE BARRIER
1941 ------------------
1943 The Linux kernel also has a special barrier for use with memory-mapped I/O
1944 writes:
1946 mmiowb();
1948 This is a variation on the mandatory write barrier that causes writes to weakly
1949 ordered I/O regions to be partially ordered. Its effects may go beyond the
1950 CPU->Hardware interface and actually affect the hardware at some level.
1952 See the subsection "Acquires vs I/O accesses" for more information.
1955 ===============================
1956 IMPLICIT KERNEL MEMORY BARRIERS
1957 ===============================
1959 Some of the other functions in the linux kernel imply memory barriers, amongst
1960 which are locking and scheduling functions.
1962 This specification is a _minimum_ guarantee; any particular architecture may
1963 provide more substantial guarantees, but these may not be relied upon outside
1964 of arch specific code.
1967 LOCK ACQUISITION FUNCTIONS
1968 --------------------------
1970 The Linux kernel has a number of locking constructs:
1972 (*) spin locks
1973 (*) R/W spin locks
1974 (*) mutexes
1975 (*) semaphores
1976 (*) R/W semaphores
1978 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1979 for each construct. These operations all imply certain barriers:
1981 (1) ACQUIRE operation implication:
1983 Memory operations issued after the ACQUIRE will be completed after the
1984 ACQUIRE operation has completed.
1986 Memory operations issued before the ACQUIRE may be completed after
1987 the ACQUIRE operation has completed.
1989 (2) RELEASE operation implication:
1991 Memory operations issued before the RELEASE will be completed before the
1992 RELEASE operation has completed.
1994 Memory operations issued after the RELEASE may be completed before the
1995 RELEASE operation has completed.
1997 (3) ACQUIRE vs ACQUIRE implication:
1999 All ACQUIRE operations issued before another ACQUIRE operation will be
2000 completed before that ACQUIRE operation.
2002 (4) ACQUIRE vs RELEASE implication:
2004 All ACQUIRE operations issued before a RELEASE operation will be
2005 completed before the RELEASE operation.
2007 (5) Failed conditional ACQUIRE implication:
2009 Certain locking variants of the ACQUIRE operation may fail, either due to
2010 being unable to get the lock immediately, or due to receiving an unblocked
2011 signal whilst asleep waiting for the lock to become available. Failed
2012 locks do not imply any sort of barrier.
2014 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
2015 one-way barriers is that the effects of instructions outside of a critical
2016 section may seep into the inside of the critical section.
2018 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2019 because it is possible for an access preceding the ACQUIRE to happen after the
2020 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2021 the two accesses can themselves then cross:
2023 *A = a;
2024 ACQUIRE M
2025 RELEASE M
2026 *B = b;
2028 may occur as:
2030 ACQUIRE M, STORE *B, STORE *A, RELEASE M
2032 When the ACQUIRE and RELEASE are a lock acquisition and release,
2033 respectively, this same reordering can occur if the lock's ACQUIRE and
2034 RELEASE are to the same lock variable, but only from the perspective of
2035 another CPU not holding that lock. In short, a ACQUIRE followed by an
2036 RELEASE may -not- be assumed to be a full memory barrier.
2038 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2039 not imply a full memory barrier. Therefore, the CPU's execution of the
2040 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2041 so that:
2043 *A = a;
2044 RELEASE M
2045 ACQUIRE N
2046 *B = b;
2048 could occur as:
2050 ACQUIRE N, STORE *B, STORE *A, RELEASE M
2052 It might appear that this reordering could introduce a deadlock.
2053 However, this cannot happen because if such a deadlock threatened,
2054 the RELEASE would simply complete, thereby avoiding the deadlock.
2056 Why does this work?
2058 One key point is that we are only talking about the CPU doing
2059 the reordering, not the compiler. If the compiler (or, for
2060 that matter, the developer) switched the operations, deadlock
2061 -could- occur.
2063 But suppose the CPU reordered the operations. In this case,
2064 the unlock precedes the lock in the assembly code. The CPU
2065 simply elected to try executing the later lock operation first.
2066 If there is a deadlock, this lock operation will simply spin (or
2067 try to sleep, but more on that later). The CPU will eventually
2068 execute the unlock operation (which preceded the lock operation
2069 in the assembly code), which will unravel the potential deadlock,
2070 allowing the lock operation to succeed.
2072 But what if the lock is a sleeplock? In that case, the code will
2073 try to enter the scheduler, where it will eventually encounter
2074 a memory barrier, which will force the earlier unlock operation
2075 to complete, again unraveling the deadlock. There might be
2076 a sleep-unlock race, but the locking primitive needs to resolve
2077 such races properly in any case.
2079 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2080 systems, and so cannot be counted on in such a situation to actually achieve
2081 anything at all - especially with respect to I/O accesses - unless combined
2082 with interrupt disabling operations.
2084 See also the section on "Inter-CPU acquiring barrier effects".
2087 As an example, consider the following:
2089 *A = a;
2090 *B = b;
2091 ACQUIRE
2092 *C = c;
2093 *D = d;
2094 RELEASE
2095 *E = e;
2096 *F = f;
2098 The following sequence of events is acceptable:
2100 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2102 [+] Note that {*F,*A} indicates a combined access.
2104 But none of the following are:
2106 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2107 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2108 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2109 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2113 INTERRUPT DISABLING FUNCTIONS
2114 -----------------------------
2116 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2117 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2118 barriers are required in such a situation, they must be provided from some
2119 other means.
2122 SLEEP AND WAKE-UP FUNCTIONS
2123 ---------------------------
2125 Sleeping and waking on an event flagged in global data can be viewed as an
2126 interaction between two pieces of data: the task state of the task waiting for
2127 the event and the global data used to indicate the event. To make sure that
2128 these appear to happen in the right order, the primitives to begin the process
2129 of going to sleep, and the primitives to initiate a wake up imply certain
2130 barriers.
2132 Firstly, the sleeper normally follows something like this sequence of events:
2134 for (;;) {
2135 set_current_state(TASK_UNINTERRUPTIBLE);
2136 if (event_indicated)
2137 break;
2138 schedule();
2139 }
2141 A general memory barrier is interpolated automatically by set_current_state()
2142 after it has altered the task state:
2144 CPU 1
2145 ===============================
2146 set_current_state();
2147 smp_store_mb();
2148 STORE current->state
2149 <general barrier>
2150 LOAD event_indicated
2152 set_current_state() may be wrapped by:
2154 prepare_to_wait();
2155 prepare_to_wait_exclusive();
2157 which therefore also imply a general memory barrier after setting the state.
2158 The whole sequence above is available in various canned forms, all of which
2159 interpolate the memory barrier in the right place:
2161 wait_event();
2162 wait_event_interruptible();
2163 wait_event_interruptible_exclusive();
2164 wait_event_interruptible_timeout();
2165 wait_event_killable();
2166 wait_event_timeout();
2167 wait_on_bit();
2168 wait_on_bit_lock();
2171 Secondly, code that performs a wake up normally follows something like this:
2173 event_indicated = 1;
2174 wake_up(&event_wait_queue);
2176 or:
2178 event_indicated = 1;
2179 wake_up_process(event_daemon);
2181 A general memory barrier is executed by wake_up() if it wakes something up.
2182 If it doesn't wake anything up then a memory barrier may or may not be
2183 executed; you must not rely on it. The barrier occurs before the task state
2184 is accessed, in particular, it sits between the STORE to indicate the event
2185 and the STORE to set TASK_RUNNING:
2187 CPU 1 (Sleeper) CPU 2 (Waker)
2188 =============================== ===============================
2189 set_current_state(); STORE event_indicated
2190 smp_store_mb(); wake_up();
2191 STORE current->state ...
2192 <general barrier> <general barrier>
2193 LOAD event_indicated if ((LOAD task->state) & TASK_NORMAL)
2194 STORE task->state
2196 where "task" is the thread being woken up and it equals CPU 1's "current".
2198 To repeat, a general memory barrier is guaranteed to be executed by wake_up()
2199 if something is actually awakened, but otherwise there is no such guarantee.
2200 To see this, consider the following sequence of events, where X and Y are both
2201 initially zero:
2203 CPU 1 CPU 2
2204 =============================== ===============================
2205 X = 1; Y = 1;
2206 smp_mb(); wake_up();
2207 LOAD Y LOAD X
2209 If a wakeup does occur, one (at least) of the two loads must see 1. If, on
2210 the other hand, a wakeup does not occur, both loads might see 0.
2212 wake_up_process() always executes a general memory barrier. The barrier again
2213 occurs before the task state is accessed. In particular, if the wake_up() in
2214 the previous snippet were replaced by a call to wake_up_process() then one of
2215 the two loads would be guaranteed to see 1.
2217 The available waker functions include:
2219 complete();
2220 wake_up();
2221 wake_up_all();
2222 wake_up_bit();
2223 wake_up_interruptible();
2224 wake_up_interruptible_all();
2225 wake_up_interruptible_nr();
2226 wake_up_interruptible_poll();
2227 wake_up_interruptible_sync();
2228 wake_up_interruptible_sync_poll();
2229 wake_up_locked();
2230 wake_up_locked_poll();
2231 wake_up_nr();
2232 wake_up_poll();
2233 wake_up_process();
2235 In terms of memory ordering, these functions all provide the same guarantees of
2236 a wake_up() (or stronger).
2238 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2239 order multiple stores before the wake-up with respect to loads of those stored
2240 values after the sleeper has called set_current_state(). For instance, if the
2241 sleeper does:
2243 set_current_state(TASK_INTERRUPTIBLE);
2244 if (event_indicated)
2245 break;
2246 __set_current_state(TASK_RUNNING);
2247 do_something(my_data);
2249 and the waker does:
2251 my_data = value;
2252 event_indicated = 1;
2253 wake_up(&event_wait_queue);
2255 there's no guarantee that the change to event_indicated will be perceived by
2256 the sleeper as coming after the change to my_data. In such a circumstance, the
2257 code on both sides must interpolate its own memory barriers between the
2258 separate data accesses. Thus the above sleeper ought to do:
2260 set_current_state(TASK_INTERRUPTIBLE);
2261 if (event_indicated) {
2262 smp_rmb();
2263 do_something(my_data);
2264 }
2266 and the waker should do:
2268 my_data = value;
2269 smp_wmb();
2270 event_indicated = 1;
2271 wake_up(&event_wait_queue);
2274 MISCELLANEOUS FUNCTIONS
2275 -----------------------
2277 Other functions that imply barriers:
2279 (*) schedule() and similar imply full memory barriers.
2282 ===================================
2283 INTER-CPU ACQUIRING BARRIER EFFECTS
2284 ===================================
2286 On SMP systems locking primitives give a more substantial form of barrier: one
2287 that does affect memory access ordering on other CPUs, within the context of
2288 conflict on any particular lock.
2291 ACQUIRES VS MEMORY ACCESSES
2292 ---------------------------
2294 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2295 three CPUs; then should the following sequence of events occur:
2297 CPU 1 CPU 2
2298 =============================== ===============================
2299 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2300 ACQUIRE M ACQUIRE Q
2301 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2302 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2303 RELEASE M RELEASE Q
2304 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2306 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2307 through *H occur in, other than the constraints imposed by the separate locks
2308 on the separate CPUs. It might, for example, see:
2310 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2312 But it won't see any of:
2314 *B, *C or *D preceding ACQUIRE M
2315 *A, *B or *C following RELEASE M
2316 *F, *G or *H preceding ACQUIRE Q
2317 *E, *F or *G following RELEASE Q
2321 ACQUIRES VS I/O ACCESSES
2322 ------------------------
2324 Under certain circumstances (especially involving NUMA), I/O accesses within
2325 two spinlocked sections on two different CPUs may be seen as interleaved by the
2326 PCI bridge, because the PCI bridge does not necessarily participate in the
2327 cache-coherence protocol, and is therefore incapable of issuing the required
2328 read memory barriers.
2330 For example:
2332 CPU 1 CPU 2
2333 =============================== ===============================
2334 spin_lock(Q)
2335 writel(0, ADDR)
2336 writel(1, DATA);
2337 spin_unlock(Q);
2338 spin_lock(Q);
2339 writel(4, ADDR);
2340 writel(5, DATA);
2341 spin_unlock(Q);
2343 may be seen by the PCI bridge as follows:
2345 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2347 which would probably cause the hardware to malfunction.
2350 What is necessary here is to intervene with an mmiowb() before dropping the
2351 spinlock, for example:
2353 CPU 1 CPU 2
2354 =============================== ===============================
2355 spin_lock(Q)
2356 writel(0, ADDR)
2357 writel(1, DATA);
2358 mmiowb();
2359 spin_unlock(Q);
2360 spin_lock(Q);
2361 writel(4, ADDR);
2362 writel(5, DATA);
2363 mmiowb();
2364 spin_unlock(Q);
2366 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2367 before either of the stores issued on CPU 2.
2370 Furthermore, following a store by a load from the same device obviates the need
2371 for the mmiowb(), because the load forces the store to complete before the load
2372 is performed:
2374 CPU 1 CPU 2
2375 =============================== ===============================
2376 spin_lock(Q)
2377 writel(0, ADDR)
2378 a = readl(DATA);
2379 spin_unlock(Q);
2380 spin_lock(Q);
2381 writel(4, ADDR);
2382 b = readl(DATA);
2383 spin_unlock(Q);
2386 See Documentation/driver-api/device-io.rst for more information.
2389 =================================
2390 WHERE ARE MEMORY BARRIERS NEEDED?
2391 =================================
2393 Under normal operation, memory operation reordering is generally not going to
2394 be a problem as a single-threaded linear piece of code will still appear to
2395 work correctly, even if it's in an SMP kernel. There are, however, four
2396 circumstances in which reordering definitely _could_ be a problem:
2398 (*) Interprocessor interaction.
2400 (*) Atomic operations.
2402 (*) Accessing devices.
2404 (*) Interrupts.
2407 INTERPROCESSOR INTERACTION
2408 --------------------------
2410 When there's a system with more than one processor, more than one CPU in the
2411 system may be working on the same data set at the same time. This can cause
2412 synchronisation problems, and the usual way of dealing with them is to use
2413 locks. Locks, however, are quite expensive, and so it may be preferable to
2414 operate without the use of a lock if at all possible. In such a case
2415 operations that affect both CPUs may have to be carefully ordered to prevent
2416 a malfunction.
2418 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2419 queued on the semaphore, by virtue of it having a piece of its stack linked to
2420 the semaphore's list of waiting processes:
2422 struct rw_semaphore {
2423 ...
2424 spinlock_t lock;
2425 struct list_head waiters;
2426 };
2428 struct rwsem_waiter {
2429 struct list_head list;
2430 struct task_struct *task;
2431 };
2433 To wake up a particular waiter, the up_read() or up_write() functions have to:
2435 (1) read the next pointer from this waiter's record to know as to where the
2436 next waiter record is;
2438 (2) read the pointer to the waiter's task structure;
2440 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2442 (4) call wake_up_process() on the task; and
2444 (5) release the reference held on the waiter's task struct.
2446 In other words, it has to perform this sequence of events:
2448 LOAD waiter->list.next;
2449 LOAD waiter->task;
2450 STORE waiter->task;
2451 CALL wakeup
2452 RELEASE task
2454 and if any of these steps occur out of order, then the whole thing may
2455 malfunction.
2457 Once it has queued itself and dropped the semaphore lock, the waiter does not
2458 get the lock again; it instead just waits for its task pointer to be cleared
2459 before proceeding. Since the record is on the waiter's stack, this means that
2460 if the task pointer is cleared _before_ the next pointer in the list is read,
2461 another CPU might start processing the waiter and might clobber the waiter's
2462 stack before the up*() function has a chance to read the next pointer.
2464 Consider then what might happen to the above sequence of events:
2466 CPU 1 CPU 2
2467 =============================== ===============================
2468 down_xxx()
2469 Queue waiter
2470 Sleep
2471 up_yyy()
2472 LOAD waiter->task;
2473 STORE waiter->task;
2474 Woken up by other event
2475 <preempt>
2476 Resume processing
2477 down_xxx() returns
2478 call foo()
2479 foo() clobbers *waiter
2480 </preempt>
2481 LOAD waiter->list.next;
2482 --- OOPS ---
2484 This could be dealt with using the semaphore lock, but then the down_xxx()
2485 function has to needlessly get the spinlock again after being woken up.
2487 The way to deal with this is to insert a general SMP memory barrier:
2489 LOAD waiter->list.next;
2490 LOAD waiter->task;
2491 smp_mb();
2492 STORE waiter->task;
2493 CALL wakeup
2494 RELEASE task
2496 In this case, the barrier makes a guarantee that all memory accesses before the
2497 barrier will appear to happen before all the memory accesses after the barrier
2498 with respect to the other CPUs on the system. It does _not_ guarantee that all
2499 the memory accesses before the barrier will be complete by the time the barrier
2500 instruction itself is complete.
2502 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2503 compiler barrier, thus making sure the compiler emits the instructions in the
2504 right order without actually intervening in the CPU. Since there's only one
2505 CPU, that CPU's dependency ordering logic will take care of everything else.
2508 ATOMIC OPERATIONS
2509 -----------------
2511 Whilst they are technically interprocessor interaction considerations, atomic
2512 operations are noted specially as some of them imply full memory barriers and
2513 some don't, but they're very heavily relied on as a group throughout the
2514 kernel.
2516 See Documentation/atomic_t.txt for more information.
2519 ACCESSING DEVICES
2520 -----------------
2522 Many devices can be memory mapped, and so appear to the CPU as if they're just
2523 a set of memory locations. To control such a device, the driver usually has to
2524 make the right memory accesses in exactly the right order.
2526 However, having a clever CPU or a clever compiler creates a potential problem
2527 in that the carefully sequenced accesses in the driver code won't reach the
2528 device in the requisite order if the CPU or the compiler thinks it is more
2529 efficient to reorder, combine or merge accesses - something that would cause
2530 the device to malfunction.
2532 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2533 routines - such as inb() or writel() - which know how to make such accesses
2534 appropriately sequential. Whilst this, for the most part, renders the explicit
2535 use of memory barriers unnecessary, there are a couple of situations where they
2536 might be needed:
2538 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2539 so for _all_ general drivers locks should be used and mmiowb() must be
2540 issued prior to unlocking the critical section.
2542 (2) If the accessor functions are used to refer to an I/O memory window with
2543 relaxed memory access properties, then _mandatory_ memory barriers are
2544 required to enforce ordering.
2546 See Documentation/driver-api/device-io.rst for more information.
2549 INTERRUPTS
2550 ----------
2552 A driver may be interrupted by its own interrupt service routine, and thus the
2553 two parts of the driver may interfere with each other's attempts to control or
2554 access the device.
2556 This may be alleviated - at least in part - by disabling local interrupts (a
2557 form of locking), such that the critical operations are all contained within
2558 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2559 routine is executing, the driver's core may not run on the same CPU, and its
2560 interrupt is not permitted to happen again until the current interrupt has been
2561 handled, thus the interrupt handler does not need to lock against that.
2563 However, consider a driver that was talking to an ethernet card that sports an
2564 address register and a data register. If that driver's core talks to the card
2565 under interrupt-disablement and then the driver's interrupt handler is invoked:
2567 LOCAL IRQ DISABLE
2568 writew(ADDR, 3);
2569 writew(DATA, y);
2570 LOCAL IRQ ENABLE
2571 <interrupt>
2572 writew(ADDR, 4);
2573 q = readw(DATA);
2574 </interrupt>
2576 The store to the data register might happen after the second store to the
2577 address register if ordering rules are sufficiently relaxed:
2579 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2582 If ordering rules are relaxed, it must be assumed that accesses done inside an
2583 interrupt disabled section may leak outside of it and may interleave with
2584 accesses performed in an interrupt - and vice versa - unless implicit or
2585 explicit barriers are used.
2587 Normally this won't be a problem because the I/O accesses done inside such
2588 sections will include synchronous load operations on strictly ordered I/O
2589 registers that form implicit I/O barriers. If this isn't sufficient then an
2590 mmiowb() may need to be used explicitly.
2593 A similar situation may occur between an interrupt routine and two routines
2594 running on separate CPUs that communicate with each other. If such a case is
2595 likely, then interrupt-disabling locks should be used to guarantee ordering.
2598 ==========================
2599 KERNEL I/O BARRIER EFFECTS
2600 ==========================
2602 When accessing I/O memory, drivers should use the appropriate accessor
2603 functions:
2605 (*) inX(), outX():
2607 These are intended to talk to I/O space rather than memory space, but
2608 that's primarily a CPU-specific concept. The i386 and x86_64 processors
2609 do indeed have special I/O space access cycles and instructions, but many
2610 CPUs don't have such a concept.
2612 The PCI bus, amongst others, defines an I/O space concept which - on such
2613 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2614 space. However, it may also be mapped as a virtual I/O space in the CPU's
2615 memory map, particularly on those CPUs that don't support alternate I/O
2616 spaces.
2618 Accesses to this space may be fully synchronous (as on i386), but
2619 intermediary bridges (such as the PCI host bridge) may not fully honour
2620 that.
2622 They are guaranteed to be fully ordered with respect to each other.
2624 They are not guaranteed to be fully ordered with respect to other types of
2625 memory and I/O operation.
2627 (*) readX(), writeX():
2629 Whether these are guaranteed to be fully ordered and uncombined with
2630 respect to each other on the issuing CPU depends on the characteristics
2631 defined for the memory window through which they're accessing. On later
2632 i386 architecture machines, for example, this is controlled by way of the
2633 MTRR registers.
2635 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2636 provided they're not accessing a prefetchable device.
2638 However, intermediary hardware (such as a PCI bridge) may indulge in
2639 deferral if it so wishes; to flush a store, a load from the same location
2640 is preferred[*], but a load from the same device or from configuration
2641 space should suffice for PCI.
2643 [*] NOTE! attempting to load from the same location as was written to may
2644 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2645 example.
2647 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2648 force stores to be ordered.
2650 Please refer to the PCI specification for more information on interactions
2651 between PCI transactions.
2653 (*) readX_relaxed(), writeX_relaxed()
2655 These are similar to readX() and writeX(), but provide weaker memory
2656 ordering guarantees. Specifically, they do not guarantee ordering with
2657 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2658 ordering with respect to LOCK or UNLOCK operations. If the latter is
2659 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2660 the same peripheral are guaranteed to be ordered with respect to each
2661 other.
2663 (*) ioreadX(), iowriteX()
2665 These will perform appropriately for the type of access they're actually
2666 doing, be it inX()/outX() or readX()/writeX().
2669 ========================================
2670 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2671 ========================================
2673 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2674 maintain the appearance of program causality with respect to itself. Some CPUs
2675 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2676 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2677 of arch-specific code.
2679 This means that it must be considered that the CPU will execute its instruction
2680 stream in any order it feels like - or even in parallel - provided that if an
2681 instruction in the stream depends on an earlier instruction, then that
2682 earlier instruction must be sufficiently complete[*] before the later
2683 instruction may proceed; in other words: provided that the appearance of
2684 causality is maintained.
2686 [*] Some instructions have more than one effect - such as changing the
2687 condition codes, changing registers or changing memory - and different
2688 instructions may depend on different effects.
2690 A CPU may also discard any instruction sequence that winds up having no
2691 ultimate effect. For example, if two adjacent instructions both load an
2692 immediate value into the same register, the first may be discarded.
2695 Similarly, it has to be assumed that compiler might reorder the instruction
2696 stream in any way it sees fit, again provided the appearance of causality is
2697 maintained.
2700 ============================
2701 THE EFFECTS OF THE CPU CACHE
2702 ============================
2704 The way cached memory operations are perceived across the system is affected to
2705 a certain extent by the caches that lie between CPUs and memory, and by the
2706 memory coherence system that maintains the consistency of state in the system.
2708 As far as the way a CPU interacts with another part of the system through the
2709 caches goes, the memory system has to include the CPU's caches, and memory
2710 barriers for the most part act at the interface between the CPU and its cache
2711 (memory barriers logically act on the dotted line in the following diagram):
2713 <--- CPU ---> : <----------- Memory ----------->
2714 :
2715 +--------+ +--------+ : +--------+ +-----------+
2716 | | | | : | | | | +--------+
2717 | CPU | | Memory | : | CPU | | | | |
2718 | Core |--->| Access |----->| Cache |<-->| | | |
2719 | | | Queue | : | | | |--->| Memory |
2720 | | | | : | | | | | |
2721 +--------+ +--------+ : +--------+ | | | |
2722 : | Cache | +--------+
2723 : | Coherency |
2724 : | Mechanism | +--------+
2725 +--------+ +--------+ : +--------+ | | | |
2726 | | | | : | | | | | |
2727 | CPU | | Memory | : | CPU | | |--->| Device |
2728 | Core |--->| Access |----->| Cache |<-->| | | |
2729 | | | Queue | : | | | | | |
2730 | | | | : | | | | +--------+
2731 +--------+ +--------+ : +--------+ +-----------+
2732 :
2733 :
2735 Although any particular load or store may not actually appear outside of the
2736 CPU that issued it since it may have been satisfied within the CPU's own cache,
2737 it will still appear as if the full memory access had taken place as far as the
2738 other CPUs are concerned since the cache coherency mechanisms will migrate the
2739 cacheline over to the accessing CPU and propagate the effects upon conflict.
2741 The CPU core may execute instructions in any order it deems fit, provided the
2742 expected program causality appears to be maintained. Some of the instructions
2743 generate load and store operations which then go into the queue of memory
2744 accesses to be performed. The core may place these in the queue in any order
2745 it wishes, and continue execution until it is forced to wait for an instruction
2746 to complete.
2748 What memory barriers are concerned with is controlling the order in which
2749 accesses cross from the CPU side of things to the memory side of things, and
2750 the order in which the effects are perceived to happen by the other observers
2751 in the system.
2753 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2754 their own loads and stores as if they had happened in program order.
2756 [!] MMIO or other device accesses may bypass the cache system. This depends on
2757 the properties of the memory window through which devices are accessed and/or
2758 the use of any special device communication instructions the CPU may have.
2761 CACHE COHERENCY
2762 ---------------
2764 Life isn't quite as simple as it may appear above, however: for while the
2765 caches are expected to be coherent, there's no guarantee that that coherency
2766 will be ordered. This means that whilst changes made on one CPU will
2767 eventually become visible on all CPUs, there's no guarantee that they will
2768 become apparent in the same order on those other CPUs.
2771 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2772 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2774 :
2775 : +--------+
2776 : +---------+ | |
2777 +--------+ : +--->| Cache A |<------->| |
2778 | | : | +---------+ | |
2779 | CPU 1 |<---+ | |
2780 | | : | +---------+ | |
2781 +--------+ : +--->| Cache B |<------->| |
2782 : +---------+ | |
2783 : | Memory |
2784 : +---------+ | System |
2785 +--------+ : +--->| Cache C |<------->| |
2786 | | : | +---------+ | |
2787 | CPU 2 |<---+ | |
2788 | | : | +---------+ | |
2789 +--------+ : +--->| Cache D |<------->| |
2790 : +---------+ | |
2791 : +--------+
2792 :
2794 Imagine the system has the following properties:
2796 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2797 resident in memory;
2799 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2800 resident in memory;
2802 (*) whilst the CPU core is interrogating one cache, the other cache may be
2803 making use of the bus to access the rest of the system - perhaps to
2804 displace a dirty cacheline or to do a speculative load;
2806 (*) each cache has a queue of operations that need to be applied to that cache
2807 to maintain coherency with the rest of the system;
2809 (*) the coherency queue is not flushed by normal loads to lines already
2810 present in the cache, even though the contents of the queue may
2811 potentially affect those loads.
2813 Imagine, then, that two writes are made on the first CPU, with a write barrier
2814 between them to guarantee that they will appear to reach that CPU's caches in
2815 the requisite order:
2817 CPU 1 CPU 2 COMMENT
2818 =============== =============== =======================================
2819 u == 0, v == 1 and p == &u, q == &u
2820 v = 2;
2821 smp_wmb(); Make sure change to v is visible before
2822 change to p
2823 <A:modify v=2> v is now in cache A exclusively
2824 p = &v;
2825 <B:modify p=&v> p is now in cache B exclusively
2827 The write memory barrier forces the other CPUs in the system to perceive that
2828 the local CPU's caches have apparently been updated in the correct order. But
2829 now imagine that the second CPU wants to read those values:
2831 CPU 1 CPU 2 COMMENT
2832 =============== =============== =======================================
2833 ...
2834 q = p;
2835 x = *q;
2837 The above pair of reads may then fail to happen in the expected order, as the
2838 cacheline holding p may get updated in one of the second CPU's caches whilst
2839 the update to the cacheline holding v is delayed in the other of the second
2840 CPU's caches by some other cache event:
2842 CPU 1 CPU 2 COMMENT
2843 =============== =============== =======================================
2844 u == 0, v == 1 and p == &u, q == &u
2845 v = 2;
2846 smp_wmb();
2847 <A:modify v=2> <C:busy>
2848 <C:queue v=2>
2849 p = &v; q = p;
2850 <D:request p>
2851 <B:modify p=&v> <D:commit p=&v>
2852 <D:read p>
2853 x = *q;
2854 <C:read *q> Reads from v before v updated in cache
2855 <C:unbusy>
2856 <C:commit v=2>
2858 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2859 no guarantee that, without intervention, the order of update will be the same
2860 as that committed on CPU 1.
2863 To intervene, we need to interpolate a data dependency barrier or a read
2864 barrier between the loads (which as of v4.15 is supplied unconditionally
2865 by the READ_ONCE() macro). This will force the cache to commit its
2866 coherency queue before processing any further requests:
2868 CPU 1 CPU 2 COMMENT
2869 =============== =============== =======================================
2870 u == 0, v == 1 and p == &u, q == &u
2871 v = 2;
2872 smp_wmb();
2873 <A:modify v=2> <C:busy>
2874 <C:queue v=2>
2875 p = &v; q = p;
2876 <D:request p>
2877 <B:modify p=&v> <D:commit p=&v>
2878 <D:read p>
2879 smp_read_barrier_depends()
2880 <C:unbusy>
2881 <C:commit v=2>
2882 x = *q;
2883 <C:read *q> Reads from v after v updated in cache
2886 This sort of problem can be encountered on DEC Alpha processors as they have a
2887 split cache that improves performance by making better use of the data bus.
2888 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2889 access depends on a read, not all do, so it may not be relied on.
2891 Other CPUs may also have split caches, but must coordinate between the various
2892 cachelets for normal memory accesses. The semantics of the Alpha removes the
2893 need for hardware coordination in the absence of memory barriers, which
2894 permitted Alpha to sport higher CPU clock rates back in the day. However,
2895 please note that (again, as of v4.15) smp_read_barrier_depends() should not
2896 be used except in Alpha arch-specific code and within the READ_ONCE() macro.
2899 CACHE COHERENCY VS DMA
2900 ----------------------
2902 Not all systems maintain cache coherency with respect to devices doing DMA. In
2903 such cases, a device attempting DMA may obtain stale data from RAM because
2904 dirty cache lines may be resident in the caches of various CPUs, and may not
2905 have been written back to RAM yet. To deal with this, the appropriate part of
2906 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2907 invalidate them as well).
2909 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2910 cache lines being written back to RAM from a CPU's cache after the device has
2911 installed its own data, or cache lines present in the CPU's cache may simply
2912 obscure the fact that RAM has been updated, until at such time as the cacheline
2913 is discarded from the CPU's cache and reloaded. To deal with this, the
2914 appropriate part of the kernel must invalidate the overlapping bits of the
2915 cache on each CPU.
2917 See Documentation/core-api/cachetlb.rst for more information on cache management.
2920 CACHE COHERENCY VS MMIO
2921 -----------------------
2923 Memory mapped I/O usually takes place through memory locations that are part of
2924 a window in the CPU's memory space that has different properties assigned than
2925 the usual RAM directed window.
2927 Amongst these properties is usually the fact that such accesses bypass the
2928 caching entirely and go directly to the device buses. This means MMIO accesses
2929 may, in effect, overtake accesses to cached memory that were emitted earlier.
2930 A memory barrier isn't sufficient in such a case, but rather the cache must be
2931 flushed between the cached memory write and the MMIO access if the two are in
2932 any way dependent.
2935 =========================
2936 THE THINGS CPUS GET UP TO
2937 =========================
2939 A programmer might take it for granted that the CPU will perform memory
2940 operations in exactly the order specified, so that if the CPU is, for example,
2941 given the following piece of code to execute:
2943 a = READ_ONCE(*A);
2944 WRITE_ONCE(*B, b);
2945 c = READ_ONCE(*C);
2946 d = READ_ONCE(*D);
2947 WRITE_ONCE(*E, e);
2949 they would then expect that the CPU will complete the memory operation for each
2950 instruction before moving on to the next one, leading to a definite sequence of
2951 operations as seen by external observers in the system:
2953 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2956 Reality is, of course, much messier. With many CPUs and compilers, the above
2957 assumption doesn't hold because:
2959 (*) loads are more likely to need to be completed immediately to permit
2960 execution progress, whereas stores can often be deferred without a
2961 problem;
2963 (*) loads may be done speculatively, and the result discarded should it prove
2964 to have been unnecessary;
2966 (*) loads may be done speculatively, leading to the result having been fetched
2967 at the wrong time in the expected sequence of events;
2969 (*) the order of the memory accesses may be rearranged to promote better use
2970 of the CPU buses and caches;
2972 (*) loads and stores may be combined to improve performance when talking to
2973 memory or I/O hardware that can do batched accesses of adjacent locations,
2974 thus cutting down on transaction setup costs (memory and PCI devices may
2975 both be able to do this); and
2977 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2978 mechanisms may alleviate this - once the store has actually hit the cache
2979 - there's no guarantee that the coherency management will be propagated in
2980 order to other CPUs.
2982 So what another CPU, say, might actually observe from the above piece of code
2983 is:
2985 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2987 (Where "LOAD {*C,*D}" is a combined load)
2990 However, it is guaranteed that a CPU will be self-consistent: it will see its
2991 _own_ accesses appear to be correctly ordered, without the need for a memory
2992 barrier. For instance with the following code:
2994 U = READ_ONCE(*A);
2995 WRITE_ONCE(*A, V);
2996 WRITE_ONCE(*A, W);
2997 X = READ_ONCE(*A);
2998 WRITE_ONCE(*A, Y);
2999 Z = READ_ONCE(*A);
3001 and assuming no intervention by an external influence, it can be assumed that
3002 the final result will appear to be:
3004 U == the original value of *A
3005 X == W
3006 Z == Y
3007 *A == Y
3009 The code above may cause the CPU to generate the full sequence of memory
3010 accesses:
3012 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
3014 in that order, but, without intervention, the sequence may have almost any
3015 combination of elements combined or discarded, provided the program's view
3016 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
3017 are -not- optional in the above example, as there are architectures
3018 where a given CPU might reorder successive loads to the same location.
3019 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
3020 necessary to prevent this, for example, on Itanium the volatile casts
3021 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
3022 and st.rel instructions (respectively) that prevent such reordering.
3024 The compiler may also combine, discard or defer elements of the sequence before
3025 the CPU even sees them.
3027 For instance:
3029 *A = V;
3030 *A = W;
3032 may be reduced to:
3034 *A = W;
3036 since, without either a write barrier or an WRITE_ONCE(), it can be
3037 assumed that the effect of the storage of V to *A is lost. Similarly:
3039 *A = Y;
3040 Z = *A;
3042 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
3043 reduced to:
3045 *A = Y;
3046 Z = Y;
3048 and the LOAD operation never appear outside of the CPU.
3051 AND THEN THERE'S THE ALPHA
3052 --------------------------
3054 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
3055 some versions of the Alpha CPU have a split data cache, permitting them to have
3056 two semantically-related cache lines updated at separate times. This is where
3057 the data dependency barrier really becomes necessary as this synchronises both
3058 caches with the memory coherence system, thus making it seem like pointer
3059 changes vs new data occur in the right order.
3061 The Alpha defines the Linux kernel's memory model, although as of v4.15
3062 the Linux kernel's addition of smp_read_barrier_depends() to READ_ONCE()
3063 greatly reduced Alpha's impact on the memory model.
3065 See the subsection on "Cache Coherency" above.
3068 VIRTUAL MACHINE GUESTS
3069 ----------------------
3071 Guests running within virtual machines might be affected by SMP effects even if
3072 the guest itself is compiled without SMP support. This is an artifact of
3073 interfacing with an SMP host while running an UP kernel. Using mandatory
3074 barriers for this use-case would be possible but is often suboptimal.
3076 To handle this case optimally, low-level virt_mb() etc macros are available.
3077 These have the same effect as smp_mb() etc when SMP is enabled, but generate
3078 identical code for SMP and non-SMP systems. For example, virtual machine guests
3079 should use virt_mb() rather than smp_mb() when synchronizing against a
3080 (possibly SMP) host.
3082 These are equivalent to smp_mb() etc counterparts in all other respects,
3083 in particular, they do not control MMIO effects: to control
3084 MMIO effects, use mandatory barriers.
3087 ============
3088 EXAMPLE USES
3089 ============
3091 CIRCULAR BUFFERS
3092 ----------------
3094 Memory barriers can be used to implement circular buffering without the need
3095 of a lock to serialise the producer with the consumer. See:
3097 Documentation/core-api/circular-buffers.rst
3099 for details.
3102 ==========
3103 REFERENCES
3104 ==========
3106 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
3107 Digital Press)
3108 Chapter 5.2: Physical Address Space Characteristics
3109 Chapter 5.4: Caches and Write Buffers
3110 Chapter 5.5: Data Sharing
3111 Chapter 5.6: Read/Write Ordering
3113 AMD64 Architecture Programmer's Manual Volume 2: System Programming
3114 Chapter 7.1: Memory-Access Ordering
3115 Chapter 7.4: Buffering and Combining Memory Writes
3117 ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile)
3118 Chapter B2: The AArch64 Application Level Memory Model
3120 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
3121 System Programming Guide
3122 Chapter 7.1: Locked Atomic Operations
3123 Chapter 7.2: Memory Ordering
3124 Chapter 7.4: Serializing Instructions
3126 The SPARC Architecture Manual, Version 9
3127 Chapter 8: Memory Models
3128 Appendix D: Formal Specification of the Memory Models
3129 Appendix J: Programming with the Memory Models
3131 Storage in the PowerPC (Stone and Fitzgerald)
3133 UltraSPARC Programmer Reference Manual
3134 Chapter 5: Memory Accesses and Cacheability
3135 Chapter 15: Sparc-V9 Memory Models
3137 UltraSPARC III Cu User's Manual
3138 Chapter 9: Memory Models
3140 UltraSPARC IIIi Processor User's Manual
3141 Chapter 8: Memory Models
3143 UltraSPARC Architecture 2005
3144 Chapter 9: Memory
3145 Appendix D: Formal Specifications of the Memory Models
3147 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3148 Chapter 8: Memory Models
3149 Appendix F: Caches and Cache Coherency
3151 Solaris Internals, Core Kernel Architecture, p63-68:
3152 Chapter 3.3: Hardware Considerations for Locks and
3153 Synchronization
3155 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3156 for Kernel Programmers:
3157 Chapter 13: Other Memory Models
3159 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3160 Section 2.6: Speculation
3161 Section 4.4: Memory Access