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perf bpf: Move perf_event_output() from stdio.h to bpf.h
[linux/fpc-iii.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
blob0c35a88e33dde45fdf6e0184d0d09d1185ec10a0
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
24 #endif
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
35 #include <linux/overflow.h>
36
37 #include <linux/reset.h>
38 #include <linux/delay.h>
39
40 #include "rockchip_drm_drv.h"
41 #include "rockchip_drm_gem.h"
42 #include "rockchip_drm_fb.h"
43 #include "rockchip_drm_psr.h"
44 #include "rockchip_drm_vop.h"
45 #include "rockchip_rgb.h"
46
47 #define VOP_WIN_SET(x, win, name, v) \
48 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
49 #define VOP_SCL_SET(x, win, name, v) \
50 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
51 #define VOP_SCL_SET_EXT(x, win, name, v) \
52 vop_reg_set(vop, &win->phy->scl->ext->name, \
53 win->base, ~0, v, #name)
54
55 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
56 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
57
58 #define VOP_REG_SET(vop, group, name, v) \
59 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
60
61 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
62 do { \
63 int i, reg = 0, mask = 0; \
64 for (i = 0; i < vop->data->intr->nintrs; i++) { \
65 if (vop->data->intr->intrs[i] & type) { \
66 reg |= (v) << i; \
67 mask |= 1 << i; \
68 } \
69 } \
70 VOP_INTR_SET_MASK(vop, name, mask, reg); \
71 } while (0)
72 #define VOP_INTR_GET_TYPE(vop, name, type) \
73 vop_get_intr_type(vop, &vop->data->intr->name, type)
74
75 #define VOP_WIN_GET(x, win, name) \
76 vop_read_reg(x, win->offset, win->phy->name)
77
78 #define VOP_WIN_GET_YRGBADDR(vop, win) \
79 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
80
81 #define VOP_WIN_TO_INDEX(vop_win) \
82 ((vop_win) - (vop_win)->vop->win)
83
84 #define to_vop(x) container_of(x, struct vop, crtc)
85 #define to_vop_win(x) container_of(x, struct vop_win, base)
86
87 enum vop_pending {
88 VOP_PENDING_FB_UNREF,
89 };
90
91 struct vop_win {
92 struct drm_plane base;
93 const struct vop_win_data *data;
94 struct vop *vop;
95 };
96
97 struct rockchip_rgb;
98 struct vop {
99 struct drm_crtc crtc;
100 struct device *dev;
101 struct drm_device *drm_dev;
102 bool is_enabled;
103
104 struct completion dsp_hold_completion;
105
106 /* protected by dev->event_lock */
107 struct drm_pending_vblank_event *event;
108
109 struct drm_flip_work fb_unref_work;
110 unsigned long pending;
111
112 struct completion line_flag_completion;
113
114 const struct vop_data *data;
115
116 uint32_t *regsbak;
117 void __iomem *regs;
118
119 /* physical map length of vop register */
120 uint32_t len;
121
122 /* one time only one process allowed to config the register */
123 spinlock_t reg_lock;
124 /* lock vop irq reg */
125 spinlock_t irq_lock;
126 /* protects crtc enable/disable */
127 struct mutex vop_lock;
128
129 unsigned int irq;
130
131 /* vop AHP clk */
132 struct clk *hclk;
133 /* vop dclk */
134 struct clk *dclk;
135 /* vop share memory frequency */
136 struct clk *aclk;
137
138 /* vop dclk reset */
139 struct reset_control *dclk_rst;
140
141 /* optional internal rgb encoder */
142 struct rockchip_rgb *rgb;
143
144 struct vop_win win[];
145 };
146
147 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
148 {
149 writel(v, vop->regs + offset);
150 vop->regsbak[offset >> 2] = v;
151 }
152
153 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
154 {
155 return readl(vop->regs + offset);
156 }
157
158 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
159 const struct vop_reg *reg)
160 {
161 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
162 }
163
164 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
165 uint32_t _offset, uint32_t _mask, uint32_t v,
166 const char *reg_name)
167 {
168 int offset, mask, shift;
169
170 if (!reg || !reg->mask) {
171 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
172 return;
173 }
174
175 offset = reg->offset + _offset;
176 mask = reg->mask & _mask;
177 shift = reg->shift;
178
179 if (reg->write_mask) {
180 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
181 } else {
182 uint32_t cached_val = vop->regsbak[offset >> 2];
183
184 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
185 vop->regsbak[offset >> 2] = v;
186 }
187
188 if (reg->relaxed)
189 writel_relaxed(v, vop->regs + offset);
190 else
191 writel(v, vop->regs + offset);
192 }
193
194 static inline uint32_t vop_get_intr_type(struct vop *vop,
195 const struct vop_reg *reg, int type)
196 {
197 uint32_t i, ret = 0;
198 uint32_t regs = vop_read_reg(vop, 0, reg);
199
200 for (i = 0; i < vop->data->intr->nintrs; i++) {
201 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
202 ret |= vop->data->intr->intrs[i];
203 }
204
205 return ret;
206 }
207
208 static inline void vop_cfg_done(struct vop *vop)
209 {
210 VOP_REG_SET(vop, common, cfg_done, 1);
211 }
212
213 static bool has_rb_swapped(uint32_t format)
214 {
215 switch (format) {
216 case DRM_FORMAT_XBGR8888:
217 case DRM_FORMAT_ABGR8888:
218 case DRM_FORMAT_BGR888:
219 case DRM_FORMAT_BGR565:
220 return true;
221 default:
222 return false;
223 }
224 }
225
226 static enum vop_data_format vop_convert_format(uint32_t format)
227 {
228 switch (format) {
229 case DRM_FORMAT_XRGB8888:
230 case DRM_FORMAT_ARGB8888:
231 case DRM_FORMAT_XBGR8888:
232 case DRM_FORMAT_ABGR8888:
233 return VOP_FMT_ARGB8888;
234 case DRM_FORMAT_RGB888:
235 case DRM_FORMAT_BGR888:
236 return VOP_FMT_RGB888;
237 case DRM_FORMAT_RGB565:
238 case DRM_FORMAT_BGR565:
239 return VOP_FMT_RGB565;
240 case DRM_FORMAT_NV12:
241 return VOP_FMT_YUV420SP;
242 case DRM_FORMAT_NV16:
243 return VOP_FMT_YUV422SP;
244 case DRM_FORMAT_NV24:
245 return VOP_FMT_YUV444SP;
246 default:
247 DRM_ERROR("unsupported format[%08x]\n", format);
248 return -EINVAL;
249 }
250 }
251
252 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
253 uint32_t dst, bool is_horizontal,
254 int vsu_mode, int *vskiplines)
255 {
256 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
257
258 if (vskiplines)
259 *vskiplines = 0;
260
261 if (is_horizontal) {
262 if (mode == SCALE_UP)
263 val = GET_SCL_FT_BIC(src, dst);
264 else if (mode == SCALE_DOWN)
265 val = GET_SCL_FT_BILI_DN(src, dst);
266 } else {
267 if (mode == SCALE_UP) {
268 if (vsu_mode == SCALE_UP_BIL)
269 val = GET_SCL_FT_BILI_UP(src, dst);
270 else
271 val = GET_SCL_FT_BIC(src, dst);
272 } else if (mode == SCALE_DOWN) {
273 if (vskiplines) {
274 *vskiplines = scl_get_vskiplines(src, dst);
275 val = scl_get_bili_dn_vskip(src, dst,
276 *vskiplines);
277 } else {
278 val = GET_SCL_FT_BILI_DN(src, dst);
279 }
280 }
281 }
282
283 return val;
284 }
285
286 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
287 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
288 uint32_t dst_h, uint32_t pixel_format)
289 {
290 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
291 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
292 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
293 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
294 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
295 const struct drm_format_info *info;
296 bool is_yuv = false;
297 uint16_t cbcr_src_w = src_w / hsub;
298 uint16_t cbcr_src_h = src_h / vsub;
299 uint16_t vsu_mode;
300 uint16_t lb_mode;
301 uint32_t val;
302 int vskiplines;
303
304 info = drm_format_info(pixel_format);
305
306 if (info->is_yuv)
307 is_yuv = true;
308
309 if (dst_w > 3840) {
310 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
311 return;
312 }
313
314 if (!win->phy->scl->ext) {
315 VOP_SCL_SET(vop, win, scale_yrgb_x,
316 scl_cal_scale2(src_w, dst_w));
317 VOP_SCL_SET(vop, win, scale_yrgb_y,
318 scl_cal_scale2(src_h, dst_h));
319 if (is_yuv) {
320 VOP_SCL_SET(vop, win, scale_cbcr_x,
321 scl_cal_scale2(cbcr_src_w, dst_w));
322 VOP_SCL_SET(vop, win, scale_cbcr_y,
323 scl_cal_scale2(cbcr_src_h, dst_h));
324 }
325 return;
326 }
327
328 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
329 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
330
331 if (is_yuv) {
332 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
333 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
334 if (cbcr_hor_scl_mode == SCALE_DOWN)
335 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
336 else
337 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
338 } else {
339 if (yrgb_hor_scl_mode == SCALE_DOWN)
340 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
341 else
342 lb_mode = scl_vop_cal_lb_mode(src_w, false);
343 }
344
345 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
346 if (lb_mode == LB_RGB_3840X2) {
347 if (yrgb_ver_scl_mode != SCALE_NONE) {
348 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
349 return;
350 }
351 if (cbcr_ver_scl_mode != SCALE_NONE) {
352 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
353 return;
354 }
355 vsu_mode = SCALE_UP_BIL;
356 } else if (lb_mode == LB_RGB_2560X4) {
357 vsu_mode = SCALE_UP_BIL;
358 } else {
359 vsu_mode = SCALE_UP_BIC;
360 }
361
362 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
363 true, 0, NULL);
364 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
365 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
366 false, vsu_mode, &vskiplines);
367 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
368
369 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
370 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
371
372 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
373 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
374 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
375 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
376 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
377 if (is_yuv) {
378 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
379 dst_w, true, 0, NULL);
380 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
381 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
382 dst_h, false, vsu_mode, &vskiplines);
383 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
384
385 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
386 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
387 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
388 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
389 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
390 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
391 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
392 }
393 }
394
395 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
396 {
397 unsigned long flags;
398
399 if (WARN_ON(!vop->is_enabled))
400 return;
401
402 spin_lock_irqsave(&vop->irq_lock, flags);
403
404 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
405 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
406
407 spin_unlock_irqrestore(&vop->irq_lock, flags);
408 }
409
410 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
411 {
412 unsigned long flags;
413
414 if (WARN_ON(!vop->is_enabled))
415 return;
416
417 spin_lock_irqsave(&vop->irq_lock, flags);
418
419 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
420
421 spin_unlock_irqrestore(&vop->irq_lock, flags);
422 }
423
424 /*
425 * (1) each frame starts at the start of the Vsync pulse which is signaled by
426 * the "FRAME_SYNC" interrupt.
427 * (2) the active data region of each frame ends at dsp_vact_end
428 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
429 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
430 *
431 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
432 * Interrupts
433 * LINE_FLAG -------------------------------+
434 * FRAME_SYNC ----+ |
435 * | |
436 * v v
437 * | Vsync | Vbp | Vactive | Vfp |
438 * ^ ^ ^ ^
439 * | | | |
440 * | | | |
441 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
442 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
443 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
444 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
445 */
446 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
447 {
448 uint32_t line_flag_irq;
449 unsigned long flags;
450
451 spin_lock_irqsave(&vop->irq_lock, flags);
452
453 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
454
455 spin_unlock_irqrestore(&vop->irq_lock, flags);
456
457 return !!line_flag_irq;
458 }
459
460 static void vop_line_flag_irq_enable(struct vop *vop)
461 {
462 unsigned long flags;
463
464 if (WARN_ON(!vop->is_enabled))
465 return;
466
467 spin_lock_irqsave(&vop->irq_lock, flags);
468
469 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
470 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
471
472 spin_unlock_irqrestore(&vop->irq_lock, flags);
473 }
474
475 static void vop_line_flag_irq_disable(struct vop *vop)
476 {
477 unsigned long flags;
478
479 if (WARN_ON(!vop->is_enabled))
480 return;
481
482 spin_lock_irqsave(&vop->irq_lock, flags);
483
484 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
485
486 spin_unlock_irqrestore(&vop->irq_lock, flags);
487 }
488
489 static int vop_core_clks_enable(struct vop *vop)
490 {
491 int ret;
492
493 ret = clk_enable(vop->hclk);
494 if (ret < 0)
495 return ret;
496
497 ret = clk_enable(vop->aclk);
498 if (ret < 0)
499 goto err_disable_hclk;
500
501 return 0;
502
503 err_disable_hclk:
504 clk_disable(vop->hclk);
505 return ret;
506 }
507
508 static void vop_core_clks_disable(struct vop *vop)
509 {
510 clk_disable(vop->aclk);
511 clk_disable(vop->hclk);
512 }
513
514 static int vop_enable(struct drm_crtc *crtc)
515 {
516 struct vop *vop = to_vop(crtc);
517 int ret, i;
518
519 ret = pm_runtime_get_sync(vop->dev);
520 if (ret < 0) {
521 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
522 return ret;
523 }
524
525 ret = vop_core_clks_enable(vop);
526 if (WARN_ON(ret < 0))
527 goto err_put_pm_runtime;
528
529 ret = clk_enable(vop->dclk);
530 if (WARN_ON(ret < 0))
531 goto err_disable_core;
532
533 /*
534 * Slave iommu shares power, irq and clock with vop. It was associated
535 * automatically with this master device via common driver code.
536 * Now that we have enabled the clock we attach it to the shared drm
537 * mapping.
538 */
539 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
540 if (ret) {
541 DRM_DEV_ERROR(vop->dev,
542 "failed to attach dma mapping, %d\n", ret);
543 goto err_disable_dclk;
544 }
545
546 spin_lock(&vop->reg_lock);
547 for (i = 0; i < vop->len; i += 4)
548 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
549
550 /*
551 * We need to make sure that all windows are disabled before we
552 * enable the crtc. Otherwise we might try to scan from a destroyed
553 * buffer later.
554 */
555 for (i = 0; i < vop->data->win_size; i++) {
556 struct vop_win *vop_win = &vop->win[i];
557 const struct vop_win_data *win = vop_win->data;
558
559 VOP_WIN_SET(vop, win, enable, 0);
560 }
561 spin_unlock(&vop->reg_lock);
562
563 vop_cfg_done(vop);
564
565 /*
566 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
567 */
568 vop->is_enabled = true;
569
570 spin_lock(&vop->reg_lock);
571
572 VOP_REG_SET(vop, common, standby, 1);
573
574 spin_unlock(&vop->reg_lock);
575
576 drm_crtc_vblank_on(crtc);
577
578 return 0;
579
580 err_disable_dclk:
581 clk_disable(vop->dclk);
582 err_disable_core:
583 vop_core_clks_disable(vop);
584 err_put_pm_runtime:
585 pm_runtime_put_sync(vop->dev);
586 return ret;
587 }
588
589 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
590 struct drm_crtc_state *old_state)
591 {
592 struct vop *vop = to_vop(crtc);
593
594 WARN_ON(vop->event);
595
596 mutex_lock(&vop->vop_lock);
597 drm_crtc_vblank_off(crtc);
598
599 /*
600 * Vop standby will take effect at end of current frame,
601 * if dsp hold valid irq happen, it means standby complete.
602 *
603 * we must wait standby complete when we want to disable aclk,
604 * if not, memory bus maybe dead.
605 */
606 reinit_completion(&vop->dsp_hold_completion);
607 vop_dsp_hold_valid_irq_enable(vop);
608
609 spin_lock(&vop->reg_lock);
610
611 VOP_REG_SET(vop, common, standby, 1);
612
613 spin_unlock(&vop->reg_lock);
614
615 wait_for_completion(&vop->dsp_hold_completion);
616
617 vop_dsp_hold_valid_irq_disable(vop);
618
619 vop->is_enabled = false;
620
621 /*
622 * vop standby complete, so iommu detach is safe.
623 */
624 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
625
626 clk_disable(vop->dclk);
627 vop_core_clks_disable(vop);
628 pm_runtime_put(vop->dev);
629 mutex_unlock(&vop->vop_lock);
630
631 if (crtc->state->event && !crtc->state->active) {
632 spin_lock_irq(&crtc->dev->event_lock);
633 drm_crtc_send_vblank_event(crtc, crtc->state->event);
634 spin_unlock_irq(&crtc->dev->event_lock);
635
636 crtc->state->event = NULL;
637 }
638 }
639
640 static void vop_plane_destroy(struct drm_plane *plane)
641 {
642 drm_plane_cleanup(plane);
643 }
644
645 static int vop_plane_atomic_check(struct drm_plane *plane,
646 struct drm_plane_state *state)
647 {
648 struct drm_crtc *crtc = state->crtc;
649 struct drm_crtc_state *crtc_state;
650 struct drm_framebuffer *fb = state->fb;
651 struct vop_win *vop_win = to_vop_win(plane);
652 const struct vop_win_data *win = vop_win->data;
653 int ret;
654 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
655 DRM_PLANE_HELPER_NO_SCALING;
656 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
657 DRM_PLANE_HELPER_NO_SCALING;
658
659 if (!crtc || !fb)
660 return 0;
661
662 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
663 if (WARN_ON(!crtc_state))
664 return -EINVAL;
665
666 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
667 min_scale, max_scale,
668 true, true);
669 if (ret)
670 return ret;
671
672 if (!state->visible)
673 return 0;
674
675 ret = vop_convert_format(fb->format->format);
676 if (ret < 0)
677 return ret;
678
679 /*
680 * Src.x1 can be odd when do clip, but yuv plane start point
681 * need align with 2 pixel.
682 */
683 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
684 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
685 return -EINVAL;
686 }
687
688 return 0;
689 }
690
691 static void vop_plane_atomic_disable(struct drm_plane *plane,
692 struct drm_plane_state *old_state)
693 {
694 struct vop_win *vop_win = to_vop_win(plane);
695 const struct vop_win_data *win = vop_win->data;
696 struct vop *vop = to_vop(old_state->crtc);
697
698 if (!old_state->crtc)
699 return;
700
701 spin_lock(&vop->reg_lock);
702
703 VOP_WIN_SET(vop, win, enable, 0);
704
705 spin_unlock(&vop->reg_lock);
706 }
707
708 static void vop_plane_atomic_update(struct drm_plane *plane,
709 struct drm_plane_state *old_state)
710 {
711 struct drm_plane_state *state = plane->state;
712 struct drm_crtc *crtc = state->crtc;
713 struct vop_win *vop_win = to_vop_win(plane);
714 const struct vop_win_data *win = vop_win->data;
715 struct vop *vop = to_vop(state->crtc);
716 struct drm_framebuffer *fb = state->fb;
717 unsigned int actual_w, actual_h;
718 unsigned int dsp_stx, dsp_sty;
719 uint32_t act_info, dsp_info, dsp_st;
720 struct drm_rect *src = &state->src;
721 struct drm_rect *dest = &state->dst;
722 struct drm_gem_object *obj, *uv_obj;
723 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
724 unsigned long offset;
725 dma_addr_t dma_addr;
726 uint32_t val;
727 bool rb_swap;
728 int win_index = VOP_WIN_TO_INDEX(vop_win);
729 int format;
730
731 /*
732 * can't update plane when vop is disabled.
733 */
734 if (WARN_ON(!crtc))
735 return;
736
737 if (WARN_ON(!vop->is_enabled))
738 return;
739
740 if (!state->visible) {
741 vop_plane_atomic_disable(plane, old_state);
742 return;
743 }
744
745 obj = fb->obj[0];
746 rk_obj = to_rockchip_obj(obj);
747
748 actual_w = drm_rect_width(src) >> 16;
749 actual_h = drm_rect_height(src) >> 16;
750 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
751
752 dsp_info = (drm_rect_height(dest) - 1) << 16;
753 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
754
755 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
756 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
757 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
758
759 offset = (src->x1 >> 16) * fb->format->cpp[0];
760 offset += (src->y1 >> 16) * fb->pitches[0];
761 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
762
763 format = vop_convert_format(fb->format->format);
764
765 spin_lock(&vop->reg_lock);
766
767 VOP_WIN_SET(vop, win, format, format);
768 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
769 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
770 if (fb->format->is_yuv) {
771 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
772 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
773 int bpp = fb->format->cpp[1];
774
775 uv_obj = fb->obj[1];
776 rk_uv_obj = to_rockchip_obj(uv_obj);
777
778 offset = (src->x1 >> 16) * bpp / hsub;
779 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
780
781 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
782 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
783 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
784 }
785
786 if (win->phy->scl)
787 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
788 drm_rect_width(dest), drm_rect_height(dest),
789 fb->format->format);
790
791 VOP_WIN_SET(vop, win, act_info, act_info);
792 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
793 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
794
795 rb_swap = has_rb_swapped(fb->format->format);
796 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
797
798 /*
799 * Blending win0 with the background color doesn't seem to work
800 * correctly. We only get the background color, no matter the contents
801 * of the win0 framebuffer. However, blending pre-multiplied color
802 * with the default opaque black default background color is a no-op,
803 * so we can just disable blending to get the correct result.
804 */
805 if (fb->format->has_alpha && win_index > 0) {
806 VOP_WIN_SET(vop, win, dst_alpha_ctl,
807 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
808 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
809 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
810 SRC_BLEND_M0(ALPHA_PER_PIX) |
811 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
812 SRC_FACTOR_M0(ALPHA_ONE);
813 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
814 } else {
815 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
816 }
817
818 VOP_WIN_SET(vop, win, enable, 1);
819 spin_unlock(&vop->reg_lock);
820 }
821
822 static const struct drm_plane_helper_funcs plane_helper_funcs = {
823 .atomic_check = vop_plane_atomic_check,
824 .atomic_update = vop_plane_atomic_update,
825 .atomic_disable = vop_plane_atomic_disable,
826 };
827
828 static const struct drm_plane_funcs vop_plane_funcs = {
829 .update_plane = drm_atomic_helper_update_plane,
830 .disable_plane = drm_atomic_helper_disable_plane,
831 .destroy = vop_plane_destroy,
832 .reset = drm_atomic_helper_plane_reset,
833 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
834 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
835 };
836
837 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
838 {
839 struct vop *vop = to_vop(crtc);
840 unsigned long flags;
841
842 if (WARN_ON(!vop->is_enabled))
843 return -EPERM;
844
845 spin_lock_irqsave(&vop->irq_lock, flags);
846
847 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
848 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
849
850 spin_unlock_irqrestore(&vop->irq_lock, flags);
851
852 return 0;
853 }
854
855 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
856 {
857 struct vop *vop = to_vop(crtc);
858 unsigned long flags;
859
860 if (WARN_ON(!vop->is_enabled))
861 return;
862
863 spin_lock_irqsave(&vop->irq_lock, flags);
864
865 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
866
867 spin_unlock_irqrestore(&vop->irq_lock, flags);
868 }
869
870 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
871 const struct drm_display_mode *mode,
872 struct drm_display_mode *adjusted_mode)
873 {
874 struct vop *vop = to_vop(crtc);
875
876 adjusted_mode->clock =
877 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
878
879 return true;
880 }
881
882 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
883 struct drm_crtc_state *old_state)
884 {
885 struct vop *vop = to_vop(crtc);
886 const struct vop_data *vop_data = vop->data;
887 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
888 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
889 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
890 u16 hdisplay = adjusted_mode->hdisplay;
891 u16 htotal = adjusted_mode->htotal;
892 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
893 u16 hact_end = hact_st + hdisplay;
894 u16 vdisplay = adjusted_mode->vdisplay;
895 u16 vtotal = adjusted_mode->vtotal;
896 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
897 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
898 u16 vact_end = vact_st + vdisplay;
899 uint32_t pin_pol, val;
900 int ret;
901
902 mutex_lock(&vop->vop_lock);
903
904 WARN_ON(vop->event);
905
906 ret = vop_enable(crtc);
907 if (ret) {
908 mutex_unlock(&vop->vop_lock);
909 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
910 return;
911 }
912
913 pin_pol = BIT(DCLK_INVERT);
914 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
915 BIT(HSYNC_POSITIVE) : 0;
916 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
917 BIT(VSYNC_POSITIVE) : 0;
918 VOP_REG_SET(vop, output, pin_pol, pin_pol);
919
920 switch (s->output_type) {
921 case DRM_MODE_CONNECTOR_LVDS:
922 VOP_REG_SET(vop, output, rgb_en, 1);
923 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
924 break;
925 case DRM_MODE_CONNECTOR_eDP:
926 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
927 VOP_REG_SET(vop, output, edp_en, 1);
928 break;
929 case DRM_MODE_CONNECTOR_HDMIA:
930 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
931 VOP_REG_SET(vop, output, hdmi_en, 1);
932 break;
933 case DRM_MODE_CONNECTOR_DSI:
934 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
935 VOP_REG_SET(vop, output, mipi_en, 1);
936 break;
937 case DRM_MODE_CONNECTOR_DisplayPort:
938 pin_pol &= ~BIT(DCLK_INVERT);
939 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
940 VOP_REG_SET(vop, output, dp_en, 1);
941 break;
942 default:
943 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
944 s->output_type);
945 }
946
947 /*
948 * if vop is not support RGB10 output, need force RGB10 to RGB888.
949 */
950 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
951 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
952 s->output_mode = ROCKCHIP_OUT_MODE_P888;
953
954 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8)
955 VOP_REG_SET(vop, common, pre_dither_down, 1);
956 else
957 VOP_REG_SET(vop, common, pre_dither_down, 0);
958
959 VOP_REG_SET(vop, common, out_mode, s->output_mode);
960
961 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
962 val = hact_st << 16;
963 val |= hact_end;
964 VOP_REG_SET(vop, modeset, hact_st_end, val);
965 VOP_REG_SET(vop, modeset, hpost_st_end, val);
966
967 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
968 val = vact_st << 16;
969 val |= vact_end;
970 VOP_REG_SET(vop, modeset, vact_st_end, val);
971 VOP_REG_SET(vop, modeset, vpost_st_end, val);
972
973 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
974
975 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
976
977 VOP_REG_SET(vop, common, standby, 0);
978 mutex_unlock(&vop->vop_lock);
979 }
980
981 static bool vop_fs_irq_is_pending(struct vop *vop)
982 {
983 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
984 }
985
986 static void vop_wait_for_irq_handler(struct vop *vop)
987 {
988 bool pending;
989 int ret;
990
991 /*
992 * Spin until frame start interrupt status bit goes low, which means
993 * that interrupt handler was invoked and cleared it. The timeout of
994 * 10 msecs is really too long, but it is just a safety measure if
995 * something goes really wrong. The wait will only happen in the very
996 * unlikely case of a vblank happening exactly at the same time and
997 * shouldn't exceed microseconds range.
998 */
999 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1000 !pending, 0, 10 * 1000);
1001 if (ret)
1002 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1003
1004 synchronize_irq(vop->irq);
1005 }
1006
1007 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1008 struct drm_crtc_state *old_crtc_state)
1009 {
1010 struct drm_atomic_state *old_state = old_crtc_state->state;
1011 struct drm_plane_state *old_plane_state, *new_plane_state;
1012 struct vop *vop = to_vop(crtc);
1013 struct drm_plane *plane;
1014 int i;
1015
1016 if (WARN_ON(!vop->is_enabled))
1017 return;
1018
1019 spin_lock(&vop->reg_lock);
1020
1021 vop_cfg_done(vop);
1022
1023 spin_unlock(&vop->reg_lock);
1024
1025 /*
1026 * There is a (rather unlikely) possiblity that a vblank interrupt
1027 * fired before we set the cfg_done bit. To avoid spuriously
1028 * signalling flip completion we need to wait for it to finish.
1029 */
1030 vop_wait_for_irq_handler(vop);
1031
1032 spin_lock_irq(&crtc->dev->event_lock);
1033 if (crtc->state->event) {
1034 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1035 WARN_ON(vop->event);
1036
1037 vop->event = crtc->state->event;
1038 crtc->state->event = NULL;
1039 }
1040 spin_unlock_irq(&crtc->dev->event_lock);
1041
1042 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1043 new_plane_state, i) {
1044 if (!old_plane_state->fb)
1045 continue;
1046
1047 if (old_plane_state->fb == new_plane_state->fb)
1048 continue;
1049
1050 drm_framebuffer_get(old_plane_state->fb);
1051 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1052 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1053 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1054 }
1055 }
1056
1057 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1058 .mode_fixup = vop_crtc_mode_fixup,
1059 .atomic_flush = vop_crtc_atomic_flush,
1060 .atomic_enable = vop_crtc_atomic_enable,
1061 .atomic_disable = vop_crtc_atomic_disable,
1062 };
1063
1064 static void vop_crtc_destroy(struct drm_crtc *crtc)
1065 {
1066 drm_crtc_cleanup(crtc);
1067 }
1068
1069 static void vop_crtc_reset(struct drm_crtc *crtc)
1070 {
1071 if (crtc->state)
1072 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1073 kfree(crtc->state);
1074
1075 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1076 if (crtc->state)
1077 crtc->state->crtc = crtc;
1078 }
1079
1080 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1081 {
1082 struct rockchip_crtc_state *rockchip_state;
1083
1084 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1085 if (!rockchip_state)
1086 return NULL;
1087
1088 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1089 return &rockchip_state->base;
1090 }
1091
1092 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1093 struct drm_crtc_state *state)
1094 {
1095 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1096
1097 __drm_atomic_helper_crtc_destroy_state(&s->base);
1098 kfree(s);
1099 }
1100
1101 #ifdef CONFIG_DRM_ANALOGIX_DP
1102 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1103 {
1104 struct drm_connector *connector;
1105 struct drm_connector_list_iter conn_iter;
1106
1107 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1108 drm_for_each_connector_iter(connector, &conn_iter) {
1109 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1110 drm_connector_list_iter_end(&conn_iter);
1111 return connector;
1112 }
1113 }
1114 drm_connector_list_iter_end(&conn_iter);
1115
1116 return NULL;
1117 }
1118
1119 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1120 const char *source_name)
1121 {
1122 struct vop *vop = to_vop(crtc);
1123 struct drm_connector *connector;
1124 int ret;
1125
1126 connector = vop_get_edp_connector(vop);
1127 if (!connector)
1128 return -EINVAL;
1129
1130 if (source_name && strcmp(source_name, "auto") == 0)
1131 ret = analogix_dp_start_crc(connector);
1132 else if (!source_name)
1133 ret = analogix_dp_stop_crc(connector);
1134 else
1135 ret = -EINVAL;
1136
1137 return ret;
1138 }
1139
1140 static int
1141 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1142 size_t *values_cnt)
1143 {
1144 if (source_name && strcmp(source_name, "auto") != 0)
1145 return -EINVAL;
1146
1147 *values_cnt = 3;
1148 return 0;
1149 }
1150
1151 #else
1152 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1153 const char *source_name)
1154 {
1155 return -ENODEV;
1156 }
1157
1158 static int
1159 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1160 size_t *values_cnt)
1161 {
1162 return -ENODEV;
1163 }
1164 #endif
1165
1166 static const struct drm_crtc_funcs vop_crtc_funcs = {
1167 .set_config = drm_atomic_helper_set_config,
1168 .page_flip = drm_atomic_helper_page_flip,
1169 .destroy = vop_crtc_destroy,
1170 .reset = vop_crtc_reset,
1171 .atomic_duplicate_state = vop_crtc_duplicate_state,
1172 .atomic_destroy_state = vop_crtc_destroy_state,
1173 .enable_vblank = vop_crtc_enable_vblank,
1174 .disable_vblank = vop_crtc_disable_vblank,
1175 .set_crc_source = vop_crtc_set_crc_source,
1176 .verify_crc_source = vop_crtc_verify_crc_source,
1177 };
1178
1179 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1180 {
1181 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1182 struct drm_framebuffer *fb = val;
1183
1184 drm_crtc_vblank_put(&vop->crtc);
1185 drm_framebuffer_put(fb);
1186 }
1187
1188 static void vop_handle_vblank(struct vop *vop)
1189 {
1190 struct drm_device *drm = vop->drm_dev;
1191 struct drm_crtc *crtc = &vop->crtc;
1192
1193 spin_lock(&drm->event_lock);
1194 if (vop->event) {
1195 drm_crtc_send_vblank_event(crtc, vop->event);
1196 drm_crtc_vblank_put(crtc);
1197 vop->event = NULL;
1198 }
1199 spin_unlock(&drm->event_lock);
1200
1201 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1202 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1203 }
1204
1205 static irqreturn_t vop_isr(int irq, void *data)
1206 {
1207 struct vop *vop = data;
1208 struct drm_crtc *crtc = &vop->crtc;
1209 uint32_t active_irqs;
1210 int ret = IRQ_NONE;
1211
1212 /*
1213 * The irq is shared with the iommu. If the runtime-pm state of the
1214 * vop-device is disabled the irq has to be targeted at the iommu.
1215 */
1216 if (!pm_runtime_get_if_in_use(vop->dev))
1217 return IRQ_NONE;
1218
1219 if (vop_core_clks_enable(vop)) {
1220 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1221 goto out;
1222 }
1223
1224 /*
1225 * interrupt register has interrupt status, enable and clear bits, we
1226 * must hold irq_lock to avoid a race with enable/disable_vblank().
1227 */
1228 spin_lock(&vop->irq_lock);
1229
1230 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1231 /* Clear all active interrupt sources */
1232 if (active_irqs)
1233 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1234
1235 spin_unlock(&vop->irq_lock);
1236
1237 /* This is expected for vop iommu irqs, since the irq is shared */
1238 if (!active_irqs)
1239 goto out_disable;
1240
1241 if (active_irqs & DSP_HOLD_VALID_INTR) {
1242 complete(&vop->dsp_hold_completion);
1243 active_irqs &= ~DSP_HOLD_VALID_INTR;
1244 ret = IRQ_HANDLED;
1245 }
1246
1247 if (active_irqs & LINE_FLAG_INTR) {
1248 complete(&vop->line_flag_completion);
1249 active_irqs &= ~LINE_FLAG_INTR;
1250 ret = IRQ_HANDLED;
1251 }
1252
1253 if (active_irqs & FS_INTR) {
1254 drm_crtc_handle_vblank(crtc);
1255 vop_handle_vblank(vop);
1256 active_irqs &= ~FS_INTR;
1257 ret = IRQ_HANDLED;
1258 }
1259
1260 /* Unhandled irqs are spurious. */
1261 if (active_irqs)
1262 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1263 active_irqs);
1264
1265 out_disable:
1266 vop_core_clks_disable(vop);
1267 out:
1268 pm_runtime_put(vop->dev);
1269 return ret;
1270 }
1271
1272 static int vop_create_crtc(struct vop *vop)
1273 {
1274 const struct vop_data *vop_data = vop->data;
1275 struct device *dev = vop->dev;
1276 struct drm_device *drm_dev = vop->drm_dev;
1277 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1278 struct drm_crtc *crtc = &vop->crtc;
1279 struct device_node *port;
1280 int ret;
1281 int i;
1282
1283 /*
1284 * Create drm_plane for primary and cursor planes first, since we need
1285 * to pass them to drm_crtc_init_with_planes, which sets the
1286 * "possible_crtcs" to the newly initialized crtc.
1287 */
1288 for (i = 0; i < vop_data->win_size; i++) {
1289 struct vop_win *vop_win = &vop->win[i];
1290 const struct vop_win_data *win_data = vop_win->data;
1291
1292 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1293 win_data->type != DRM_PLANE_TYPE_CURSOR)
1294 continue;
1295
1296 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1297 0, &vop_plane_funcs,
1298 win_data->phy->data_formats,
1299 win_data->phy->nformats,
1300 NULL, win_data->type, NULL);
1301 if (ret) {
1302 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1303 ret);
1304 goto err_cleanup_planes;
1305 }
1306
1307 plane = &vop_win->base;
1308 drm_plane_helper_add(plane, &plane_helper_funcs);
1309 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1310 primary = plane;
1311 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1312 cursor = plane;
1313 }
1314
1315 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1316 &vop_crtc_funcs, NULL);
1317 if (ret)
1318 goto err_cleanup_planes;
1319
1320 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1321
1322 /*
1323 * Create drm_planes for overlay windows with possible_crtcs restricted
1324 * to the newly created crtc.
1325 */
1326 for (i = 0; i < vop_data->win_size; i++) {
1327 struct vop_win *vop_win = &vop->win[i];
1328 const struct vop_win_data *win_data = vop_win->data;
1329 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1330
1331 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1332 continue;
1333
1334 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1335 possible_crtcs,
1336 &vop_plane_funcs,
1337 win_data->phy->data_formats,
1338 win_data->phy->nformats,
1339 NULL, win_data->type, NULL);
1340 if (ret) {
1341 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1342 ret);
1343 goto err_cleanup_crtc;
1344 }
1345 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1346 }
1347
1348 port = of_get_child_by_name(dev->of_node, "port");
1349 if (!port) {
1350 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1351 dev->of_node);
1352 ret = -ENOENT;
1353 goto err_cleanup_crtc;
1354 }
1355
1356 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1357 vop_fb_unref_worker);
1358
1359 init_completion(&vop->dsp_hold_completion);
1360 init_completion(&vop->line_flag_completion);
1361 crtc->port = port;
1362
1363 return 0;
1364
1365 err_cleanup_crtc:
1366 drm_crtc_cleanup(crtc);
1367 err_cleanup_planes:
1368 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1369 head)
1370 drm_plane_cleanup(plane);
1371 return ret;
1372 }
1373
1374 static void vop_destroy_crtc(struct vop *vop)
1375 {
1376 struct drm_crtc *crtc = &vop->crtc;
1377 struct drm_device *drm_dev = vop->drm_dev;
1378 struct drm_plane *plane, *tmp;
1379
1380 of_node_put(crtc->port);
1381
1382 /*
1383 * We need to cleanup the planes now. Why?
1384 *
1385 * The planes are "&vop->win[i].base". That means the memory is
1386 * all part of the big "struct vop" chunk of memory. That memory
1387 * was devm allocated and associated with this component. We need to
1388 * free it ourselves before vop_unbind() finishes.
1389 */
1390 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1391 head)
1392 vop_plane_destroy(plane);
1393
1394 /*
1395 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1396 * references the CRTC.
1397 */
1398 drm_crtc_cleanup(crtc);
1399 drm_flip_work_cleanup(&vop->fb_unref_work);
1400 }
1401
1402 static int vop_initial(struct vop *vop)
1403 {
1404 const struct vop_data *vop_data = vop->data;
1405 struct reset_control *ahb_rst;
1406 int i, ret;
1407
1408 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1409 if (IS_ERR(vop->hclk)) {
1410 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1411 return PTR_ERR(vop->hclk);
1412 }
1413 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1414 if (IS_ERR(vop->aclk)) {
1415 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1416 return PTR_ERR(vop->aclk);
1417 }
1418 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1419 if (IS_ERR(vop->dclk)) {
1420 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1421 return PTR_ERR(vop->dclk);
1422 }
1423
1424 ret = pm_runtime_get_sync(vop->dev);
1425 if (ret < 0) {
1426 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1427 return ret;
1428 }
1429
1430 ret = clk_prepare(vop->dclk);
1431 if (ret < 0) {
1432 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1433 goto err_put_pm_runtime;
1434 }
1435
1436 /* Enable both the hclk and aclk to setup the vop */
1437 ret = clk_prepare_enable(vop->hclk);
1438 if (ret < 0) {
1439 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1440 goto err_unprepare_dclk;
1441 }
1442
1443 ret = clk_prepare_enable(vop->aclk);
1444 if (ret < 0) {
1445 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1446 goto err_disable_hclk;
1447 }
1448
1449 /*
1450 * do hclk_reset, reset all vop registers.
1451 */
1452 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1453 if (IS_ERR(ahb_rst)) {
1454 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1455 ret = PTR_ERR(ahb_rst);
1456 goto err_disable_aclk;
1457 }
1458 reset_control_assert(ahb_rst);
1459 usleep_range(10, 20);
1460 reset_control_deassert(ahb_rst);
1461
1462 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1463 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1464
1465 for (i = 0; i < vop->len; i += sizeof(u32))
1466 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1467
1468 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1469 VOP_REG_SET(vop, common, dsp_blank, 0);
1470
1471 for (i = 0; i < vop_data->win_size; i++) {
1472 const struct vop_win_data *win = &vop_data->win[i];
1473 int channel = i * 2 + 1;
1474
1475 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1476 VOP_WIN_SET(vop, win, enable, 0);
1477 VOP_WIN_SET(vop, win, gate, 1);
1478 }
1479
1480 vop_cfg_done(vop);
1481
1482 /*
1483 * do dclk_reset, let all config take affect.
1484 */
1485 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1486 if (IS_ERR(vop->dclk_rst)) {
1487 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1488 ret = PTR_ERR(vop->dclk_rst);
1489 goto err_disable_aclk;
1490 }
1491 reset_control_assert(vop->dclk_rst);
1492 usleep_range(10, 20);
1493 reset_control_deassert(vop->dclk_rst);
1494
1495 clk_disable(vop->hclk);
1496 clk_disable(vop->aclk);
1497
1498 vop->is_enabled = false;
1499
1500 pm_runtime_put_sync(vop->dev);
1501
1502 return 0;
1503
1504 err_disable_aclk:
1505 clk_disable_unprepare(vop->aclk);
1506 err_disable_hclk:
1507 clk_disable_unprepare(vop->hclk);
1508 err_unprepare_dclk:
1509 clk_unprepare(vop->dclk);
1510 err_put_pm_runtime:
1511 pm_runtime_put_sync(vop->dev);
1512 return ret;
1513 }
1514
1515 /*
1516 * Initialize the vop->win array elements.
1517 */
1518 static void vop_win_init(struct vop *vop)
1519 {
1520 const struct vop_data *vop_data = vop->data;
1521 unsigned int i;
1522
1523 for (i = 0; i < vop_data->win_size; i++) {
1524 struct vop_win *vop_win = &vop->win[i];
1525 const struct vop_win_data *win_data = &vop_data->win[i];
1526
1527 vop_win->data = win_data;
1528 vop_win->vop = vop;
1529 }
1530 }
1531
1532 /**
1533 * rockchip_drm_wait_vact_end
1534 * @crtc: CRTC to enable line flag
1535 * @mstimeout: millisecond for timeout
1536 *
1537 * Wait for vact_end line flag irq or timeout.
1538 *
1539 * Returns:
1540 * Zero on success, negative errno on failure.
1541 */
1542 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1543 {
1544 struct vop *vop = to_vop(crtc);
1545 unsigned long jiffies_left;
1546 int ret = 0;
1547
1548 if (!crtc || !vop->is_enabled)
1549 return -ENODEV;
1550
1551 mutex_lock(&vop->vop_lock);
1552 if (mstimeout <= 0) {
1553 ret = -EINVAL;
1554 goto out;
1555 }
1556
1557 if (vop_line_flag_irq_is_enabled(vop)) {
1558 ret = -EBUSY;
1559 goto out;
1560 }
1561
1562 reinit_completion(&vop->line_flag_completion);
1563 vop_line_flag_irq_enable(vop);
1564
1565 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1566 msecs_to_jiffies(mstimeout));
1567 vop_line_flag_irq_disable(vop);
1568
1569 if (jiffies_left == 0) {
1570 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1571 ret = -ETIMEDOUT;
1572 goto out;
1573 }
1574
1575 out:
1576 mutex_unlock(&vop->vop_lock);
1577 return ret;
1578 }
1579 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1580
1581 static int vop_bind(struct device *dev, struct device *master, void *data)
1582 {
1583 struct platform_device *pdev = to_platform_device(dev);
1584 const struct vop_data *vop_data;
1585 struct drm_device *drm_dev = data;
1586 struct vop *vop;
1587 struct resource *res;
1588 int ret, irq;
1589
1590 vop_data = of_device_get_match_data(dev);
1591 if (!vop_data)
1592 return -ENODEV;
1593
1594 /* Allocate vop struct and its vop_win array */
1595 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1596 GFP_KERNEL);
1597 if (!vop)
1598 return -ENOMEM;
1599
1600 vop->dev = dev;
1601 vop->data = vop_data;
1602 vop->drm_dev = drm_dev;
1603 dev_set_drvdata(dev, vop);
1604
1605 vop_win_init(vop);
1606
1607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1608 vop->len = resource_size(res);
1609 vop->regs = devm_ioremap_resource(dev, res);
1610 if (IS_ERR(vop->regs))
1611 return PTR_ERR(vop->regs);
1612
1613 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1614 if (!vop->regsbak)
1615 return -ENOMEM;
1616
1617 irq = platform_get_irq(pdev, 0);
1618 if (irq < 0) {
1619 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1620 return irq;
1621 }
1622 vop->irq = (unsigned int)irq;
1623
1624 spin_lock_init(&vop->reg_lock);
1625 spin_lock_init(&vop->irq_lock);
1626 mutex_init(&vop->vop_lock);
1627
1628 ret = vop_create_crtc(vop);
1629 if (ret)
1630 return ret;
1631
1632 pm_runtime_enable(&pdev->dev);
1633
1634 ret = vop_initial(vop);
1635 if (ret < 0) {
1636 DRM_DEV_ERROR(&pdev->dev,
1637 "cannot initial vop dev - err %d\n", ret);
1638 goto err_disable_pm_runtime;
1639 }
1640
1641 ret = devm_request_irq(dev, vop->irq, vop_isr,
1642 IRQF_SHARED, dev_name(dev), vop);
1643 if (ret)
1644 goto err_disable_pm_runtime;
1645
1646 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1647 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1648 if (IS_ERR(vop->rgb)) {
1649 ret = PTR_ERR(vop->rgb);
1650 goto err_disable_pm_runtime;
1651 }
1652 }
1653
1654 return 0;
1655
1656 err_disable_pm_runtime:
1657 pm_runtime_disable(&pdev->dev);
1658 vop_destroy_crtc(vop);
1659 return ret;
1660 }
1661
1662 static void vop_unbind(struct device *dev, struct device *master, void *data)
1663 {
1664 struct vop *vop = dev_get_drvdata(dev);
1665
1666 if (vop->rgb)
1667 rockchip_rgb_fini(vop->rgb);
1668
1669 pm_runtime_disable(dev);
1670 vop_destroy_crtc(vop);
1671
1672 clk_unprepare(vop->aclk);
1673 clk_unprepare(vop->hclk);
1674 clk_unprepare(vop->dclk);
1675 }
1676
1677 const struct component_ops vop_component_ops = {
1678 .bind = vop_bind,
1679 .unbind = vop_unbind,
1680 };
1681 EXPORT_SYMBOL_GPL(vop_component_ops);
Linux with added FPC-III support